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Merge git://git.denx.de/u-boot-marvell
[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
1 /*
2 * (C) Copyright 2015 Google, Inc
3 * (C) 2017 Theobroma Systems Design und Consulting GmbH
4 *
5 * SPDX-License-Identifier: GPL-2.0
6 */
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <dt-structs.h>
12 #include <errno.h>
13 #include <mapmem.h>
14 #include <syscon.h>
15 #include <bitfield.h>
16 #include <asm/io.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cru_rk3399.h>
19 #include <asm/arch/hardware.h>
20 #include <dm/lists.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #if CONFIG_IS_ENABLED(OF_PLATDATA)
26 struct rk3399_clk_plat {
27 struct dtd_rockchip_rk3399_cru dtd;
28 };
29
30 struct rk3399_pmuclk_plat {
31 struct dtd_rockchip_rk3399_pmucru dtd;
32 };
33 #endif
34
35 struct pll_div {
36 u32 refdiv;
37 u32 fbdiv;
38 u32 postdiv1;
39 u32 postdiv2;
40 u32 frac;
41 };
42
43 #define RATE_TO_DIV(input_rate, output_rate) \
44 ((input_rate) / (output_rate) - 1);
45 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
46
47 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
48 .refdiv = _refdiv,\
49 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
50 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
51
52 #if defined(CONFIG_SPL_BUILD)
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
55 #else
56 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
57 #endif
58
59 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
60 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
61
62 static const struct pll_div *apll_l_cfgs[] = {
63 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
64 [APLL_L_600_MHZ] = &apll_l_600_cfg,
65 };
66
67 enum {
68 /* PLL_CON0 */
69 PLL_FBDIV_MASK = 0xfff,
70 PLL_FBDIV_SHIFT = 0,
71
72 /* PLL_CON1 */
73 PLL_POSTDIV2_SHIFT = 12,
74 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
75 PLL_POSTDIV1_SHIFT = 8,
76 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
77 PLL_REFDIV_MASK = 0x3f,
78 PLL_REFDIV_SHIFT = 0,
79
80 /* PLL_CON2 */
81 PLL_LOCK_STATUS_SHIFT = 31,
82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
83 PLL_FRACDIV_MASK = 0xffffff,
84 PLL_FRACDIV_SHIFT = 0,
85
86 /* PLL_CON3 */
87 PLL_MODE_SHIFT = 8,
88 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
89 PLL_MODE_SLOW = 0,
90 PLL_MODE_NORM,
91 PLL_MODE_DEEP,
92 PLL_DSMPD_SHIFT = 3,
93 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
94 PLL_INTEGER_MODE = 1,
95
96 /* PMUCRU_CLKSEL_CON0 */
97 PMU_PCLK_DIV_CON_MASK = 0x1f,
98 PMU_PCLK_DIV_CON_SHIFT = 0,
99
100 /* PMUCRU_CLKSEL_CON1 */
101 SPI3_PLL_SEL_SHIFT = 7,
102 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
103 SPI3_PLL_SEL_24M = 0,
104 SPI3_PLL_SEL_PPLL = 1,
105 SPI3_DIV_CON_SHIFT = 0x0,
106 SPI3_DIV_CON_MASK = 0x7f,
107
108 /* PMUCRU_CLKSEL_CON2 */
109 I2C_DIV_CON_MASK = 0x7f,
110 CLK_I2C8_DIV_CON_SHIFT = 8,
111 CLK_I2C0_DIV_CON_SHIFT = 0,
112
113 /* PMUCRU_CLKSEL_CON3 */
114 CLK_I2C4_DIV_CON_SHIFT = 0,
115
116 /* CLKSEL_CON0 */
117 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
118 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
119 CLK_CORE_L_PLL_SEL_SHIFT = 6,
120 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
121 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
122 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
123 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
124 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
125 CLK_CORE_L_DIV_MASK = 0x1f,
126 CLK_CORE_L_DIV_SHIFT = 0,
127
128 /* CLKSEL_CON1 */
129 PCLK_DBG_L_DIV_SHIFT = 0x8,
130 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
131 ATCLK_CORE_L_DIV_SHIFT = 0,
132 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
133
134 /* CLKSEL_CON14 */
135 PCLK_PERIHP_DIV_CON_SHIFT = 12,
136 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
137 HCLK_PERIHP_DIV_CON_SHIFT = 8,
138 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
139 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
140 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
141 ACLK_PERIHP_PLL_SEL_CPLL = 0,
142 ACLK_PERIHP_PLL_SEL_GPLL = 1,
143 ACLK_PERIHP_DIV_CON_SHIFT = 0,
144 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
145
146 /* CLKSEL_CON21 */
147 ACLK_EMMC_PLL_SEL_SHIFT = 7,
148 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
149 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
150 ACLK_EMMC_DIV_CON_SHIFT = 0,
151 ACLK_EMMC_DIV_CON_MASK = 0x1f,
152
153 /* CLKSEL_CON22 */
154 CLK_EMMC_PLL_SHIFT = 8,
155 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
156 CLK_EMMC_PLL_SEL_GPLL = 0x1,
157 CLK_EMMC_PLL_SEL_24M = 0x5,
158 CLK_EMMC_DIV_CON_SHIFT = 0,
159 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
160
161 /* CLKSEL_CON23 */
162 PCLK_PERILP0_DIV_CON_SHIFT = 12,
163 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
164 HCLK_PERILP0_DIV_CON_SHIFT = 8,
165 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
166 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
167 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
168 ACLK_PERILP0_PLL_SEL_CPLL = 0,
169 ACLK_PERILP0_PLL_SEL_GPLL = 1,
170 ACLK_PERILP0_DIV_CON_SHIFT = 0,
171 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
172
173 /* CLKSEL_CON25 */
174 PCLK_PERILP1_DIV_CON_SHIFT = 8,
175 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
176 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
177 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
178 HCLK_PERILP1_PLL_SEL_CPLL = 0,
179 HCLK_PERILP1_PLL_SEL_GPLL = 1,
180 HCLK_PERILP1_DIV_CON_SHIFT = 0,
181 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
182
183 /* CLKSEL_CON26 */
184 CLK_SARADC_DIV_CON_SHIFT = 8,
185 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
186 CLK_SARADC_DIV_CON_WIDTH = 8,
187
188 /* CLKSEL_CON27 */
189 CLK_TSADC_SEL_X24M = 0x0,
190 CLK_TSADC_SEL_SHIFT = 15,
191 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
192 CLK_TSADC_DIV_CON_SHIFT = 0,
193 CLK_TSADC_DIV_CON_MASK = 0x3ff,
194
195 /* CLKSEL_CON47 & CLKSEL_CON48 */
196 ACLK_VOP_PLL_SEL_SHIFT = 6,
197 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
198 ACLK_VOP_PLL_SEL_CPLL = 0x1,
199 ACLK_VOP_DIV_CON_SHIFT = 0,
200 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
201
202 /* CLKSEL_CON49 & CLKSEL_CON50 */
203 DCLK_VOP_DCLK_SEL_SHIFT = 11,
204 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
205 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
206 DCLK_VOP_PLL_SEL_SHIFT = 8,
207 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
208 DCLK_VOP_PLL_SEL_VPLL = 0,
209 DCLK_VOP_DIV_CON_MASK = 0xff,
210 DCLK_VOP_DIV_CON_SHIFT = 0,
211
212 /* CLKSEL_CON58 */
213 CLK_SPI_PLL_SEL_WIDTH = 1,
214 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
215 CLK_SPI_PLL_SEL_CPLL = 0,
216 CLK_SPI_PLL_SEL_GPLL = 1,
217 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
218 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
219
220 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
221 CLK_SPI5_PLL_SEL_SHIFT = 15,
222
223 /* CLKSEL_CON59 */
224 CLK_SPI1_PLL_SEL_SHIFT = 15,
225 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
226 CLK_SPI0_PLL_SEL_SHIFT = 7,
227 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
228
229 /* CLKSEL_CON60 */
230 CLK_SPI4_PLL_SEL_SHIFT = 15,
231 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
232 CLK_SPI2_PLL_SEL_SHIFT = 7,
233 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
234
235 /* CLKSEL_CON61 */
236 CLK_I2C_PLL_SEL_MASK = 1,
237 CLK_I2C_PLL_SEL_CPLL = 0,
238 CLK_I2C_PLL_SEL_GPLL = 1,
239 CLK_I2C5_PLL_SEL_SHIFT = 15,
240 CLK_I2C5_DIV_CON_SHIFT = 8,
241 CLK_I2C1_PLL_SEL_SHIFT = 7,
242 CLK_I2C1_DIV_CON_SHIFT = 0,
243
244 /* CLKSEL_CON62 */
245 CLK_I2C6_PLL_SEL_SHIFT = 15,
246 CLK_I2C6_DIV_CON_SHIFT = 8,
247 CLK_I2C2_PLL_SEL_SHIFT = 7,
248 CLK_I2C2_DIV_CON_SHIFT = 0,
249
250 /* CLKSEL_CON63 */
251 CLK_I2C7_PLL_SEL_SHIFT = 15,
252 CLK_I2C7_DIV_CON_SHIFT = 8,
253 CLK_I2C3_PLL_SEL_SHIFT = 7,
254 CLK_I2C3_DIV_CON_SHIFT = 0,
255
256 /* CRU_SOFTRST_CON4 */
257 RESETN_DDR0_REQ_SHIFT = 8,
258 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
259 RESETN_DDRPHY0_REQ_SHIFT = 9,
260 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
261 RESETN_DDR1_REQ_SHIFT = 12,
262 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
263 RESETN_DDRPHY1_REQ_SHIFT = 13,
264 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
265 };
266
267 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
268 #define VCO_MIN_KHZ (800 * (MHz / KHz))
269 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
270 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
271
272 /*
273 * the div restructions of pll in integer mode, these are defined in
274 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
275 */
276 #define PLL_DIV_MIN 16
277 #define PLL_DIV_MAX 3200
278
279 /*
280 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
281 * Formulas also embedded within the Fractional PLL Verilog model:
282 * If DSMPD = 1 (DSM is disabled, "integer mode")
283 * FOUTVCO = FREF / REFDIV * FBDIV
284 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
285 * Where:
286 * FOUTVCO = Fractional PLL non-divided output frequency
287 * FOUTPOSTDIV = Fractional PLL divided output frequency
288 * (output of second post divider)
289 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
290 * REFDIV = Fractional PLL input reference clock divider
291 * FBDIV = Integer value programmed into feedback divide
292 *
293 */
294 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
295 {
296 /* All 8 PLLs have same VCO and output frequency range restrictions. */
297 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
298 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
299
300 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
301 "postdiv2=%d, vco=%u khz, output=%u khz\n",
302 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
303 div->postdiv2, vco_khz, output_khz);
304 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
305 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
306 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
307
308 /*
309 * When power on or changing PLL setting,
310 * we must force PLL into slow mode to ensure output stable clock.
311 */
312 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
313 PLL_MODE_SLOW << PLL_MODE_SHIFT);
314
315 /* use integer mode */
316 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
317 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
318
319 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
320 div->fbdiv << PLL_FBDIV_SHIFT);
321 rk_clrsetreg(&pll_con[1],
322 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
323 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
324 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
325 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
326 (div->refdiv << PLL_REFDIV_SHIFT));
327
328 /* waiting for pll lock */
329 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
330 udelay(1);
331
332 /* pll enter normal mode */
333 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
334 PLL_MODE_NORM << PLL_MODE_SHIFT);
335 }
336
337 static int pll_para_config(u32 freq_hz, struct pll_div *div)
338 {
339 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
340 u32 postdiv1, postdiv2 = 1;
341 u32 fref_khz;
342 u32 diff_khz, best_diff_khz;
343 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
344 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
345 u32 vco_khz;
346 u32 freq_khz = freq_hz / KHz;
347
348 if (!freq_hz) {
349 printf("%s: the frequency can't be 0 Hz\n", __func__);
350 return -1;
351 }
352
353 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
354 if (postdiv1 > max_postdiv1) {
355 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
356 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
357 }
358
359 vco_khz = freq_khz * postdiv1 * postdiv2;
360
361 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
362 postdiv2 > max_postdiv2) {
363 printf("%s: Cannot find out a supported VCO"
364 " for Frequency (%uHz).\n", __func__, freq_hz);
365 return -1;
366 }
367
368 div->postdiv1 = postdiv1;
369 div->postdiv2 = postdiv2;
370
371 best_diff_khz = vco_khz;
372 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
373 fref_khz = ref_khz / refdiv;
374
375 fbdiv = vco_khz / fref_khz;
376 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
377 continue;
378 diff_khz = vco_khz - fbdiv * fref_khz;
379 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
380 fbdiv++;
381 diff_khz = fref_khz - diff_khz;
382 }
383
384 if (diff_khz >= best_diff_khz)
385 continue;
386
387 best_diff_khz = diff_khz;
388 div->refdiv = refdiv;
389 div->fbdiv = fbdiv;
390 }
391
392 if (best_diff_khz > 4 * (MHz/KHz)) {
393 printf("%s: Failed to match output frequency %u, "
394 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
395 best_diff_khz * KHz);
396 return -1;
397 }
398 return 0;
399 }
400
401 void rk3399_configure_cpu(struct rk3399_cru *cru,
402 enum apll_l_frequencies apll_l_freq)
403 {
404 u32 aclkm_div;
405 u32 pclk_dbg_div;
406 u32 atclk_div;
407
408 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
409
410 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
411 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
412 aclkm_div < 0x1f);
413
414 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
415 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
416 pclk_dbg_div < 0x1f);
417
418 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
419 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
420 atclk_div < 0x1f);
421
422 rk_clrsetreg(&cru->clksel_con[0],
423 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
424 CLK_CORE_L_DIV_MASK,
425 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
426 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
427 0 << CLK_CORE_L_DIV_SHIFT);
428
429 rk_clrsetreg(&cru->clksel_con[1],
430 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
431 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
432 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
433 }
434 #define I2C_CLK_REG_MASK(bus) \
435 (I2C_DIV_CON_MASK << \
436 CLK_I2C ##bus## _DIV_CON_SHIFT | \
437 CLK_I2C_PLL_SEL_MASK << \
438 CLK_I2C ##bus## _PLL_SEL_SHIFT)
439
440 #define I2C_CLK_REG_VALUE(bus, clk_div) \
441 ((clk_div - 1) << \
442 CLK_I2C ##bus## _DIV_CON_SHIFT | \
443 CLK_I2C_PLL_SEL_GPLL << \
444 CLK_I2C ##bus## _PLL_SEL_SHIFT)
445
446 #define I2C_CLK_DIV_VALUE(con, bus) \
447 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
448 I2C_DIV_CON_MASK;
449
450 #define I2C_PMUCLK_REG_MASK(bus) \
451 (I2C_DIV_CON_MASK << \
452 CLK_I2C ##bus## _DIV_CON_SHIFT)
453
454 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
455 ((clk_div - 1) << \
456 CLK_I2C ##bus## _DIV_CON_SHIFT)
457
458 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
459 {
460 u32 div, con;
461
462 switch (clk_id) {
463 case SCLK_I2C1:
464 con = readl(&cru->clksel_con[61]);
465 div = I2C_CLK_DIV_VALUE(con, 1);
466 break;
467 case SCLK_I2C2:
468 con = readl(&cru->clksel_con[62]);
469 div = I2C_CLK_DIV_VALUE(con, 2);
470 break;
471 case SCLK_I2C3:
472 con = readl(&cru->clksel_con[63]);
473 div = I2C_CLK_DIV_VALUE(con, 3);
474 break;
475 case SCLK_I2C5:
476 con = readl(&cru->clksel_con[61]);
477 div = I2C_CLK_DIV_VALUE(con, 5);
478 break;
479 case SCLK_I2C6:
480 con = readl(&cru->clksel_con[62]);
481 div = I2C_CLK_DIV_VALUE(con, 6);
482 break;
483 case SCLK_I2C7:
484 con = readl(&cru->clksel_con[63]);
485 div = I2C_CLK_DIV_VALUE(con, 7);
486 break;
487 default:
488 printf("do not support this i2c bus\n");
489 return -EINVAL;
490 }
491
492 return DIV_TO_RATE(GPLL_HZ, div);
493 }
494
495 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
496 {
497 int src_clk_div;
498
499 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
500 src_clk_div = GPLL_HZ / hz;
501 assert(src_clk_div - 1 < 127);
502
503 switch (clk_id) {
504 case SCLK_I2C1:
505 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
506 I2C_CLK_REG_VALUE(1, src_clk_div));
507 break;
508 case SCLK_I2C2:
509 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
510 I2C_CLK_REG_VALUE(2, src_clk_div));
511 break;
512 case SCLK_I2C3:
513 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
514 I2C_CLK_REG_VALUE(3, src_clk_div));
515 break;
516 case SCLK_I2C5:
517 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
518 I2C_CLK_REG_VALUE(5, src_clk_div));
519 break;
520 case SCLK_I2C6:
521 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
522 I2C_CLK_REG_VALUE(6, src_clk_div));
523 break;
524 case SCLK_I2C7:
525 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
526 I2C_CLK_REG_VALUE(7, src_clk_div));
527 break;
528 default:
529 printf("do not support this i2c bus\n");
530 return -EINVAL;
531 }
532
533 return rk3399_i2c_get_clk(cru, clk_id);
534 }
535
536 /*
537 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
538 * to select either CPLL or GPLL as the clock-parent. The location within
539 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
540 */
541
542 struct spi_clkreg {
543 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
544 uint8_t div_shift;
545 uint8_t sel_shift;
546 };
547
548 /*
549 * The entries are numbered relative to their offset from SCLK_SPI0.
550 *
551 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
552 * logic is not supported).
553 */
554 static const struct spi_clkreg spi_clkregs[] = {
555 [0] = { .reg = 59,
556 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
557 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
558 [1] = { .reg = 59,
559 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
560 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
561 [2] = { .reg = 60,
562 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
563 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
564 [3] = { .reg = 60,
565 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
566 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
567 [4] = { .reg = 58,
568 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
569 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
570 };
571
572 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
573 {
574 const struct spi_clkreg *spiclk = NULL;
575 u32 div, val;
576
577 switch (clk_id) {
578 case SCLK_SPI0 ... SCLK_SPI5:
579 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
580 break;
581
582 default:
583 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
584 return -EINVAL;
585 }
586
587 val = readl(&cru->clksel_con[spiclk->reg]);
588 div = bitfield_extract(val, spiclk->div_shift,
589 CLK_SPI_PLL_DIV_CON_WIDTH);
590
591 return DIV_TO_RATE(GPLL_HZ, div);
592 }
593
594 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
595 {
596 const struct spi_clkreg *spiclk = NULL;
597 int src_clk_div;
598
599 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
600 assert(src_clk_div < 128);
601
602 switch (clk_id) {
603 case SCLK_SPI1 ... SCLK_SPI5:
604 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
605 break;
606
607 default:
608 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
609 return -EINVAL;
610 }
611
612 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
613 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
614 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
615 ((src_clk_div << spiclk->div_shift) |
616 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
617
618 return rk3399_spi_get_clk(cru, clk_id);
619 }
620
621 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
622 {
623 struct pll_div vpll_config = {0};
624 int aclk_vop = 198*MHz;
625 void *aclkreg_addr, *dclkreg_addr;
626 u32 div;
627
628 switch (clk_id) {
629 case DCLK_VOP0:
630 aclkreg_addr = &cru->clksel_con[47];
631 dclkreg_addr = &cru->clksel_con[49];
632 break;
633 case DCLK_VOP1:
634 aclkreg_addr = &cru->clksel_con[48];
635 dclkreg_addr = &cru->clksel_con[50];
636 break;
637 default:
638 return -EINVAL;
639 }
640 /* vop aclk source clk: cpll */
641 div = CPLL_HZ / aclk_vop;
642 assert(div - 1 < 32);
643
644 rk_clrsetreg(aclkreg_addr,
645 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
646 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
647 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
648
649 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
650 if (pll_para_config(hz, &vpll_config))
651 return -1;
652
653 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
654
655 rk_clrsetreg(dclkreg_addr,
656 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
657 DCLK_VOP_DIV_CON_MASK,
658 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
659 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
660 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
661
662 return hz;
663 }
664
665 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
666 {
667 u32 div, con;
668
669 switch (clk_id) {
670 case HCLK_SDMMC:
671 case SCLK_SDMMC:
672 con = readl(&cru->clksel_con[16]);
673 /* dwmmc controller have internal div 2 */
674 div = 2;
675 break;
676 case SCLK_EMMC:
677 con = readl(&cru->clksel_con[21]);
678 div = 1;
679 break;
680 default:
681 return -EINVAL;
682 }
683
684 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
685 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
686 == CLK_EMMC_PLL_SEL_24M)
687 return DIV_TO_RATE(OSC_HZ, div);
688 else
689 return DIV_TO_RATE(GPLL_HZ, div);
690 }
691
692 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
693 ulong clk_id, ulong set_rate)
694 {
695 int src_clk_div;
696 int aclk_emmc = 198*MHz;
697
698 switch (clk_id) {
699 case HCLK_SDMMC:
700 case SCLK_SDMMC:
701 /* Select clk_sdmmc source from GPLL by default */
702 /* mmc clock defaulg div 2 internal, provide double in cru */
703 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
704
705 if (src_clk_div > 128) {
706 /* use 24MHz source for 400KHz clock */
707 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
708 assert(src_clk_div - 1 < 128);
709 rk_clrsetreg(&cru->clksel_con[16],
710 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
711 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
712 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
713 } else {
714 rk_clrsetreg(&cru->clksel_con[16],
715 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
716 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
717 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
718 }
719 break;
720 case SCLK_EMMC:
721 /* Select aclk_emmc source from GPLL */
722 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
723 assert(src_clk_div - 1 < 32);
724
725 rk_clrsetreg(&cru->clksel_con[21],
726 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
727 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
728 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
729
730 /* Select clk_emmc source from GPLL too */
731 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
732 assert(src_clk_div - 1 < 128);
733
734 rk_clrsetreg(&cru->clksel_con[22],
735 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
736 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
737 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
738 break;
739 default:
740 return -EINVAL;
741 }
742 return rk3399_mmc_get_clk(cru, clk_id);
743 }
744
745 #define PMUSGRF_DDR_RGN_CON16 0xff330040
746 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
747 ulong set_rate)
748 {
749 struct pll_div dpll_cfg;
750
751 /* IC ECO bug, need to set this register */
752 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
753
754 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
755 switch (set_rate) {
756 case 200*MHz:
757 dpll_cfg = (struct pll_div)
758 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
759 break;
760 case 300*MHz:
761 dpll_cfg = (struct pll_div)
762 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
763 break;
764 case 666*MHz:
765 dpll_cfg = (struct pll_div)
766 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
767 break;
768 case 800*MHz:
769 dpll_cfg = (struct pll_div)
770 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
771 break;
772 case 933*MHz:
773 dpll_cfg = (struct pll_div)
774 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
775 break;
776 default:
777 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
778 }
779 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
780
781 return set_rate;
782 }
783
784 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
785 {
786 u32 div, val;
787
788 val = readl(&cru->clksel_con[26]);
789 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
790 CLK_SARADC_DIV_CON_WIDTH);
791
792 return DIV_TO_RATE(OSC_HZ, div);
793 }
794
795 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
796 {
797 int src_clk_div;
798
799 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
800 assert(src_clk_div < 128);
801
802 rk_clrsetreg(&cru->clksel_con[26],
803 CLK_SARADC_DIV_CON_MASK,
804 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
805
806 return rk3399_saradc_get_clk(cru);
807 }
808
809 static ulong rk3399_clk_get_rate(struct clk *clk)
810 {
811 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
812 ulong rate = 0;
813
814 switch (clk->id) {
815 case 0 ... 63:
816 return 0;
817 case HCLK_SDMMC:
818 case SCLK_SDMMC:
819 case SCLK_EMMC:
820 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
821 break;
822 case SCLK_I2C1:
823 case SCLK_I2C2:
824 case SCLK_I2C3:
825 case SCLK_I2C5:
826 case SCLK_I2C6:
827 case SCLK_I2C7:
828 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
829 break;
830 case SCLK_SPI0...SCLK_SPI5:
831 rate = rk3399_spi_get_clk(priv->cru, clk->id);
832 break;
833 case SCLK_UART0:
834 case SCLK_UART2:
835 return 24000000;
836 break;
837 case PCLK_HDMI_CTRL:
838 break;
839 case DCLK_VOP0:
840 case DCLK_VOP1:
841 break;
842 case PCLK_EFUSE1024NS:
843 break;
844 case SCLK_SARADC:
845 rate = rk3399_saradc_get_clk(priv->cru);
846 break;
847 default:
848 return -ENOENT;
849 }
850
851 return rate;
852 }
853
854 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
855 {
856 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
857 ulong ret = 0;
858
859 switch (clk->id) {
860 case 0 ... 63:
861 return 0;
862 case HCLK_SDMMC:
863 case SCLK_SDMMC:
864 case SCLK_EMMC:
865 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
866 break;
867 case SCLK_MAC:
868 /* nothing to do, as this is an external clock */
869 ret = rate;
870 break;
871 case SCLK_I2C1:
872 case SCLK_I2C2:
873 case SCLK_I2C3:
874 case SCLK_I2C5:
875 case SCLK_I2C6:
876 case SCLK_I2C7:
877 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
878 break;
879 case SCLK_SPI0...SCLK_SPI5:
880 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
881 break;
882 case PCLK_HDMI_CTRL:
883 case PCLK_VIO_GRF:
884 /* the PCLK gates for video are enabled by default */
885 break;
886 case DCLK_VOP0:
887 case DCLK_VOP1:
888 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
889 break;
890 case SCLK_DDRCLK:
891 ret = rk3399_ddr_set_clk(priv->cru, rate);
892 break;
893 case PCLK_EFUSE1024NS:
894 break;
895 case SCLK_SARADC:
896 ret = rk3399_saradc_set_clk(priv->cru, rate);
897 break;
898 default:
899 return -ENOENT;
900 }
901
902 return ret;
903 }
904
905 static int rk3399_clk_enable(struct clk *clk)
906 {
907 switch (clk->id) {
908 case HCLK_HOST0:
909 case HCLK_HOST0_ARB:
910 case HCLK_HOST1:
911 case HCLK_HOST1_ARB:
912 return 0;
913 }
914
915 debug("%s: unsupported clk %ld\n", __func__, clk->id);
916 return -ENOENT;
917 }
918
919 static struct clk_ops rk3399_clk_ops = {
920 .get_rate = rk3399_clk_get_rate,
921 .set_rate = rk3399_clk_set_rate,
922 .enable = rk3399_clk_enable,
923 };
924
925 #ifdef CONFIG_SPL_BUILD
926 static void rkclk_init(struct rk3399_cru *cru)
927 {
928 u32 aclk_div;
929 u32 hclk_div;
930 u32 pclk_div;
931
932 rk3399_configure_cpu(cru, APLL_L_600_MHZ);
933 /*
934 * some cru registers changed by bootrom, we'd better reset them to
935 * reset/default values described in TRM to avoid confusion in kernel.
936 * Please consider these three lines as a fix of bootrom bug.
937 */
938 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
939 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
940 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
941
942 /* configure gpll cpll */
943 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
944 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
945
946 /* configure perihp aclk, hclk, pclk */
947 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
948 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
949
950 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
951 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
952 PERIHP_ACLK_HZ && (hclk_div < 0x4));
953
954 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
955 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
956 PERIHP_ACLK_HZ && (pclk_div < 0x7));
957
958 rk_clrsetreg(&cru->clksel_con[14],
959 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
960 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
961 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
962 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
963 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
964 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
965
966 /* configure perilp0 aclk, hclk, pclk */
967 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
968 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
969
970 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
971 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
972 PERILP0_ACLK_HZ && (hclk_div < 0x4));
973
974 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
975 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
976 PERILP0_ACLK_HZ && (pclk_div < 0x7));
977
978 rk_clrsetreg(&cru->clksel_con[23],
979 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
980 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
981 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
982 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
983 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
984 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
985
986 /* perilp1 hclk select gpll as source */
987 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
988 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
989 GPLL_HZ && (hclk_div < 0x1f));
990
991 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
992 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
993 PERILP1_HCLK_HZ && (hclk_div < 0x7));
994
995 rk_clrsetreg(&cru->clksel_con[25],
996 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
997 HCLK_PERILP1_PLL_SEL_MASK,
998 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
999 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1000 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1001 }
1002 #endif
1003
1004 static int rk3399_clk_probe(struct udevice *dev)
1005 {
1006 #ifdef CONFIG_SPL_BUILD
1007 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1008
1009 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1010 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1011
1012 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1013 #endif
1014 rkclk_init(priv->cru);
1015 #endif
1016 return 0;
1017 }
1018
1019 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1020 {
1021 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1022 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1023
1024 priv->cru = dev_read_addr_ptr(dev);
1025 #endif
1026 return 0;
1027 }
1028
1029 static int rk3399_clk_bind(struct udevice *dev)
1030 {
1031 int ret;
1032 struct udevice *sys_child;
1033 struct sysreset_reg *priv;
1034
1035 /* The reset driver does not have a device node, so bind it here */
1036 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1037 &sys_child);
1038 if (ret) {
1039 debug("Warning: No sysreset driver: ret=%d\n", ret);
1040 } else {
1041 priv = malloc(sizeof(struct sysreset_reg));
1042 priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
1043 glb_srst_fst_value);
1044 priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
1045 glb_srst_snd_value);
1046 sys_child->priv = priv;
1047 }
1048
1049 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1050 ret = offsetof(struct rk3399_cru, softrst_con[0]);
1051 ret = rockchip_reset_bind(dev, ret, 21);
1052 if (ret)
1053 debug("Warning: software reset driver bind faile\n");
1054 #endif
1055
1056 return 0;
1057 }
1058
1059 static const struct udevice_id rk3399_clk_ids[] = {
1060 { .compatible = "rockchip,rk3399-cru" },
1061 { }
1062 };
1063
1064 U_BOOT_DRIVER(clk_rk3399) = {
1065 .name = "rockchip_rk3399_cru",
1066 .id = UCLASS_CLK,
1067 .of_match = rk3399_clk_ids,
1068 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1069 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1070 .ops = &rk3399_clk_ops,
1071 .bind = rk3399_clk_bind,
1072 .probe = rk3399_clk_probe,
1073 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1074 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1075 #endif
1076 };
1077
1078 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1079 {
1080 u32 div, con;
1081
1082 switch (clk_id) {
1083 case SCLK_I2C0_PMU:
1084 con = readl(&pmucru->pmucru_clksel[2]);
1085 div = I2C_CLK_DIV_VALUE(con, 0);
1086 break;
1087 case SCLK_I2C4_PMU:
1088 con = readl(&pmucru->pmucru_clksel[3]);
1089 div = I2C_CLK_DIV_VALUE(con, 4);
1090 break;
1091 case SCLK_I2C8_PMU:
1092 con = readl(&pmucru->pmucru_clksel[2]);
1093 div = I2C_CLK_DIV_VALUE(con, 8);
1094 break;
1095 default:
1096 printf("do not support this i2c bus\n");
1097 return -EINVAL;
1098 }
1099
1100 return DIV_TO_RATE(PPLL_HZ, div);
1101 }
1102
1103 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1104 uint hz)
1105 {
1106 int src_clk_div;
1107
1108 src_clk_div = PPLL_HZ / hz;
1109 assert(src_clk_div - 1 < 127);
1110
1111 switch (clk_id) {
1112 case SCLK_I2C0_PMU:
1113 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1114 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1115 break;
1116 case SCLK_I2C4_PMU:
1117 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1118 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1119 break;
1120 case SCLK_I2C8_PMU:
1121 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1122 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1123 break;
1124 default:
1125 printf("do not support this i2c bus\n");
1126 return -EINVAL;
1127 }
1128
1129 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1130 }
1131
1132 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1133 {
1134 u32 div, con;
1135
1136 /* PWM closk rate is same as pclk_pmu */
1137 con = readl(&pmucru->pmucru_clksel[0]);
1138 div = con & PMU_PCLK_DIV_CON_MASK;
1139
1140 return DIV_TO_RATE(PPLL_HZ, div);
1141 }
1142
1143 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1144 {
1145 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1146 ulong rate = 0;
1147
1148 switch (clk->id) {
1149 case PCLK_RKPWM_PMU:
1150 rate = rk3399_pwm_get_clk(priv->pmucru);
1151 break;
1152 case SCLK_I2C0_PMU:
1153 case SCLK_I2C4_PMU:
1154 case SCLK_I2C8_PMU:
1155 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1156 break;
1157 default:
1158 return -ENOENT;
1159 }
1160
1161 return rate;
1162 }
1163
1164 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1165 {
1166 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1167 ulong ret = 0;
1168
1169 switch (clk->id) {
1170 case SCLK_I2C0_PMU:
1171 case SCLK_I2C4_PMU:
1172 case SCLK_I2C8_PMU:
1173 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1174 break;
1175 default:
1176 return -ENOENT;
1177 }
1178
1179 return ret;
1180 }
1181
1182 static struct clk_ops rk3399_pmuclk_ops = {
1183 .get_rate = rk3399_pmuclk_get_rate,
1184 .set_rate = rk3399_pmuclk_set_rate,
1185 };
1186
1187 #ifndef CONFIG_SPL_BUILD
1188 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1189 {
1190 u32 pclk_div;
1191
1192 /* configure pmu pll(ppll) */
1193 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1194
1195 /* configure pmu pclk */
1196 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1197 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1198 PMU_PCLK_DIV_CON_MASK,
1199 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1200 }
1201 #endif
1202
1203 static int rk3399_pmuclk_probe(struct udevice *dev)
1204 {
1205 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1206 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1207 #endif
1208
1209 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1210 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1211
1212 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1213 #endif
1214
1215 #ifndef CONFIG_SPL_BUILD
1216 pmuclk_init(priv->pmucru);
1217 #endif
1218 return 0;
1219 }
1220
1221 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1222 {
1223 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1224 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1225
1226 priv->pmucru = dev_read_addr_ptr(dev);
1227 #endif
1228 return 0;
1229 }
1230
1231 static int rk3399_pmuclk_bind(struct udevice *dev)
1232 {
1233 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1234 int ret;
1235
1236 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1237 ret = rockchip_reset_bind(dev, ret, 2);
1238 if (ret)
1239 debug("Warning: software reset driver bind faile\n");
1240 #endif
1241 return 0;
1242 }
1243
1244 static const struct udevice_id rk3399_pmuclk_ids[] = {
1245 { .compatible = "rockchip,rk3399-pmucru" },
1246 { }
1247 };
1248
1249 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1250 .name = "rockchip_rk3399_pmucru",
1251 .id = UCLASS_CLK,
1252 .of_match = rk3399_pmuclk_ids,
1253 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1254 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1255 .ops = &rk3399_pmuclk_ops,
1256 .probe = rk3399_pmuclk_probe,
1257 .bind = rk3399_pmuclk_bind,
1258 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1259 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1260 #endif
1261 };
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