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clock: rk3399: add support for dwmmc 400K
[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <syscon.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3399.h>
15 #include <asm/arch/hardware.h>
16 #include <dm/lists.h>
17 #include <dt-bindings/clock/rk3399-cru.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 struct rk3399_clk_priv {
22 struct rk3399_cru *cru;
23 ulong rate;
24 };
25
26 struct pll_div {
27 u32 refdiv;
28 u32 fbdiv;
29 u32 postdiv1;
30 u32 postdiv2;
31 u32 frac;
32 };
33
34 #define RATE_TO_DIV(input_rate, output_rate) \
35 ((input_rate) / (output_rate) - 1);
36 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
37
38 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
39 .refdiv = _refdiv,\
40 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
41 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
42
43 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
44 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
45 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
46
47 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
48 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
49
50 static const struct pll_div *apll_l_cfgs[] = {
51 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
52 [APLL_L_600_MHZ] = &apll_l_600_cfg,
53 };
54
55 enum {
56 /* PLL_CON0 */
57 PLL_FBDIV_MASK = 0xfff,
58 PLL_FBDIV_SHIFT = 0,
59
60 /* PLL_CON1 */
61 PLL_POSTDIV2_SHIFT = 12,
62 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
63 PLL_POSTDIV1_SHIFT = 8,
64 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
65 PLL_REFDIV_MASK = 0x3f,
66 PLL_REFDIV_SHIFT = 0,
67
68 /* PLL_CON2 */
69 PLL_LOCK_STATUS_SHIFT = 31,
70 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
71 PLL_FRACDIV_MASK = 0xffffff,
72 PLL_FRACDIV_SHIFT = 0,
73
74 /* PLL_CON3 */
75 PLL_MODE_SHIFT = 8,
76 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
77 PLL_MODE_SLOW = 0,
78 PLL_MODE_NORM,
79 PLL_MODE_DEEP,
80 PLL_DSMPD_SHIFT = 3,
81 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
82 PLL_INTEGER_MODE = 1,
83
84 /* PMUCRU_CLKSEL_CON0 */
85 PMU_PCLK_DIV_CON_MASK = 0x1f,
86 PMU_PCLK_DIV_CON_SHIFT = 0,
87
88 /* PMUCRU_CLKSEL_CON1 */
89 SPI3_PLL_SEL_SHIFT = 7,
90 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
91 SPI3_PLL_SEL_24M = 0,
92 SPI3_PLL_SEL_PPLL = 1,
93 SPI3_DIV_CON_SHIFT = 0x0,
94 SPI3_DIV_CON_MASK = 0x7f,
95
96 /* PMUCRU_CLKSEL_CON2 */
97 I2C_DIV_CON_MASK = 0x7f,
98 I2C8_DIV_CON_SHIFT = 8,
99 I2C0_DIV_CON_SHIFT = 0,
100
101 /* PMUCRU_CLKSEL_CON3 */
102 I2C4_DIV_CON_SHIFT = 0,
103
104 /* CLKSEL_CON0 */
105 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
106 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
107 CLK_CORE_L_PLL_SEL_SHIFT = 6,
108 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
109 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
110 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
111 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
112 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
113 CLK_CORE_L_DIV_MASK = 0x1f,
114 CLK_CORE_L_DIV_SHIFT = 0,
115
116 /* CLKSEL_CON1 */
117 PCLK_DBG_L_DIV_SHIFT = 0x8,
118 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
119 ATCLK_CORE_L_DIV_SHIFT = 0,
120 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
121
122 /* CLKSEL_CON14 */
123 PCLK_PERIHP_DIV_CON_SHIFT = 12,
124 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
125 HCLK_PERIHP_DIV_CON_SHIFT = 8,
126 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
127 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
128 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
129 ACLK_PERIHP_PLL_SEL_CPLL = 0,
130 ACLK_PERIHP_PLL_SEL_GPLL = 1,
131 ACLK_PERIHP_DIV_CON_SHIFT = 0,
132 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
133
134 /* CLKSEL_CON21 */
135 ACLK_EMMC_PLL_SEL_SHIFT = 7,
136 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
137 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
138 ACLK_EMMC_DIV_CON_SHIFT = 0,
139 ACLK_EMMC_DIV_CON_MASK = 0x1f,
140
141 /* CLKSEL_CON22 */
142 CLK_EMMC_PLL_SHIFT = 8,
143 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
144 CLK_EMMC_PLL_SEL_GPLL = 0x1,
145 CLK_EMMC_PLL_SEL_24M = 0x5,
146 CLK_EMMC_DIV_CON_SHIFT = 0,
147 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
148
149 /* CLKSEL_CON23 */
150 PCLK_PERILP0_DIV_CON_SHIFT = 12,
151 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
152 HCLK_PERILP0_DIV_CON_SHIFT = 8,
153 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
154 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
155 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
156 ACLK_PERILP0_PLL_SEL_CPLL = 0,
157 ACLK_PERILP0_PLL_SEL_GPLL = 1,
158 ACLK_PERILP0_DIV_CON_SHIFT = 0,
159 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
160
161 /* CLKSEL_CON25 */
162 PCLK_PERILP1_DIV_CON_SHIFT = 8,
163 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
164 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
165 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
166 HCLK_PERILP1_PLL_SEL_CPLL = 0,
167 HCLK_PERILP1_PLL_SEL_GPLL = 1,
168 HCLK_PERILP1_DIV_CON_SHIFT = 0,
169 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
170
171 /* CLKSEL_CON26 */
172 CLK_SARADC_DIV_CON_SHIFT = 8,
173 CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT,
174
175 /* CLKSEL_CON27 */
176 CLK_TSADC_SEL_X24M = 0x0,
177 CLK_TSADC_SEL_SHIFT = 15,
178 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
179 CLK_TSADC_DIV_CON_SHIFT = 0,
180 CLK_TSADC_DIV_CON_MASK = 0x3ff,
181
182 /* CLKSEL_CON47 & CLKSEL_CON48 */
183 ACLK_VOP_PLL_SEL_SHIFT = 6,
184 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
185 ACLK_VOP_PLL_SEL_CPLL = 0x1,
186 ACLK_VOP_DIV_CON_SHIFT = 0,
187 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
188
189 /* CLKSEL_CON49 & CLKSEL_CON50 */
190 DCLK_VOP_DCLK_SEL_SHIFT = 11,
191 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
192 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
193 DCLK_VOP_PLL_SEL_SHIFT = 8,
194 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
195 DCLK_VOP_PLL_SEL_VPLL = 0,
196 DCLK_VOP_DIV_CON_MASK = 0xff,
197 DCLK_VOP_DIV_CON_SHIFT = 0,
198
199 /* CLKSEL_CON58 */
200 CLK_SPI_PLL_SEL_MASK = 1,
201 CLK_SPI_PLL_SEL_CPLL = 0,
202 CLK_SPI_PLL_SEL_GPLL = 1,
203 CLK_SPI_PLL_DIV_CON_MASK = 0x7f,
204 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
205 CLK_SPI5_PLL_SEL_SHIFT = 15,
206
207 /* CLKSEL_CON59 */
208 CLK_SPI1_PLL_SEL_SHIFT = 15,
209 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
210 CLK_SPI0_PLL_SEL_SHIFT = 7,
211 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
212
213 /* CLKSEL_CON60 */
214 CLK_SPI4_PLL_SEL_SHIFT = 15,
215 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
216 CLK_SPI2_PLL_SEL_SHIFT = 7,
217 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
218
219 /* CLKSEL_CON61 */
220 CLK_I2C_PLL_SEL_MASK = 1,
221 CLK_I2C_PLL_SEL_CPLL = 0,
222 CLK_I2C_PLL_SEL_GPLL = 1,
223 CLK_I2C5_PLL_SEL_SHIFT = 15,
224 CLK_I2C5_DIV_CON_SHIFT = 8,
225 CLK_I2C1_PLL_SEL_SHIFT = 7,
226 CLK_I2C1_DIV_CON_SHIFT = 0,
227
228 /* CLKSEL_CON62 */
229 CLK_I2C6_PLL_SEL_SHIFT = 15,
230 CLK_I2C6_DIV_CON_SHIFT = 8,
231 CLK_I2C2_PLL_SEL_SHIFT = 7,
232 CLK_I2C2_DIV_CON_SHIFT = 0,
233
234 /* CLKSEL_CON63 */
235 CLK_I2C7_PLL_SEL_SHIFT = 15,
236 CLK_I2C7_DIV_CON_SHIFT = 8,
237 CLK_I2C3_PLL_SEL_SHIFT = 7,
238 CLK_I2C3_DIV_CON_SHIFT = 0,
239
240 /* CRU_SOFTRST_CON4 */
241 RESETN_DDR0_REQ_SHIFT = 8,
242 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
243 RESETN_DDRPHY0_REQ_SHIFT = 9,
244 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
245 RESETN_DDR1_REQ_SHIFT = 12,
246 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
247 RESETN_DDRPHY1_REQ_SHIFT = 13,
248 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
249 };
250
251 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
252 #define VCO_MIN_KHZ (800 * (MHz / KHz))
253 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
254 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
255
256 /*
257 * the div restructions of pll in integer mode, these are defined in
258 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
259 */
260 #define PLL_DIV_MIN 16
261 #define PLL_DIV_MAX 3200
262
263 /*
264 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
265 * Formulas also embedded within the Fractional PLL Verilog model:
266 * If DSMPD = 1 (DSM is disabled, "integer mode")
267 * FOUTVCO = FREF / REFDIV * FBDIV
268 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
269 * Where:
270 * FOUTVCO = Fractional PLL non-divided output frequency
271 * FOUTPOSTDIV = Fractional PLL divided output frequency
272 * (output of second post divider)
273 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
274 * REFDIV = Fractional PLL input reference clock divider
275 * FBDIV = Integer value programmed into feedback divide
276 *
277 */
278 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
279 {
280 /* All 8 PLLs have same VCO and output frequency range restrictions. */
281 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
282 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
283
284 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
285 "postdiv2=%d, vco=%u khz, output=%u khz\n",
286 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
287 div->postdiv2, vco_khz, output_khz);
288 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
289 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
290 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
291
292 /*
293 * When power on or changing PLL setting,
294 * we must force PLL into slow mode to ensure output stable clock.
295 */
296 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
297 PLL_MODE_SLOW << PLL_MODE_SHIFT);
298
299 /* use integer mode */
300 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
301 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
302
303 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
304 div->fbdiv << PLL_FBDIV_SHIFT);
305 rk_clrsetreg(&pll_con[1],
306 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
307 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
308 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
309 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
310 (div->refdiv << PLL_REFDIV_SHIFT));
311
312 /* waiting for pll lock */
313 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
314 udelay(1);
315
316 /* pll enter normal mode */
317 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
318 PLL_MODE_NORM << PLL_MODE_SHIFT);
319 }
320
321 static int pll_para_config(u32 freq_hz, struct pll_div *div)
322 {
323 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
324 u32 postdiv1, postdiv2 = 1;
325 u32 fref_khz;
326 u32 diff_khz, best_diff_khz;
327 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
328 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
329 u32 vco_khz;
330 u32 freq_khz = freq_hz / KHz;
331
332 if (!freq_hz) {
333 printf("%s: the frequency can't be 0 Hz\n", __func__);
334 return -1;
335 }
336
337 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
338 if (postdiv1 > max_postdiv1) {
339 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
340 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
341 }
342
343 vco_khz = freq_khz * postdiv1 * postdiv2;
344
345 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
346 postdiv2 > max_postdiv2) {
347 printf("%s: Cannot find out a supported VCO"
348 " for Frequency (%uHz).\n", __func__, freq_hz);
349 return -1;
350 }
351
352 div->postdiv1 = postdiv1;
353 div->postdiv2 = postdiv2;
354
355 best_diff_khz = vco_khz;
356 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
357 fref_khz = ref_khz / refdiv;
358
359 fbdiv = vco_khz / fref_khz;
360 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
361 continue;
362 diff_khz = vco_khz - fbdiv * fref_khz;
363 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
364 fbdiv++;
365 diff_khz = fref_khz - diff_khz;
366 }
367
368 if (diff_khz >= best_diff_khz)
369 continue;
370
371 best_diff_khz = diff_khz;
372 div->refdiv = refdiv;
373 div->fbdiv = fbdiv;
374 }
375
376 if (best_diff_khz > 4 * (MHz/KHz)) {
377 printf("%s: Failed to match output frequency %u, "
378 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
379 best_diff_khz * KHz);
380 return -1;
381 }
382 return 0;
383 }
384
385 static void rkclk_init(struct rk3399_cru *cru)
386 {
387 u32 aclk_div;
388 u32 hclk_div;
389 u32 pclk_div;
390
391 /*
392 * some cru registers changed by bootrom, we'd better reset them to
393 * reset/default values described in TRM to avoid confusion in kernel.
394 * Please consider these three lines as a fix of bootrom bug.
395 */
396 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
397 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
398 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
399
400 /* configure gpll cpll */
401 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
402 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
403
404 /* configure perihp aclk, hclk, pclk */
405 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
406 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
407
408 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
409 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
410 PERIHP_ACLK_HZ && (hclk_div < 0x4));
411
412 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
413 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
414 PERIHP_ACLK_HZ && (pclk_div < 0x7));
415
416 rk_clrsetreg(&cru->clksel_con[14],
417 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
418 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
419 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
420 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
421 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
422 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
423
424 /* configure perilp0 aclk, hclk, pclk */
425 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
426 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
427
428 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
429 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
430 PERILP0_ACLK_HZ && (hclk_div < 0x4));
431
432 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
433 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
434 PERILP0_ACLK_HZ && (pclk_div < 0x7));
435
436 rk_clrsetreg(&cru->clksel_con[23],
437 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
438 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
439 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
440 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
441 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
442 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
443
444 /* perilp1 hclk select gpll as source */
445 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
446 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
447 GPLL_HZ && (hclk_div < 0x1f));
448
449 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
450 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
451 PERILP1_HCLK_HZ && (hclk_div < 0x7));
452
453 rk_clrsetreg(&cru->clksel_con[25],
454 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
455 HCLK_PERILP1_PLL_SEL_MASK,
456 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
457 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
458 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
459 }
460
461 void rk3399_configure_cpu(struct rk3399_cru *cru,
462 enum apll_l_frequencies apll_l_freq)
463 {
464 u32 aclkm_div;
465 u32 pclk_dbg_div;
466 u32 atclk_div;
467
468 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
469
470 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
471 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
472 aclkm_div < 0x1f);
473
474 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
475 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
476 pclk_dbg_div < 0x1f);
477
478 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
479 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
480 atclk_div < 0x1f);
481
482 rk_clrsetreg(&cru->clksel_con[0],
483 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
484 CLK_CORE_L_DIV_MASK,
485 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
486 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
487 0 << CLK_CORE_L_DIV_SHIFT);
488
489 rk_clrsetreg(&cru->clksel_con[1],
490 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
491 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
492 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
493 }
494 #define I2C_CLK_REG_MASK(bus) \
495 (I2C_DIV_CON_MASK << \
496 CLK_I2C ##bus## _DIV_CON_SHIFT | \
497 CLK_I2C_PLL_SEL_MASK << \
498 CLK_I2C ##bus## _PLL_SEL_SHIFT)
499
500 #define I2C_CLK_REG_VALUE(bus, clk_div) \
501 ((clk_div - 1) << \
502 CLK_I2C ##bus## _DIV_CON_SHIFT | \
503 CLK_I2C_PLL_SEL_GPLL << \
504 CLK_I2C ##bus## _PLL_SEL_SHIFT)
505
506 #define I2C_CLK_DIV_VALUE(con, bus) \
507 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
508 I2C_DIV_CON_MASK;
509
510 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
511 {
512 u32 div, con;
513
514 switch (clk_id) {
515 case SCLK_I2C1:
516 con = readl(&cru->clksel_con[61]);
517 div = I2C_CLK_DIV_VALUE(con, 1);
518 break;
519 case SCLK_I2C2:
520 con = readl(&cru->clksel_con[62]);
521 div = I2C_CLK_DIV_VALUE(con, 2);
522 break;
523 case SCLK_I2C3:
524 con = readl(&cru->clksel_con[63]);
525 div = I2C_CLK_DIV_VALUE(con, 3);
526 break;
527 case SCLK_I2C5:
528 con = readl(&cru->clksel_con[61]);
529 div = I2C_CLK_DIV_VALUE(con, 5);
530 break;
531 case SCLK_I2C6:
532 con = readl(&cru->clksel_con[62]);
533 div = I2C_CLK_DIV_VALUE(con, 6);
534 break;
535 case SCLK_I2C7:
536 con = readl(&cru->clksel_con[63]);
537 div = I2C_CLK_DIV_VALUE(con, 7);
538 break;
539 default:
540 printf("do not support this i2c bus\n");
541 return -EINVAL;
542 }
543
544 return DIV_TO_RATE(GPLL_HZ, div);
545 }
546
547 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
548 {
549 int src_clk_div;
550
551 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
552 src_clk_div = GPLL_HZ / hz;
553 assert(src_clk_div - 1 < 127);
554
555 switch (clk_id) {
556 case SCLK_I2C1:
557 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
558 I2C_CLK_REG_VALUE(1, src_clk_div));
559 break;
560 case SCLK_I2C2:
561 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
562 I2C_CLK_REG_VALUE(2, src_clk_div));
563 break;
564 case SCLK_I2C3:
565 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
566 I2C_CLK_REG_VALUE(3, src_clk_div));
567 break;
568 case SCLK_I2C5:
569 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
570 I2C_CLK_REG_VALUE(5, src_clk_div));
571 break;
572 case SCLK_I2C6:
573 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
574 I2C_CLK_REG_VALUE(6, src_clk_div));
575 break;
576 case SCLK_I2C7:
577 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
578 I2C_CLK_REG_VALUE(7, src_clk_div));
579 break;
580 default:
581 printf("do not support this i2c bus\n");
582 return -EINVAL;
583 }
584
585 return DIV_TO_RATE(GPLL_HZ, src_clk_div);
586 }
587
588 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
589 {
590 struct pll_div vpll_config = {0};
591 int aclk_vop = 198*MHz;
592 void *aclkreg_addr, *dclkreg_addr;
593 u32 div;
594
595 switch (clk_id) {
596 case DCLK_VOP0:
597 aclkreg_addr = &cru->clksel_con[47];
598 dclkreg_addr = &cru->clksel_con[49];
599 break;
600 case DCLK_VOP1:
601 aclkreg_addr = &cru->clksel_con[48];
602 dclkreg_addr = &cru->clksel_con[50];
603 break;
604 default:
605 return -EINVAL;
606 }
607 /* vop aclk source clk: cpll */
608 div = CPLL_HZ / aclk_vop;
609 assert(div - 1 < 32);
610
611 rk_clrsetreg(aclkreg_addr,
612 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
613 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
614 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
615
616 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
617 if (pll_para_config(hz, &vpll_config))
618 return -1;
619
620 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
621
622 rk_clrsetreg(dclkreg_addr,
623 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
624 DCLK_VOP_DIV_CON_MASK,
625 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
626 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
627 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
628
629 return hz;
630 }
631
632 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
633 {
634 u32 div, con;
635
636 switch (clk_id) {
637 case SCLK_SDMMC:
638 con = readl(&cru->clksel_con[16]);
639 break;
640 case SCLK_EMMC:
641 con = readl(&cru->clksel_con[21]);
642 break;
643 default:
644 return -EINVAL;
645 }
646 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
647
648 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
649 == CLK_EMMC_PLL_SEL_24M)
650 return DIV_TO_RATE(24*1024*1024, div);
651 else
652 return DIV_TO_RATE(GPLL_HZ, div);
653 }
654
655 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
656 ulong clk_id, ulong set_rate)
657 {
658 int src_clk_div;
659 int aclk_emmc = 198*MHz;
660
661 switch (clk_id) {
662 case SCLK_SDMMC:
663 /* Select clk_sdmmc source from GPLL by default */
664 src_clk_div = GPLL_HZ / set_rate;
665
666 if (src_clk_div > 127) {
667 /* use 24MHz source for 400KHz clock */
668 src_clk_div = 24*1024*1024 / set_rate;
669 rk_clrsetreg(&cru->clksel_con[16],
670 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
671 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
672 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
673 } else {
674 rk_clrsetreg(&cru->clksel_con[16],
675 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
676 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
677 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
678 }
679 break;
680 case SCLK_EMMC:
681 /* Select aclk_emmc source from GPLL */
682 src_clk_div = GPLL_HZ / aclk_emmc;
683 assert(src_clk_div - 1 < 31);
684
685 rk_clrsetreg(&cru->clksel_con[21],
686 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
687 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
688 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
689
690 /* Select clk_emmc source from GPLL too */
691 src_clk_div = GPLL_HZ / set_rate;
692 assert(src_clk_div - 1 < 127);
693
694 rk_clrsetreg(&cru->clksel_con[22],
695 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
696 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
697 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
698 break;
699 default:
700 return -EINVAL;
701 }
702 return rk3399_mmc_get_clk(cru, clk_id);
703 }
704
705 static ulong rk3399_clk_get_rate(struct clk *clk)
706 {
707 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
708 ulong rate = 0;
709
710 switch (clk->id) {
711 case 0 ... 63:
712 return 0;
713 case SCLK_SDMMC:
714 case SCLK_EMMC:
715 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
716 break;
717 case SCLK_I2C1:
718 case SCLK_I2C2:
719 case SCLK_I2C3:
720 case SCLK_I2C5:
721 case SCLK_I2C6:
722 case SCLK_I2C7:
723 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
724 break;
725 case DCLK_VOP0:
726 case DCLK_VOP1:
727 break;
728 default:
729 return -ENOENT;
730 }
731
732 return rate;
733 }
734
735 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
736 {
737 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
738 ulong ret = 0;
739
740 switch (clk->id) {
741 case 0 ... 63:
742 return 0;
743 case SCLK_SDMMC:
744 case SCLK_EMMC:
745 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
746 break;
747 case SCLK_I2C1:
748 case SCLK_I2C2:
749 case SCLK_I2C3:
750 case SCLK_I2C5:
751 case SCLK_I2C6:
752 case SCLK_I2C7:
753 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
754 break;
755 case DCLK_VOP0:
756 case DCLK_VOP1:
757 rate = rk3399_vop_set_clk(priv->cru, clk->id, rate);
758 break;
759 default:
760 return -ENOENT;
761 }
762
763 return ret;
764 }
765
766 static struct clk_ops rk3399_clk_ops = {
767 .get_rate = rk3399_clk_get_rate,
768 .set_rate = rk3399_clk_set_rate,
769 };
770
771 void *rockchip_get_cru(void)
772 {
773 struct udevice *dev;
774 fdt_addr_t *addr;
775 int ret;
776
777 ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev);
778 if (ret)
779 return ERR_PTR(ret);
780
781 addr = dev_get_addr_ptr(dev);
782 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
783 return ERR_PTR(-EINVAL);
784
785 return addr;
786 }
787
788 static int rk3399_clk_probe(struct udevice *dev)
789 {
790 struct rk3399_clk_priv *priv = dev_get_priv(dev);
791
792 rkclk_init(priv->cru);
793
794 return 0;
795 }
796
797 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
798 {
799 struct rk3399_clk_priv *priv = dev_get_priv(dev);
800
801 priv->cru = (struct rk3399_cru *)dev_get_addr(dev);
802
803 return 0;
804 }
805
806 static int rk3399_clk_bind(struct udevice *dev)
807 {
808 int ret;
809
810 /* The reset driver does not have a device node, so bind it here */
811 ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev);
812 if (ret)
813 printf("Warning: No RK3399 reset driver: ret=%d\n", ret);
814
815 return 0;
816 }
817
818 static const struct udevice_id rk3399_clk_ids[] = {
819 { .compatible = "rockchip,rk3399-cru" },
820 { }
821 };
822
823 U_BOOT_DRIVER(clk_rk3399) = {
824 .name = "clk_rk3399",
825 .id = UCLASS_CLK,
826 .of_match = rk3399_clk_ids,
827 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
828 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
829 .ops = &rk3399_clk_ops,
830 .bind = rk3399_clk_bind,
831 .probe = rk3399_clk_probe,
832 };
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