drivers/i2c/ppc4xx_i2c.c

   1 /*
   2  * (C) Copyright 2007-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
   6  *
   7  * (C) Copyright 2001
   8  * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  *
  12  * NOTE: This driver should be converted to driver model before June 2017.
  13  * Please see doc/driver-model/i2c-howto.txt for instructions.
  14  */
  15
  16 #include <common.h>
  17 #include <asm/ppc4xx.h>
  18 #include <asm/ppc4xx-i2c.h>
  19 #include <i2c.h>
  20 #include <asm/io.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
  25 {
  26         unsigned long base;
  27
  28 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  29         defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  30         defined(CONFIG_460EX) || defined(CONFIG_460GT)
  31         base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
  32 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
  33 /* all remaining 440 variants */
  34         base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
  35 #else
  36 /* all 405 variants */
  37         base = 0xEF600500 + (hwadapnr * 0x100);
  38 #endif
  39         return (struct ppc4xx_i2c *)base;
  40 }
  41
  42 static void _i2c_bus_reset(struct i2c_adapter *adap)
  43 {
  44         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
  45         int i;
  46         u8 dc;
  47
  48         /* Reset status register */
  49         /* write 1 in SCMP and IRQA to clear these fields */
  50         out_8(&i2c->sts, 0x0A);
  51
  52         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  53         out_8(&i2c->extsts, 0x8F);
  54
  55         /* Place chip in the reset state */
  56         out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
  57
  58         /* Check if bus is free */
  59         dc = in_8(&i2c->directcntl);
  60         if (!DIRCTNL_FREE(dc)){
  61                 /* Try to set bus free state */
  62                 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
  63
  64                 /* Wait until we regain bus control */
  65                 for (i = 0; i < 100; ++i) {
  66                         dc = in_8(&i2c->directcntl);
  67                         if (DIRCTNL_FREE(dc))
  68                                 break;
  69
  70                         /* Toggle SCL line */
  71                         dc ^= IIC_DIRCNTL_SCC;
  72                         out_8(&i2c->directcntl, dc);
  73                         udelay(10);
  74                         dc ^= IIC_DIRCNTL_SCC;
  75                         out_8(&i2c->directcntl, dc);
  76                 }
  77         }
  78
  79         /* Remove reset */
  80         out_8(&i2c->xtcntlss, 0);
  81 }
  82
  83 static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  84 {
  85         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
  86         int val, divisor;
  87
  88 #ifdef CONFIG_SYS_I2C_INIT_BOARD
  89         /*
  90          * Call board specific i2c bus reset routine before accessing the
  91          * environment, which might be in a chip on that bus. For details
  92          * about this problem see doc/I2C_Edge_Conditions.
  93          */
  94         i2c_init_board();
  95 #endif
  96
  97         /* Handle possible failed I2C state */
  98         /* FIXME: put this into i2c_init_board()? */
  99         _i2c_bus_reset(adap);
 100
 101         /* clear lo master address */
 102         out_8(&i2c->lmadr, 0);
 103
 104         /* clear hi master address */
 105         out_8(&i2c->hmadr, 0);
 106
 107         /* clear lo slave address */
 108         out_8(&i2c->lsadr, 0);
 109
 110         /* clear hi slave address */
 111         out_8(&i2c->hsadr, 0);
 112
 113         /* Clock divide Register */
 114         /* set divisor according to freq_opb */
 115         divisor = (get_OPB_freq() - 1) / 10000000;
 116         if (divisor == 0)
 117                 divisor = 1;
 118         out_8(&i2c->clkdiv, divisor);
 119
 120         /* no interrupts */
 121         out_8(&i2c->intrmsk, 0);
 122
 123         /* clear transfer count */
 124         out_8(&i2c->xfrcnt, 0);
 125
 126         /* clear extended control & stat */
 127         /* write 1 in SRC SRS SWC SWS to clear these fields */
 128         out_8(&i2c->xtcntlss, 0xF0);
 129
 130         /* Mode Control Register
 131            Flush Slave/Master data buffer */
 132         out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 133
 134         val = in_8(&i2c->mdcntl);
 135
 136         /* Ignore General Call, slave transfers are ignored,
 137          * disable interrupts, exit unknown bus state, enable hold
 138          * SCL 100kHz normaly or FastMode for 400kHz and above
 139          */
 140
 141         val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
 142         if (speed >= 400000)
 143                 val |= IIC_MDCNTL_FSM;
 144         out_8(&i2c->mdcntl, val);
 145
 146         /* clear control reg */
 147         out_8(&i2c->cntl, 0x00);
 148 }
 149
 150 /*
 151  * This code tries to use the features of the 405GP i2c
 152  * controller. It will transfer up to 4 bytes in one pass
 153  * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
 154  * is possible to do out16(lhz) transfers.
 155  *
 156  * cmd_type is 0 for write 1 for read.
 157  *
 158  * addr_len can take any value from 0-255, it is only limited
 159  * by the char, we could make it larger if needed. If it is
 160  * 0 we skip the address write cycle.
 161  *
 162  * Typical case is a Write of an addr followd by a Read. The
 163  * IBM FAQ does not cover this. On the last byte of the write
 164  * we don't set the creg CHT bit but the RPST bit.
 165  *
 166  * It does not support address only transfers, there must be
 167  * a data part. If you want to write the address yourself, put
 168  * it in the data pointer.
 169  *
 170  * It does not support transfer to/from address 0.
 171  *
 172  * It does not check XFRCNT.
 173  */
 174 static int _i2c_transfer(struct i2c_adapter *adap,
 175                         unsigned char cmd_type,
 176                         unsigned char chip,
 177                         unsigned char addr[],
 178                         unsigned char addr_len,
 179                         unsigned char data[],
 180                         unsigned short data_len)
 181 {
 182         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
 183         u8 *ptr;
 184         int reading;
 185         int tran, cnt;
 186         int result;
 187         int status;
 188         int i;
 189         u8 creg;
 190
 191         if (data == 0 || data_len == 0) {
 192                 /* Don't support data transfer of no length or to address 0 */
 193                 printf( "i2c_transfer: bad call\n" );
 194                 return IIC_NOK;
 195         }
 196         if (addr && addr_len) {
 197                 ptr = addr;
 198                 cnt = addr_len;
 199                 reading = 0;
 200         } else {
 201                 ptr = data;
 202                 cnt = data_len;
 203                 reading = cmd_type;
 204         }
 205
 206         /* Clear Stop Complete Bit */
 207         out_8(&i2c->sts, IIC_STS_SCMP);
 208
 209         /* Check init */
 210         i = 10;
 211         do {
 212                 /* Get status */
 213                 status = in_8(&i2c->sts);
 214                 i--;
 215         } while ((status & IIC_STS_PT) && (i > 0));
 216
 217         if (status & IIC_STS_PT) {
 218                 result = IIC_NOK_TOUT;
 219                 return(result);
 220         }
 221
 222         /* flush the Master/Slave Databuffers */
 223         out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
 224               IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
 225
 226         /* need to wait 4 OPB clocks? code below should take that long */
 227
 228         /* 7-bit adressing */
 229         out_8(&i2c->hmadr, 0);
 230         out_8(&i2c->lmadr, chip);
 231
 232         tran = 0;
 233         result = IIC_OK;
 234         creg = 0;
 235
 236         while (tran != cnt && (result == IIC_OK)) {
 237                 int  bc,j;
 238
 239                 /*
 240                  * Control register =
 241                  * Normal transfer, 7-bits adressing, Transfer up to
 242                  * bc bytes, Normal start, Transfer is a sequence of transfers
 243                  */
 244                 creg |= IIC_CNTL_PT;
 245
 246                 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
 247                 creg |= (bc - 1) << 4;
 248                 /* if the real cmd type is write continue trans */
 249                 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 250                         creg |= IIC_CNTL_CHT;
 251
 252                 /* last part of address, prepare for repeated start on read */
 253                 if (cmd_type && (ptr == addr) && ((tran + bc) == cnt))
 254                         creg |= IIC_CNTL_RPST;
 255
 256                 if (reading) {
 257                         creg |= IIC_CNTL_READ;
 258                 } else {
 259                         for(j = 0; j < bc; j++) {
 260                                 /* Set buffer */
 261                                 out_8(&i2c->mdbuf, ptr[tran + j]);
 262                         }
 263                 }
 264                 out_8(&i2c->cntl, creg);
 265
 266                 /*
 267                  * Transfer is in progress
 268                  * we have to wait for upto 5 bytes of data
 269                  * 1 byte chip address+r/w bit then bc bytes
 270                  * of data.
 271                  * udelay(10) is 1 bit time at 100khz
 272                  * Doubled for slop. 20 is too small.
 273                  */
 274                 i = 2 * 5 * 8;
 275                 do {
 276                         /* Get status */
 277                         status = in_8(&i2c->sts);
 278                         udelay(10);
 279                         i--;
 280                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
 281                          (i > 0));
 282
 283                 if (status & IIC_STS_ERR) {
 284                         result = IIC_NOK;
 285                         status = in_8(&i2c->extsts);
 286                         /* Lost arbitration? */
 287                         if (status & IIC_EXTSTS_LA)
 288                                 result = IIC_NOK_LA;
 289                         /* Incomplete transfer? */
 290                         if (status & IIC_EXTSTS_ICT)
 291                                 result = IIC_NOK_ICT;
 292                         /* Transfer aborted? */
 293                         if (status & IIC_EXTSTS_XFRA)
 294                                 result = IIC_NOK_XFRA;
 295                         /* Is bus free?
 296                          * If error happened during combined xfer
 297                          * IIC interface is usually stuck in some strange
 298                          * state without a valid stop condition.
 299                          * Brute, but working: generate stop, then soft reset.
 300                          */
 301                         if ((status & IIC_EXTSTS_BCS_MASK)
 302                             != IIC_EXTSTS_BCS_FREE){
 303                                 u8 mdcntl = in_8(&i2c->mdcntl);
 304
 305                                 /* Generate valid stop condition */
 306                                 out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
 307                                 out_8(&i2c->directcntl, IIC_DIRCNTL_SCC);
 308                                 udelay(10);
 309                                 out_8(&i2c->directcntl,
 310                                       IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC);
 311                                 out_8(&i2c->xtcntlss, 0);
 312
 313                                 ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM)
 314                                                 ? 400000 : 100000, 0);
 315                         }
 316                 } else if ( status & IIC_STS_PT) {
 317                         result = IIC_NOK_TOUT;
 318                 }
 319
 320                 /* Command is reading => get buffer */
 321                 if ((reading) && (result == IIC_OK)) {
 322                         /* Are there data in buffer */
 323                         if (status & IIC_STS_MDBS) {
 324                                 /*
 325                                  * even if we have data we have to wait 4OPB
 326                                  * clocks for it to hit the front of the FIFO,
 327                                  * after that we can just read. We should check
 328                                  * XFCNT here and if the FIFO is full there is
 329                                  * no need to wait.
 330                                  */
 331                                 udelay(1);
 332                                 for (j = 0; j < bc; j++)
 333                                         ptr[tran + j] = in_8(&i2c->mdbuf);
 334                         } else
 335                                 result = IIC_NOK_DATA;
 336                 }
 337                 creg = 0;
 338                 tran += bc;
 339                 if (ptr == addr && tran == cnt) {
 340                         ptr = data;
 341                         cnt = data_len;
 342                         tran = 0;
 343                         reading = cmd_type;
 344                 }
 345         }
 346         return result;
 347 }
 348
 349 static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
 350 {
 351         uchar buf[1];
 352
 353         buf[0] = 0;
 354
 355         /*
 356          * What is needed is to send the chip address and verify that the
 357          * address was <ACK>ed (i.e. there was a chip at that address which
 358          * drove the data line low).
 359          */
 360         return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
 361 }
 362
 363 static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
 364                                int alen, uchar *buffer, int len, int read)
 365 {
 366         uchar xaddr[4];
 367         int ret;
 368
 369         if (alen > 4) {
 370                 printf("I2C: addr len %d not supported\n", alen);
 371                 return 1;
 372         }
 373
 374         if (alen > 0) {
 375                 xaddr[0] = (addr >> 24) & 0xFF;
 376                 xaddr[1] = (addr >> 16) & 0xFF;
 377                 xaddr[2] = (addr >> 8) & 0xFF;
 378                 xaddr[3] = addr & 0xFF;
 379         }
 380
 381
 382 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 383         /*
 384          * EEPROM chips that implement "address overflow" are ones
 385          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 386          * address and the extra bits end up in the "chip address"
 387          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 388          * four 256 byte chips.
 389          *
 390          * Note that we consider the length of the address field to
 391          * still be one byte because the extra address bits are
 392          * hidden in the chip address.
 393          */
 394         if (alen > 0)
 395                 chip |= ((addr >> (alen * 8)) &
 396                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 397 #endif
 398         ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
 399                             buffer, len);
 400         if (ret) {
 401                 printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
 402                 return 1;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 409                            int alen, uchar *buffer, int len)
 410 {
 411         return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
 412 }
 413
 414 static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 415                             int alen, uchar *buffer, int len)
 416 {
 417         return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
 418 }
 419
 420 static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 421                                              unsigned int speed)
 422 {
 423         if (speed != adap->speed)
 424                 return -1;
 425         return speed;
 426 }
 427
 428 /*
 429  * Register ppc4xx i2c adapters
 430  */
 431 #ifdef CONFIG_SYS_I2C_PPC4XX_CH0
 432 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
 433                          ppc4xx_i2c_read, ppc4xx_i2c_write,
 434                          ppc4xx_i2c_set_bus_speed,
 435                          CONFIG_SYS_I2C_PPC4XX_SPEED_0,
 436                          CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
 437 #endif
 438 #ifdef CONFIG_SYS_I2C_PPC4XX_CH1
 439 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
 440                          ppc4xx_i2c_read, ppc4xx_i2c_write,
 441                          ppc4xx_i2c_set_bus_speed,
 442                          CONFIG_SYS_I2C_PPC4XX_SPEED_1,
 443                          CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)
 444 #endif