57548ee31f4dba1ccf0403fcce97eaf3875e4ca4
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2  * (C) Copyright 2008
3  * Texas Instruments, <www.ti.com>
4  * Sukumar Ghorai <s-ghorai@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation's version 2 of
12  * the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <config.h>
26 #include <common.h>
27 #include <malloc.h>
28 #include <memalign.h>
29 #include <mmc.h>
30 #include <part.h>
31 #include <i2c.h>
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
33 #include <palmas.h>
34 #endif
35 #include <asm/io.h>
36 #include <asm/arch/mmc_host_def.h>
37 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/gpio.h>
39 #include <asm/arch/sys_proto.h>
40 #endif
41 #ifdef CONFIG_MMC_OMAP36XX_PINS
42 #include <asm/arch/mux.h>
43 #endif
44 #include <dm.h>
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51 #define OMAP_HSMMC_USE_GPIO
52 #else
53 #undef OMAP_HSMMC_USE_GPIO
54 #endif
55
56 /* common definitions for all OMAPs */
57 #define SYSCTL_SRC      (1 << 25)
58 #define SYSCTL_SRD      (1 << 26)
59
60 struct omap_hsmmc_data {
61         struct hsmmc *base_addr;
62 #if !CONFIG_IS_ENABLED(DM_MMC)
63         struct mmc_config cfg;
64 #endif
65         uint bus_width;
66         uint clock;
67 #ifdef OMAP_HSMMC_USE_GPIO
68 #if CONFIG_IS_ENABLED(DM_MMC)
69         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
70         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
71         bool cd_inverted;
72 #else
73         int cd_gpio;
74         int wp_gpio;
75 #endif
76 #endif
77 #if CONFIG_IS_ENABLED(DM_MMC)
78         uint iov;
79         enum bus_mode mode;
80 #endif
81         u8 controller_flags;
82 #ifndef CONFIG_OMAP34XX
83         struct omap_hsmmc_adma_desc *adma_desc_table;
84         uint desc_slot;
85 #endif
86 };
87
88 #ifndef CONFIG_OMAP34XX
89 struct omap_hsmmc_adma_desc {
90         u8 attr;
91         u8 reserved;
92         u16 len;
93         u32 addr;
94 };
95
96 #define ADMA_MAX_LEN    63488
97
98 /* Decriptor table defines */
99 #define ADMA_DESC_ATTR_VALID            BIT(0)
100 #define ADMA_DESC_ATTR_END              BIT(1)
101 #define ADMA_DESC_ATTR_INT              BIT(2)
102 #define ADMA_DESC_ATTR_ACT1             BIT(4)
103 #define ADMA_DESC_ATTR_ACT2             BIT(5)
104
105 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
106 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
107 #endif
108
109 /* If we fail after 1 second wait, something is really bad */
110 #define MAX_RETRY_MS    1000
111 #define MMC_TIMEOUT_MS  20
112
113 /* DMA transfers can take a long time if a lot a data is transferred.
114  * The timeout must take in account the amount of data. Let's assume
115  * that the time will never exceed 333 ms per MB (in other word we assume
116  * that the bandwidth is always above 3MB/s).
117  */
118 #define DMA_TIMEOUT_PER_MB      333
119 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
120 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
121 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
122
123 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
124 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
125                         unsigned int siz);
126 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
127 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
128 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
129
130 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
131 {
132 #if CONFIG_IS_ENABLED(DM_MMC)
133         return dev_get_priv(mmc->dev);
134 #else
135         return (struct omap_hsmmc_data *)mmc->priv;
136 #endif
137 }
138 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
139 {
140 #if CONFIG_IS_ENABLED(DM_MMC)
141         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
142         return &plat->cfg;
143 #else
144         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
145 #endif
146 }
147
148 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
149 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
150 {
151         int ret;
152
153 #ifndef CONFIG_DM_GPIO
154         if (!gpio_is_valid(gpio))
155                 return -1;
156 #endif
157         ret = gpio_request(gpio, label);
158         if (ret)
159                 return ret;
160
161         ret = gpio_direction_input(gpio);
162         if (ret)
163                 return ret;
164
165         return gpio;
166 }
167 #endif
168
169 static unsigned char mmc_board_init(struct mmc *mmc)
170 {
171 #if defined(CONFIG_OMAP34XX)
172         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
173         t2_t *t2_base = (t2_t *)T2_BASE;
174         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
175         u32 pbias_lite;
176 #ifdef CONFIG_MMC_OMAP36XX_PINS
177         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
178 #endif
179
180         pbias_lite = readl(&t2_base->pbias_lite);
181         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
182 #ifdef CONFIG_TARGET_OMAP3_CAIRO
183         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
184         pbias_lite &= ~PBIASLITEVMODE0;
185 #endif
186 #ifdef CONFIG_MMC_OMAP36XX_PINS
187         if (get_cpu_family() == CPU_OMAP36XX) {
188                 /* Disable extended drain IO before changing PBIAS */
189                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
190                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
191         }
192 #endif
193         writel(pbias_lite, &t2_base->pbias_lite);
194
195         writel(pbias_lite | PBIASLITEPWRDNZ1 |
196                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
197                 &t2_base->pbias_lite);
198
199 #ifdef CONFIG_MMC_OMAP36XX_PINS
200         if (get_cpu_family() == CPU_OMAP36XX)
201                 /* Enable extended drain IO after changing PBIAS */
202                 writel(wkup_ctrl |
203                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
204                                 OMAP34XX_CTRL_WKUP_CTRL);
205 #endif
206         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
207                 &t2_base->devconf0);
208
209         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
210                 &t2_base->devconf1);
211
212         /* Change from default of 52MHz to 26MHz if necessary */
213         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
214                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
215                         &t2_base->ctl_prog_io1);
216
217         writel(readl(&prcm_base->fclken1_core) |
218                 EN_MMC1 | EN_MMC2 | EN_MMC3,
219                 &prcm_base->fclken1_core);
220
221         writel(readl(&prcm_base->iclken1_core) |
222                 EN_MMC1 | EN_MMC2 | EN_MMC3,
223                 &prcm_base->iclken1_core);
224 #endif
225
226 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
227         /* PBIAS config needed for MMC1 only */
228         if (mmc_get_blk_desc(mmc)->devnum == 0)
229                 vmmc_pbias_config(LDO_VOLT_3V0);
230 #endif
231
232         return 0;
233 }
234
235 void mmc_init_stream(struct hsmmc *mmc_base)
236 {
237         ulong start;
238
239         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
240
241         writel(MMC_CMD0, &mmc_base->cmd);
242         start = get_timer(0);
243         while (!(readl(&mmc_base->stat) & CC_MASK)) {
244                 if (get_timer(0) - start > MAX_RETRY_MS) {
245                         printf("%s: timedout waiting for cc!\n", __func__);
246                         return;
247                 }
248         }
249         writel(CC_MASK, &mmc_base->stat)
250                 ;
251         writel(MMC_CMD0, &mmc_base->cmd)
252                 ;
253         start = get_timer(0);
254         while (!(readl(&mmc_base->stat) & CC_MASK)) {
255                 if (get_timer(0) - start > MAX_RETRY_MS) {
256                         printf("%s: timedout waiting for cc2!\n", __func__);
257                         return;
258                 }
259         }
260         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
261 }
262
263 #if CONFIG_IS_ENABLED(DM_MMC)
264 static void omap_hsmmc_set_timing(struct mmc *mmc)
265 {
266         u32 val;
267         struct hsmmc *mmc_base;
268         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
269
270         mmc_base = priv->base_addr;
271
272         val = readl(&mmc_base->ac12);
273         val &= ~AC12_UHSMC_MASK;
274         priv->mode = mmc->selected_mode;
275
276         if (mmc_is_mode_ddr(priv->mode))
277                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
278         else
279                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
280
281         switch (priv->mode) {
282         case MMC_HS_200:
283         case UHS_SDR104:
284                 val |= AC12_UHSMC_SDR104;
285                 break;
286         case UHS_SDR50:
287                 val |= AC12_UHSMC_SDR50;
288                 break;
289         case MMC_DDR_52:
290         case UHS_DDR50:
291                 val |= AC12_UHSMC_DDR50;
292                 break;
293         case SD_HS:
294         case MMC_HS_52:
295         case UHS_SDR25:
296                 val |= AC12_UHSMC_SDR25;
297                 break;
298         case MMC_LEGACY:
299         case MMC_HS:
300         case SD_LEGACY:
301         case UHS_SDR12:
302                 val |= AC12_UHSMC_SDR12;
303                 break;
304         default:
305                 val |= AC12_UHSMC_RES;
306                 break;
307         }
308         writel(val, &mmc_base->ac12);
309 }
310
311 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
312 {
313         struct hsmmc *mmc_base;
314         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
315         u32 val;
316
317         mmc_base = priv->base_addr;
318
319         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
320
321         switch (priv->iov) {
322         case IOV_3V3:
323                 val |= SDVS_3V3;
324                 break;
325         case IOV_3V0:
326                 val |= SDVS_3V0;
327                 break;
328         case IOV_1V8:
329                 val |= SDVS_1V8;
330                 break;
331         }
332
333         writel(val, &mmc_base->hctl);
334 }
335
336 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
337 {
338         struct hsmmc *mmc_base;
339         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
340         u32 val;
341
342         mmc_base = priv->base_addr;
343         val = readl(&mmc_base->capa);
344
345         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
346                 val |= (VS30_3V0SUP | VS18_1V8SUP);
347                 priv->iov = IOV_3V0;
348         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
349                 val |= VS30_3V0SUP;
350                 val &= ~VS18_1V8SUP;
351                 priv->iov = IOV_3V0;
352         } else {
353                 val |= VS18_1V8SUP;
354                 val &= ~VS30_3V0SUP;
355                 priv->iov = IOV_1V8;
356         }
357
358         writel(val, &mmc_base->capa);
359 }
360
361 #ifdef MMC_SUPPORTS_TUNING
362 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
363 {
364         struct hsmmc *mmc_base;
365         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
366         u32 val;
367
368         mmc_base = priv->base_addr;
369         val = readl(&mmc_base->ac12);
370         val &= ~(AC12_SCLK_SEL);
371         writel(val, &mmc_base->ac12);
372
373         val = readl(&mmc_base->dll);
374         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
375         writel(val, &mmc_base->dll);
376 }
377
378 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
379 {
380         int i;
381         struct hsmmc *mmc_base;
382         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
383         u32 val;
384
385         mmc_base = priv->base_addr;
386         val = readl(&mmc_base->dll);
387         val |= DLL_FORCE_VALUE;
388         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
389         val |= (count << DLL_FORCE_SR_C_SHIFT);
390         writel(val, &mmc_base->dll);
391
392         val |= DLL_CALIB;
393         writel(val, &mmc_base->dll);
394         for (i = 0; i < 1000; i++) {
395                 if (readl(&mmc_base->dll) & DLL_CALIB)
396                         break;
397         }
398         val &= ~DLL_CALIB;
399         writel(val, &mmc_base->dll);
400 }
401
402 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
403 {
404         struct omap_hsmmc_data *priv = dev_get_priv(dev);
405         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
406         struct mmc *mmc = upriv->mmc;
407         struct hsmmc *mmc_base;
408         u32 val;
409         u8 cur_match, prev_match = 0;
410         int ret;
411         u32 phase_delay = 0;
412         u32 start_window = 0, max_window = 0;
413         u32 length = 0, max_len = 0;
414
415         mmc_base = priv->base_addr;
416         val = readl(&mmc_base->capa2);
417
418         /* clock tuning is not needed for upto 52MHz */
419         if (!((mmc->selected_mode == MMC_HS_200) ||
420               (mmc->selected_mode == UHS_SDR104) ||
421               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
422                 return 0;
423
424         val = readl(&mmc_base->dll);
425         val |= DLL_SWT;
426         writel(val, &mmc_base->dll);
427         while (phase_delay <= MAX_PHASE_DELAY) {
428                 omap_hsmmc_set_dll(mmc, phase_delay);
429
430                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
431
432                 if (cur_match) {
433                         if (prev_match) {
434                                 length++;
435                         } else {
436                                 start_window = phase_delay;
437                                 length = 1;
438                         }
439                 }
440
441                 if (length > max_len) {
442                         max_window = start_window;
443                         max_len = length;
444                 }
445
446                 prev_match = cur_match;
447                 phase_delay += 4;
448         }
449
450         if (!max_len) {
451                 ret = -EIO;
452                 goto tuning_error;
453         }
454
455         val = readl(&mmc_base->ac12);
456         if (!(val & AC12_SCLK_SEL)) {
457                 ret = -EIO;
458                 goto tuning_error;
459         }
460
461         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
462         omap_hsmmc_set_dll(mmc, phase_delay);
463
464         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
465         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
466
467         return 0;
468
469 tuning_error:
470
471         omap_hsmmc_disable_tuning(mmc);
472         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
473         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
474
475         return ret;
476 }
477 #endif
478 #endif
479
480 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
481 {
482         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
483         struct hsmmc *mmc_base = priv->base_addr;
484         u32 irq_mask = INT_EN_MASK;
485
486         /*
487          * TODO: Errata i802 indicates only DCRC interrupts can occur during
488          * tuning procedure and DCRC should be disabled. But see occurences
489          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
490          * interrupts occur along with BRR, so the data is actually in the
491          * buffer. It has to be debugged why these interrutps occur
492          */
493         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
494                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
495
496         writel(irq_mask, &mmc_base->ie);
497 }
498
499 static int omap_hsmmc_init_setup(struct mmc *mmc)
500 {
501         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
502         struct hsmmc *mmc_base;
503         unsigned int reg_val;
504         unsigned int dsor;
505         ulong start;
506
507         mmc_base = priv->base_addr;
508         mmc_board_init(mmc);
509
510         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
511                 &mmc_base->sysconfig);
512         start = get_timer(0);
513         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
514                 if (get_timer(0) - start > MAX_RETRY_MS) {
515                         printf("%s: timedout waiting for cc2!\n", __func__);
516                         return -ETIMEDOUT;
517                 }
518         }
519         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
520         start = get_timer(0);
521         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
522                 if (get_timer(0) - start > MAX_RETRY_MS) {
523                         printf("%s: timedout waiting for softresetall!\n",
524                                 __func__);
525                         return -ETIMEDOUT;
526                 }
527         }
528 #ifndef CONFIG_OMAP34XX
529         reg_val = readl(&mmc_base->hl_hwinfo);
530         if (reg_val & MADMA_EN)
531                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
532 #endif
533
534 #if CONFIG_IS_ENABLED(DM_MMC)
535         omap_hsmmc_set_capabilities(mmc);
536         omap_hsmmc_conf_bus_power(mmc);
537 #else
538         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
539         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
540                 &mmc_base->capa);
541 #endif
542
543         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
544
545         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
546                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
547                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
548
549         dsor = 240;
550         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
551                 (ICE_STOP | DTO_15THDTO));
552         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
553                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
554         start = get_timer(0);
555         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
556                 if (get_timer(0) - start > MAX_RETRY_MS) {
557                         printf("%s: timedout waiting for ics!\n", __func__);
558                         return -ETIMEDOUT;
559                 }
560         }
561         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
562
563         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
564
565         mmc_enable_irq(mmc, NULL);
566         mmc_init_stream(mmc_base);
567
568         return 0;
569 }
570
571 /*
572  * MMC controller internal finite state machine reset
573  *
574  * Used to reset command or data internal state machines, using respectively
575  * SRC or SRD bit of SYSCTL register
576  */
577 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
578 {
579         ulong start;
580
581         mmc_reg_out(&mmc_base->sysctl, bit, bit);
582
583         /*
584          * CMD(DAT) lines reset procedures are slightly different
585          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
586          * According to OMAP3 TRM:
587          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
588          * returns to 0x0.
589          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
590          * procedure steps must be as follows:
591          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
592          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
593          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
594          * 3. Wait until the SRC (SRD) bit returns to 0x0
595          *    (reset procedure is completed).
596          */
597 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
598         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
599         if (!(readl(&mmc_base->sysctl) & bit)) {
600                 start = get_timer(0);
601                 while (!(readl(&mmc_base->sysctl) & bit)) {
602                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
603                                 return;
604                 }
605         }
606 #endif
607         start = get_timer(0);
608         while ((readl(&mmc_base->sysctl) & bit) != 0) {
609                 if (get_timer(0) - start > MAX_RETRY_MS) {
610                         printf("%s: timedout waiting for sysctl %x to clear\n",
611                                 __func__, bit);
612                         return;
613                 }
614         }
615 }
616
617 #ifndef CONFIG_OMAP34XX
618 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
619 {
620         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
621         struct omap_hsmmc_adma_desc *desc;
622         u8 attr;
623
624         desc = &priv->adma_desc_table[priv->desc_slot];
625
626         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
627         if (!end)
628                 priv->desc_slot++;
629         else
630                 attr |= ADMA_DESC_ATTR_END;
631
632         desc->len = len;
633         desc->addr = (u32)buf;
634         desc->reserved = 0;
635         desc->attr = attr;
636 }
637
638 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
639                                           struct mmc_data *data)
640 {
641         uint total_len = data->blocksize * data->blocks;
642         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
643         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
644         int i = desc_count;
645         char *buf;
646
647         priv->desc_slot = 0;
648         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
649                                 memalign(ARCH_DMA_MINALIGN, desc_count *
650                                 sizeof(struct omap_hsmmc_adma_desc));
651
652         if (data->flags & MMC_DATA_READ)
653                 buf = data->dest;
654         else
655                 buf = (char *)data->src;
656
657         while (--i) {
658                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
659                 buf += ADMA_MAX_LEN;
660                 total_len -= ADMA_MAX_LEN;
661         }
662
663         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
664
665         flush_dcache_range((long)priv->adma_desc_table,
666                            (long)priv->adma_desc_table +
667                            ROUND(desc_count *
668                            sizeof(struct omap_hsmmc_adma_desc),
669                            ARCH_DMA_MINALIGN));
670 }
671
672 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
673 {
674         struct hsmmc *mmc_base;
675         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
676         u32 val;
677         char *buf;
678
679         mmc_base = priv->base_addr;
680         omap_hsmmc_prepare_adma_table(mmc, data);
681
682         if (data->flags & MMC_DATA_READ)
683                 buf = data->dest;
684         else
685                 buf = (char *)data->src;
686
687         val = readl(&mmc_base->hctl);
688         val |= DMA_SELECT;
689         writel(val, &mmc_base->hctl);
690
691         val = readl(&mmc_base->con);
692         val |= DMA_MASTER;
693         writel(val, &mmc_base->con);
694
695         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
696
697         flush_dcache_range((u32)buf,
698                            (u32)buf +
699                            ROUND(data->blocksize * data->blocks,
700                                  ARCH_DMA_MINALIGN));
701 }
702
703 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
704 {
705         struct hsmmc *mmc_base;
706         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
707         u32 val;
708
709         mmc_base = priv->base_addr;
710
711         val = readl(&mmc_base->con);
712         val &= ~DMA_MASTER;
713         writel(val, &mmc_base->con);
714
715         val = readl(&mmc_base->hctl);
716         val &= ~DMA_SELECT;
717         writel(val, &mmc_base->hctl);
718
719         kfree(priv->adma_desc_table);
720 }
721 #else
722 #define omap_hsmmc_adma_desc
723 #define omap_hsmmc_prepare_adma_table
724 #define omap_hsmmc_prepare_data
725 #define omap_hsmmc_dma_cleanup
726 #endif
727
728 #if !CONFIG_IS_ENABLED(DM_MMC)
729 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
730                         struct mmc_data *data)
731 {
732         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
733 #else
734 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
735                         struct mmc_data *data)
736 {
737         struct omap_hsmmc_data *priv = dev_get_priv(dev);
738         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
739         struct mmc *mmc = upriv->mmc;
740 #endif
741         struct hsmmc *mmc_base;
742         unsigned int flags, mmc_stat;
743         ulong start;
744
745         mmc_base = priv->base_addr;
746
747         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
748                 return 0;
749
750         start = get_timer(0);
751         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
752                 if (get_timer(0) - start > MAX_RETRY_MS) {
753                         printf("%s: timedout waiting on cmd inhibit to clear\n",
754                                         __func__);
755                         return -ETIMEDOUT;
756                 }
757         }
758         writel(0xFFFFFFFF, &mmc_base->stat);
759         start = get_timer(0);
760         while (readl(&mmc_base->stat)) {
761                 if (get_timer(0) - start > MAX_RETRY_MS) {
762                         printf("%s: timedout waiting for STAT (%x) to clear\n",
763                                 __func__, readl(&mmc_base->stat));
764                         return -ETIMEDOUT;
765                 }
766         }
767         /*
768          * CMDREG
769          * CMDIDX[13:8] : Command index
770          * DATAPRNT[5]  : Data Present Select
771          * ENCMDIDX[4]  : Command Index Check Enable
772          * ENCMDCRC[3]  : Command CRC Check Enable
773          * RSPTYP[1:0]
774          *      00 = No Response
775          *      01 = Length 136
776          *      10 = Length 48
777          *      11 = Length 48 Check busy after response
778          */
779         /* Delay added before checking the status of frq change
780          * retry not supported by mmc.c(core file)
781          */
782         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
783                 udelay(50000); /* wait 50 ms */
784
785         if (!(cmd->resp_type & MMC_RSP_PRESENT))
786                 flags = 0;
787         else if (cmd->resp_type & MMC_RSP_136)
788                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
789         else if (cmd->resp_type & MMC_RSP_BUSY)
790                 flags = RSP_TYPE_LGHT48B;
791         else
792                 flags = RSP_TYPE_LGHT48;
793
794         /* enable default flags */
795         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
796                         MSBS_SGLEBLK);
797         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
798
799         if (cmd->resp_type & MMC_RSP_CRC)
800                 flags |= CCCE_CHECK;
801         if (cmd->resp_type & MMC_RSP_OPCODE)
802                 flags |= CICE_CHECK;
803
804         if (data) {
805                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
806                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
807                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
808                         data->blocksize = 512;
809                         writel(data->blocksize | (data->blocks << 16),
810                                                         &mmc_base->blk);
811                 } else
812                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
813
814                 if (data->flags & MMC_DATA_READ)
815                         flags |= (DP_DATA | DDIR_READ);
816                 else
817                         flags |= (DP_DATA | DDIR_WRITE);
818
819 #ifndef CONFIG_OMAP34XX
820                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
821                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
822                         omap_hsmmc_prepare_data(mmc, data);
823                         flags |= DE_ENABLE;
824                 }
825 #endif
826         }
827
828         mmc_enable_irq(mmc, cmd);
829
830         writel(cmd->cmdarg, &mmc_base->arg);
831         udelay(20);             /* To fix "No status update" error on eMMC */
832         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
833
834         start = get_timer(0);
835         do {
836                 mmc_stat = readl(&mmc_base->stat);
837                 if (get_timer(start) > MAX_RETRY_MS) {
838                         printf("%s : timeout: No status update\n", __func__);
839                         return -ETIMEDOUT;
840                 }
841         } while (!mmc_stat);
842
843         if ((mmc_stat & IE_CTO) != 0) {
844                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
845                 return -ETIMEDOUT;
846         } else if ((mmc_stat & ERRI_MASK) != 0)
847                 return -1;
848
849         if (mmc_stat & CC_MASK) {
850                 writel(CC_MASK, &mmc_base->stat);
851                 if (cmd->resp_type & MMC_RSP_PRESENT) {
852                         if (cmd->resp_type & MMC_RSP_136) {
853                                 /* response type 2 */
854                                 cmd->response[3] = readl(&mmc_base->rsp10);
855                                 cmd->response[2] = readl(&mmc_base->rsp32);
856                                 cmd->response[1] = readl(&mmc_base->rsp54);
857                                 cmd->response[0] = readl(&mmc_base->rsp76);
858                         } else
859                                 /* response types 1, 1b, 3, 4, 5, 6 */
860                                 cmd->response[0] = readl(&mmc_base->rsp10);
861                 }
862         }
863
864 #ifndef CONFIG_OMAP34XX
865         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
866             !mmc_is_tuning_cmd(cmd->cmdidx)) {
867                 u32 sz_mb, timeout;
868
869                 if (mmc_stat & IE_ADMAE) {
870                         omap_hsmmc_dma_cleanup(mmc);
871                         return -EIO;
872                 }
873
874                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
875                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
876                 if (timeout < MAX_RETRY_MS)
877                         timeout = MAX_RETRY_MS;
878
879                 start = get_timer(0);
880                 do {
881                         mmc_stat = readl(&mmc_base->stat);
882                         if (mmc_stat & TC_MASK) {
883                                 writel(readl(&mmc_base->stat) | TC_MASK,
884                                        &mmc_base->stat);
885                                 break;
886                         }
887                         if (get_timer(start) > timeout) {
888                                 printf("%s : DMA timeout: No status update\n",
889                                        __func__);
890                                 return -ETIMEDOUT;
891                         }
892                 } while (1);
893
894                 omap_hsmmc_dma_cleanup(mmc);
895                 return 0;
896         }
897 #endif
898
899         if (data && (data->flags & MMC_DATA_READ)) {
900                 mmc_read_data(mmc_base, data->dest,
901                                 data->blocksize * data->blocks);
902         } else if (data && (data->flags & MMC_DATA_WRITE)) {
903                 mmc_write_data(mmc_base, data->src,
904                                 data->blocksize * data->blocks);
905         }
906         return 0;
907 }
908
909 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
910 {
911         unsigned int *output_buf = (unsigned int *)buf;
912         unsigned int mmc_stat;
913         unsigned int count;
914
915         /*
916          * Start Polled Read
917          */
918         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
919         count /= 4;
920
921         while (size) {
922                 ulong start = get_timer(0);
923                 do {
924                         mmc_stat = readl(&mmc_base->stat);
925                         if (get_timer(0) - start > MAX_RETRY_MS) {
926                                 printf("%s: timedout waiting for status!\n",
927                                                 __func__);
928                                 return -ETIMEDOUT;
929                         }
930                 } while (mmc_stat == 0);
931
932                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
933                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
934
935                 if ((mmc_stat & ERRI_MASK) != 0)
936                         return 1;
937
938                 if (mmc_stat & BRR_MASK) {
939                         unsigned int k;
940
941                         writel(readl(&mmc_base->stat) | BRR_MASK,
942                                 &mmc_base->stat);
943                         for (k = 0; k < count; k++) {
944                                 *output_buf = readl(&mmc_base->data);
945                                 output_buf++;
946                         }
947                         size -= (count*4);
948                 }
949
950                 if (mmc_stat & BWR_MASK)
951                         writel(readl(&mmc_base->stat) | BWR_MASK,
952                                 &mmc_base->stat);
953
954                 if (mmc_stat & TC_MASK) {
955                         writel(readl(&mmc_base->stat) | TC_MASK,
956                                 &mmc_base->stat);
957                         break;
958                 }
959         }
960         return 0;
961 }
962
963 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
964                                 unsigned int size)
965 {
966         unsigned int *input_buf = (unsigned int *)buf;
967         unsigned int mmc_stat;
968         unsigned int count;
969
970         /*
971          * Start Polled Write
972          */
973         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
974         count /= 4;
975
976         while (size) {
977                 ulong start = get_timer(0);
978                 do {
979                         mmc_stat = readl(&mmc_base->stat);
980                         if (get_timer(0) - start > MAX_RETRY_MS) {
981                                 printf("%s: timedout waiting for status!\n",
982                                                 __func__);
983                                 return -ETIMEDOUT;
984                         }
985                 } while (mmc_stat == 0);
986
987                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
988                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
989
990                 if ((mmc_stat & ERRI_MASK) != 0)
991                         return 1;
992
993                 if (mmc_stat & BWR_MASK) {
994                         unsigned int k;
995
996                         writel(readl(&mmc_base->stat) | BWR_MASK,
997                                         &mmc_base->stat);
998                         for (k = 0; k < count; k++) {
999                                 writel(*input_buf, &mmc_base->data);
1000                                 input_buf++;
1001                         }
1002                         size -= (count*4);
1003                 }
1004
1005                 if (mmc_stat & BRR_MASK)
1006                         writel(readl(&mmc_base->stat) | BRR_MASK,
1007                                 &mmc_base->stat);
1008
1009                 if (mmc_stat & TC_MASK) {
1010                         writel(readl(&mmc_base->stat) | TC_MASK,
1011                                 &mmc_base->stat);
1012                         break;
1013                 }
1014         }
1015         return 0;
1016 }
1017
1018 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1019 {
1020         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1021 }
1022
1023 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1024 {
1025         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1026 }
1027
1028 static void omap_hsmmc_set_clock(struct mmc *mmc)
1029 {
1030         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1031         struct hsmmc *mmc_base;
1032         unsigned int dsor = 0;
1033         ulong start;
1034
1035         mmc_base = priv->base_addr;
1036         omap_hsmmc_stop_clock(mmc_base);
1037
1038         /* TODO: Is setting DTO required here? */
1039         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1040                     (ICE_STOP | DTO_15THDTO));
1041
1042         if (mmc->clock != 0) {
1043                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1044                 if (dsor > CLKD_MAX)
1045                         dsor = CLKD_MAX;
1046         } else {
1047                 dsor = CLKD_MAX;
1048         }
1049
1050         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1051                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1052
1053         start = get_timer(0);
1054         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1055                 if (get_timer(0) - start > MAX_RETRY_MS) {
1056                         printf("%s: timedout waiting for ics!\n", __func__);
1057                         return;
1058                 }
1059         }
1060
1061         priv->clock = mmc->clock;
1062         omap_hsmmc_start_clock(mmc_base);
1063 }
1064
1065 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1066 {
1067         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1068         struct hsmmc *mmc_base;
1069
1070         mmc_base = priv->base_addr;
1071         /* configue bus width */
1072         switch (mmc->bus_width) {
1073         case 8:
1074                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1075                         &mmc_base->con);
1076                 break;
1077
1078         case 4:
1079                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1080                         &mmc_base->con);
1081                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1082                         &mmc_base->hctl);
1083                 break;
1084
1085         case 1:
1086         default:
1087                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1088                         &mmc_base->con);
1089                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1090                         &mmc_base->hctl);
1091                 break;
1092         }
1093
1094         priv->bus_width = mmc->bus_width;
1095 }
1096
1097 #if !CONFIG_IS_ENABLED(DM_MMC)
1098 static int omap_hsmmc_set_ios(struct mmc *mmc)
1099 {
1100         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1101 #else
1102 static int omap_hsmmc_set_ios(struct udevice *dev)
1103 {
1104         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1105         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1106         struct mmc *mmc = upriv->mmc;
1107 #endif
1108
1109         if (priv->bus_width != mmc->bus_width)
1110                 omap_hsmmc_set_bus_width(mmc);
1111
1112         if (priv->clock != mmc->clock)
1113                 omap_hsmmc_set_clock(mmc);
1114
1115 #if CONFIG_IS_ENABLED(DM_MMC)
1116         if (priv->mode != mmc->selected_mode)
1117                 omap_hsmmc_set_timing(mmc);
1118 #endif
1119         return 0;
1120 }
1121
1122 #ifdef OMAP_HSMMC_USE_GPIO
1123 #if CONFIG_IS_ENABLED(DM_MMC)
1124 static int omap_hsmmc_getcd(struct udevice *dev)
1125 {
1126         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1127         int value;
1128
1129         value = dm_gpio_get_value(&priv->cd_gpio);
1130         /* if no CD return as 1 */
1131         if (value < 0)
1132                 return 1;
1133
1134         if (priv->cd_inverted)
1135                 return !value;
1136         return value;
1137 }
1138
1139 static int omap_hsmmc_getwp(struct udevice *dev)
1140 {
1141         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1142         int value;
1143
1144         value = dm_gpio_get_value(&priv->wp_gpio);
1145         /* if no WP return as 0 */
1146         if (value < 0)
1147                 return 0;
1148         return value;
1149 }
1150 #else
1151 static int omap_hsmmc_getcd(struct mmc *mmc)
1152 {
1153         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1154         int cd_gpio;
1155
1156         /* if no CD return as 1 */
1157         cd_gpio = priv->cd_gpio;
1158         if (cd_gpio < 0)
1159                 return 1;
1160
1161         /* NOTE: assumes card detect signal is active-low */
1162         return !gpio_get_value(cd_gpio);
1163 }
1164
1165 static int omap_hsmmc_getwp(struct mmc *mmc)
1166 {
1167         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1168         int wp_gpio;
1169
1170         /* if no WP return as 0 */
1171         wp_gpio = priv->wp_gpio;
1172         if (wp_gpio < 0)
1173                 return 0;
1174
1175         /* NOTE: assumes write protect signal is active-high */
1176         return gpio_get_value(wp_gpio);
1177 }
1178 #endif
1179 #endif
1180
1181 #if CONFIG_IS_ENABLED(DM_MMC)
1182 static const struct dm_mmc_ops omap_hsmmc_ops = {
1183         .send_cmd       = omap_hsmmc_send_cmd,
1184         .set_ios        = omap_hsmmc_set_ios,
1185 #ifdef OMAP_HSMMC_USE_GPIO
1186         .get_cd         = omap_hsmmc_getcd,
1187         .get_wp         = omap_hsmmc_getwp,
1188 #endif
1189 #ifdef MMC_SUPPORTS_TUNING
1190         .execute_tuning = omap_hsmmc_execute_tuning,
1191 #endif
1192 };
1193 #else
1194 static const struct mmc_ops omap_hsmmc_ops = {
1195         .send_cmd       = omap_hsmmc_send_cmd,
1196         .set_ios        = omap_hsmmc_set_ios,
1197         .init           = omap_hsmmc_init_setup,
1198 #ifdef OMAP_HSMMC_USE_GPIO
1199         .getcd          = omap_hsmmc_getcd,
1200         .getwp          = omap_hsmmc_getwp,
1201 #endif
1202 };
1203 #endif
1204
1205 #if !CONFIG_IS_ENABLED(DM_MMC)
1206 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1207                 int wp_gpio)
1208 {
1209         struct mmc *mmc;
1210         struct omap_hsmmc_data *priv;
1211         struct mmc_config *cfg;
1212         uint host_caps_val;
1213
1214         priv = malloc(sizeof(*priv));
1215         if (priv == NULL)
1216                 return -1;
1217
1218         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1219
1220         switch (dev_index) {
1221         case 0:
1222                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1223                 break;
1224 #ifdef OMAP_HSMMC2_BASE
1225         case 1:
1226                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1227 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1228         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1229         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1230                 defined(CONFIG_HSMMC2_8BIT)
1231                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1232                 host_caps_val |= MMC_MODE_8BIT;
1233 #endif
1234                 break;
1235 #endif
1236 #ifdef OMAP_HSMMC3_BASE
1237         case 2:
1238                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1239 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1240                 /* Enable 8-bit interface for eMMC on DRA7XX */
1241                 host_caps_val |= MMC_MODE_8BIT;
1242 #endif
1243                 break;
1244 #endif
1245         default:
1246                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1247                 return 1;
1248         }
1249 #ifdef OMAP_HSMMC_USE_GPIO
1250         /* on error gpio values are set to -1, which is what we want */
1251         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1252         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1253 #endif
1254
1255         cfg = &priv->cfg;
1256
1257         cfg->name = "OMAP SD/MMC";
1258         cfg->ops = &omap_hsmmc_ops;
1259
1260         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1261         cfg->host_caps = host_caps_val & ~host_caps_mask;
1262
1263         cfg->f_min = 400000;
1264
1265         if (f_max != 0)
1266                 cfg->f_max = f_max;
1267         else {
1268                 if (cfg->host_caps & MMC_MODE_HS) {
1269                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1270                                 cfg->f_max = 52000000;
1271                         else
1272                                 cfg->f_max = 26000000;
1273                 } else
1274                         cfg->f_max = 20000000;
1275         }
1276
1277         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1278
1279 #if defined(CONFIG_OMAP34XX)
1280         /*
1281          * Silicon revs 2.1 and older do not support multiblock transfers.
1282          */
1283         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1284                 cfg->b_max = 1;
1285 #endif
1286         mmc = mmc_create(cfg, priv);
1287         if (mmc == NULL)
1288                 return -1;
1289
1290         return 0;
1291 }
1292 #else
1293 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1294 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1295 {
1296         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1297         struct mmc_config *cfg = &plat->cfg;
1298         const void *fdt = gd->fdt_blob;
1299         int node = dev_of_offset(dev);
1300         int ret;
1301
1302         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1303                                       sizeof(struct hsmmc *),
1304                                       MAP_NOCACHE);
1305
1306         ret = mmc_of_parse(dev, cfg);
1307         if (ret < 0)
1308                 return ret;
1309
1310         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1311         cfg->f_min = 400000;
1312         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1313         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1314         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1315                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1316         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1317                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1318
1319 #ifdef OMAP_HSMMC_USE_GPIO
1320         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1321 #endif
1322
1323         return 0;
1324 }
1325 #endif
1326
1327 #ifdef CONFIG_BLK
1328
1329 static int omap_hsmmc_bind(struct udevice *dev)
1330 {
1331         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1332
1333         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1334 }
1335 #endif
1336 static int omap_hsmmc_probe(struct udevice *dev)
1337 {
1338         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1339         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1340         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1341         struct mmc_config *cfg = &plat->cfg;
1342         struct mmc *mmc;
1343
1344         cfg->name = "OMAP SD/MMC";
1345         priv->base_addr = plat->base_addr;
1346 #ifdef OMAP_HSMMC_USE_GPIO
1347         priv->cd_inverted = plat->cd_inverted;
1348 #endif
1349
1350 #ifdef CONFIG_BLK
1351         mmc = &plat->mmc;
1352 #else
1353         mmc = mmc_create(cfg, priv);
1354         if (mmc == NULL)
1355                 return -1;
1356 #endif
1357
1358 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1359         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1360         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1361 #endif
1362
1363         mmc->dev = dev;
1364         upriv->mmc = mmc;
1365
1366         return omap_hsmmc_init_setup(mmc);
1367 }
1368
1369 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1370 static const struct udevice_id omap_hsmmc_ids[] = {
1371         { .compatible = "ti,omap3-hsmmc" },
1372         { .compatible = "ti,omap4-hsmmc" },
1373         { .compatible = "ti,am33xx-hsmmc" },
1374         { }
1375 };
1376 #endif
1377
1378 U_BOOT_DRIVER(omap_hsmmc) = {
1379         .name   = "omap_hsmmc",
1380         .id     = UCLASS_MMC,
1381 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1382         .of_match = omap_hsmmc_ids,
1383         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1384         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1385 #endif
1386 #ifdef CONFIG_BLK
1387         .bind = omap_hsmmc_bind,
1388 #endif
1389         .ops = &omap_hsmmc_ops,
1390         .probe  = omap_hsmmc_probe,
1391         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1392         .flags  = DM_FLAG_PRE_RELOC,
1393 };
1394 #endif