mmc: omap_hsmmc: use a default 52MHz max clock rate if none is specified
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2  * (C) Copyright 2008
3  * Texas Instruments, <www.ti.com>
4  * Sukumar Ghorai <s-ghorai@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation's version 2 of
12  * the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <config.h>
26 #include <common.h>
27 #include <malloc.h>
28 #include <memalign.h>
29 #include <mmc.h>
30 #include <part.h>
31 #include <i2c.h>
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
33 #include <palmas.h>
34 #endif
35 #include <asm/io.h>
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
40 #endif
41 #if !defined(CONFIG_SOC_KEYSTONE)
42 #include <asm/gpio.h>
43 #include <asm/arch/sys_proto.h>
44 #endif
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
47 #endif
48 #include <dm.h>
49 #include <power/regulator.h>
50
51 DECLARE_GLOBAL_DATA_PTR;
52
53 /* simplify defines to OMAP_HSMMC_USE_GPIO */
54 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
55         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
56 #define OMAP_HSMMC_USE_GPIO
57 #else
58 #undef OMAP_HSMMC_USE_GPIO
59 #endif
60
61 /* common definitions for all OMAPs */
62 #define SYSCTL_SRC      (1 << 25)
63 #define SYSCTL_SRD      (1 << 26)
64
65 #ifdef CONFIG_IODELAY_RECALIBRATION
66 struct omap_hsmmc_pinctrl_state {
67         struct pad_conf_entry *padconf;
68         int npads;
69         struct iodelay_cfg_entry *iodelay;
70         int niodelays;
71 };
72 #endif
73
74 struct omap_hsmmc_data {
75         struct hsmmc *base_addr;
76 #if !CONFIG_IS_ENABLED(DM_MMC)
77         struct mmc_config cfg;
78 #endif
79         uint bus_width;
80         uint clock;
81         ushort last_cmd;
82 #ifdef OMAP_HSMMC_USE_GPIO
83 #if CONFIG_IS_ENABLED(DM_MMC)
84         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
85         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
86         bool cd_inverted;
87 #else
88         int cd_gpio;
89         int wp_gpio;
90 #endif
91 #endif
92 #if CONFIG_IS_ENABLED(DM_MMC)
93         enum bus_mode mode;
94 #endif
95         u8 controller_flags;
96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
97         struct omap_hsmmc_adma_desc *adma_desc_table;
98         uint desc_slot;
99 #endif
100         const char *hw_rev;
101         struct udevice *pbias_supply;
102         uint signal_voltage;
103 #ifdef CONFIG_IODELAY_RECALIBRATION
104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
113 #endif
114 };
115
116 struct omap_mmc_of_data {
117         u8 controller_flags;
118 };
119
120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
121 struct omap_hsmmc_adma_desc {
122         u8 attr;
123         u8 reserved;
124         u16 len;
125         u32 addr;
126 };
127
128 #define ADMA_MAX_LEN    63488
129
130 /* Decriptor table defines */
131 #define ADMA_DESC_ATTR_VALID            BIT(0)
132 #define ADMA_DESC_ATTR_END              BIT(1)
133 #define ADMA_DESC_ATTR_INT              BIT(2)
134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
136
137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
139 #endif
140
141 /* If we fail after 1 second wait, something is really bad */
142 #define MAX_RETRY_MS    1000
143 #define MMC_TIMEOUT_MS  20
144
145 /* DMA transfers can take a long time if a lot a data is transferred.
146  * The timeout must take in account the amount of data. Let's assume
147  * that the time will never exceed 333 ms per MB (in other word we assume
148  * that the bandwidth is always above 3MB/s).
149  */
150 #define DMA_TIMEOUT_PER_MB      333
151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
155
156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
158                         unsigned int siz);
159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
162
163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
164 {
165 #if CONFIG_IS_ENABLED(DM_MMC)
166         return dev_get_priv(mmc->dev);
167 #else
168         return (struct omap_hsmmc_data *)mmc->priv;
169 #endif
170 }
171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
172 {
173 #if CONFIG_IS_ENABLED(DM_MMC)
174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
175         return &plat->cfg;
176 #else
177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
178 #endif
179 }
180
181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
183 {
184         int ret;
185
186 #ifndef CONFIG_DM_GPIO
187         if (!gpio_is_valid(gpio))
188                 return -1;
189 #endif
190         ret = gpio_request(gpio, label);
191         if (ret)
192                 return ret;
193
194         ret = gpio_direction_input(gpio);
195         if (ret)
196                 return ret;
197
198         return gpio;
199 }
200 #endif
201
202 static unsigned char mmc_board_init(struct mmc *mmc)
203 {
204 #if defined(CONFIG_OMAP34XX)
205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
206         t2_t *t2_base = (t2_t *)T2_BASE;
207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
208         u32 pbias_lite;
209 #ifdef CONFIG_MMC_OMAP36XX_PINS
210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
211 #endif
212
213         pbias_lite = readl(&t2_base->pbias_lite);
214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
217         pbias_lite &= ~PBIASLITEVMODE0;
218 #endif
219 #ifdef CONFIG_MMC_OMAP36XX_PINS
220         if (get_cpu_family() == CPU_OMAP36XX) {
221                 /* Disable extended drain IO before changing PBIAS */
222                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
223                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
224         }
225 #endif
226         writel(pbias_lite, &t2_base->pbias_lite);
227
228         writel(pbias_lite | PBIASLITEPWRDNZ1 |
229                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
230                 &t2_base->pbias_lite);
231
232 #ifdef CONFIG_MMC_OMAP36XX_PINS
233         if (get_cpu_family() == CPU_OMAP36XX)
234                 /* Enable extended drain IO after changing PBIAS */
235                 writel(wkup_ctrl |
236                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
237                                 OMAP34XX_CTRL_WKUP_CTRL);
238 #endif
239         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
240                 &t2_base->devconf0);
241
242         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
243                 &t2_base->devconf1);
244
245         /* Change from default of 52MHz to 26MHz if necessary */
246         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
247                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
248                         &t2_base->ctl_prog_io1);
249
250         writel(readl(&prcm_base->fclken1_core) |
251                 EN_MMC1 | EN_MMC2 | EN_MMC3,
252                 &prcm_base->fclken1_core);
253
254         writel(readl(&prcm_base->iclken1_core) |
255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
256                 &prcm_base->iclken1_core);
257 #endif
258
259 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
260         !CONFIG_IS_ENABLED(DM_REGULATOR)
261         /* PBIAS config needed for MMC1 only */
262         if (mmc_get_blk_desc(mmc)->devnum == 0)
263                 vmmc_pbias_config(LDO_VOLT_3V0);
264 #endif
265
266         return 0;
267 }
268
269 void mmc_init_stream(struct hsmmc *mmc_base)
270 {
271         ulong start;
272
273         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
274
275         writel(MMC_CMD0, &mmc_base->cmd);
276         start = get_timer(0);
277         while (!(readl(&mmc_base->stat) & CC_MASK)) {
278                 if (get_timer(0) - start > MAX_RETRY_MS) {
279                         printf("%s: timedout waiting for cc!\n", __func__);
280                         return;
281                 }
282         }
283         writel(CC_MASK, &mmc_base->stat)
284                 ;
285         writel(MMC_CMD0, &mmc_base->cmd)
286                 ;
287         start = get_timer(0);
288         while (!(readl(&mmc_base->stat) & CC_MASK)) {
289                 if (get_timer(0) - start > MAX_RETRY_MS) {
290                         printf("%s: timedout waiting for cc2!\n", __func__);
291                         return;
292                 }
293         }
294         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
295 }
296
297 #if CONFIG_IS_ENABLED(DM_MMC)
298 #ifdef CONFIG_IODELAY_RECALIBRATION
299 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
300 {
301         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
302         struct omap_hsmmc_pinctrl_state *pinctrl_state;
303
304         switch (priv->mode) {
305         case MMC_HS_200:
306                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
307                 break;
308         case UHS_SDR104:
309                 pinctrl_state = priv->sdr104_pinctrl_state;
310                 break;
311         case UHS_SDR50:
312                 pinctrl_state = priv->sdr50_pinctrl_state;
313                 break;
314         case UHS_DDR50:
315                 pinctrl_state = priv->ddr50_pinctrl_state;
316                 break;
317         case UHS_SDR25:
318                 pinctrl_state = priv->sdr25_pinctrl_state;
319                 break;
320         case UHS_SDR12:
321                 pinctrl_state = priv->sdr12_pinctrl_state;
322                 break;
323         case SD_HS:
324         case MMC_HS:
325         case MMC_HS_52:
326                 pinctrl_state = priv->hs_pinctrl_state;
327                 break;
328         case MMC_DDR_52:
329                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
330         default:
331                 pinctrl_state = priv->default_pinctrl_state;
332                 break;
333         }
334
335         if (!pinctrl_state)
336                 pinctrl_state = priv->default_pinctrl_state;
337
338         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
339                 if (pinctrl_state->iodelay)
340                         late_recalibrate_iodelay(pinctrl_state->padconf,
341                                                  pinctrl_state->npads,
342                                                  pinctrl_state->iodelay,
343                                                  pinctrl_state->niodelays);
344                 else
345                         do_set_mux32((*ctrl)->control_padconf_core_base,
346                                      pinctrl_state->padconf,
347                                      pinctrl_state->npads);
348         }
349 }
350 #endif
351 static void omap_hsmmc_set_timing(struct mmc *mmc)
352 {
353         u32 val;
354         struct hsmmc *mmc_base;
355         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
356
357         mmc_base = priv->base_addr;
358
359         omap_hsmmc_stop_clock(mmc_base);
360         val = readl(&mmc_base->ac12);
361         val &= ~AC12_UHSMC_MASK;
362         priv->mode = mmc->selected_mode;
363
364         if (mmc_is_mode_ddr(priv->mode))
365                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
366         else
367                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
368
369         switch (priv->mode) {
370         case MMC_HS_200:
371         case UHS_SDR104:
372                 val |= AC12_UHSMC_SDR104;
373                 break;
374         case UHS_SDR50:
375                 val |= AC12_UHSMC_SDR50;
376                 break;
377         case MMC_DDR_52:
378         case UHS_DDR50:
379                 val |= AC12_UHSMC_DDR50;
380                 break;
381         case SD_HS:
382         case MMC_HS_52:
383         case UHS_SDR25:
384                 val |= AC12_UHSMC_SDR25;
385                 break;
386         case MMC_LEGACY:
387         case MMC_HS:
388         case SD_LEGACY:
389         case UHS_SDR12:
390                 val |= AC12_UHSMC_SDR12;
391                 break;
392         default:
393                 val |= AC12_UHSMC_RES;
394                 break;
395         }
396         writel(val, &mmc_base->ac12);
397
398 #ifdef CONFIG_IODELAY_RECALIBRATION
399         omap_hsmmc_io_recalibrate(mmc);
400 #endif
401         omap_hsmmc_start_clock(mmc_base);
402 }
403
404 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
405 {
406         struct hsmmc *mmc_base;
407         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
408         u32 hctl, ac12;
409
410         mmc_base = priv->base_addr;
411
412         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
413         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
414
415         switch (signal_voltage) {
416         case MMC_SIGNAL_VOLTAGE_330:
417                 hctl |= SDVS_3V0;
418                 break;
419         case MMC_SIGNAL_VOLTAGE_180:
420                 hctl |= SDVS_1V8;
421                 ac12 |= AC12_V1V8_SIGEN;
422                 break;
423         }
424
425         writel(hctl, &mmc_base->hctl);
426         writel(ac12, &mmc_base->ac12);
427 }
428
429 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
430 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
431 {
432         int ret = -ETIMEDOUT;
433         u32 con;
434         bool dat0_high;
435         bool target_dat0_high = !!state;
436         struct omap_hsmmc_data *priv = dev_get_priv(dev);
437         struct hsmmc *mmc_base = priv->base_addr;
438
439         con = readl(&mmc_base->con);
440         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
441
442         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
443         while (timeout--)       {
444                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
445                 if (dat0_high == target_dat0_high) {
446                         ret = 0;
447                         break;
448                 }
449                 udelay(10);
450         }
451         writel(con, &mmc_base->con);
452
453         return ret;
454 }
455 #endif
456
457 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
458 #if CONFIG_IS_ENABLED(DM_REGULATOR)
459 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
460 {
461         int ret = 0;
462         int uV = mV * 1000;
463
464         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
465
466         if (!mmc->vqmmc_supply)
467                 return 0;
468
469         /* Disable PBIAS */
470         ret = regulator_set_enable(priv->pbias_supply, false);
471         if (ret && ret != -ENOSYS)
472                 return ret;
473
474         /* Turn off IO voltage */
475         ret = regulator_set_enable(mmc->vqmmc_supply, false);
476         if (ret && ret != -ENOSYS)
477                 return ret;
478         /* Program a new IO voltage value */
479         ret = regulator_set_value(mmc->vqmmc_supply, uV);
480         if (ret)
481                 return ret;
482         /* Turn on IO voltage */
483         ret = regulator_set_enable(mmc->vqmmc_supply, true);
484         if (ret && ret != -ENOSYS)
485                 return ret;
486
487         /* Program PBIAS voltage*/
488         ret = regulator_set_value(priv->pbias_supply, uV);
489         if (ret && ret != -ENOSYS)
490                 return ret;
491         /* Enable PBIAS */
492         ret = regulator_set_enable(priv->pbias_supply, true);
493         if (ret && ret != -ENOSYS)
494                 return ret;
495
496         return 0;
497 }
498 #endif
499
500 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
501 {
502         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
503         struct hsmmc *mmc_base = priv->base_addr;
504         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
505         u32 capa_mask;
506         __maybe_unused u8 palmas_ldo_volt;
507         u32 val;
508
509         if (mv < 0)
510                 return -EINVAL;
511
512         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
513                 /* Use 3.0V rather than 3.3V */
514                 mv = 3000;
515                 capa_mask = VS30_3V0SUP;
516                 palmas_ldo_volt = LDO_VOLT_3V0;
517         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
518                 capa_mask = VS18_1V8SUP;
519                 palmas_ldo_volt = LDO_VOLT_1V8;
520         } else {
521                 return -EOPNOTSUPP;
522         }
523
524         val = readl(&mmc_base->capa);
525         if (!(val & capa_mask))
526                 return -EOPNOTSUPP;
527
528         priv->signal_voltage = mmc->signal_voltage;
529
530         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
531
532 #if CONFIG_IS_ENABLED(DM_REGULATOR)
533         return omap_hsmmc_set_io_regulator(mmc, mv);
534 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
535         defined(CONFIG_PALMAS_POWER)
536         if (mmc_get_blk_desc(mmc)->devnum == 0)
537                 vmmc_pbias_config(palmas_ldo_volt);
538         return 0;
539 #else
540         return 0;
541 #endif
542 }
543 #endif
544
545 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
546 {
547         struct hsmmc *mmc_base;
548         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
549         u32 val;
550
551         mmc_base = priv->base_addr;
552         val = readl(&mmc_base->capa);
553
554         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
555                 val |= (VS30_3V0SUP | VS18_1V8SUP);
556         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
557                 val |= VS30_3V0SUP;
558                 val &= ~VS18_1V8SUP;
559         } else {
560                 val |= VS18_1V8SUP;
561                 val &= ~VS30_3V0SUP;
562         }
563
564         writel(val, &mmc_base->capa);
565
566         return val;
567 }
568
569 #ifdef MMC_SUPPORTS_TUNING
570 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
571 {
572         struct hsmmc *mmc_base;
573         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
574         u32 val;
575
576         mmc_base = priv->base_addr;
577         val = readl(&mmc_base->ac12);
578         val &= ~(AC12_SCLK_SEL);
579         writel(val, &mmc_base->ac12);
580
581         val = readl(&mmc_base->dll);
582         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
583         writel(val, &mmc_base->dll);
584 }
585
586 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
587 {
588         int i;
589         struct hsmmc *mmc_base;
590         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
591         u32 val;
592
593         mmc_base = priv->base_addr;
594         val = readl(&mmc_base->dll);
595         val |= DLL_FORCE_VALUE;
596         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
597         val |= (count << DLL_FORCE_SR_C_SHIFT);
598         writel(val, &mmc_base->dll);
599
600         val |= DLL_CALIB;
601         writel(val, &mmc_base->dll);
602         for (i = 0; i < 1000; i++) {
603                 if (readl(&mmc_base->dll) & DLL_CALIB)
604                         break;
605         }
606         val &= ~DLL_CALIB;
607         writel(val, &mmc_base->dll);
608 }
609
610 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
611 {
612         struct omap_hsmmc_data *priv = dev_get_priv(dev);
613         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
614         struct mmc *mmc = upriv->mmc;
615         struct hsmmc *mmc_base;
616         u32 val;
617         u8 cur_match, prev_match = 0;
618         int ret;
619         u32 phase_delay = 0;
620         u32 start_window = 0, max_window = 0;
621         u32 length = 0, max_len = 0;
622
623         mmc_base = priv->base_addr;
624         val = readl(&mmc_base->capa2);
625
626         /* clock tuning is not needed for upto 52MHz */
627         if (!((mmc->selected_mode == MMC_HS_200) ||
628               (mmc->selected_mode == UHS_SDR104) ||
629               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
630                 return 0;
631
632         val = readl(&mmc_base->dll);
633         val |= DLL_SWT;
634         writel(val, &mmc_base->dll);
635         while (phase_delay <= MAX_PHASE_DELAY) {
636                 omap_hsmmc_set_dll(mmc, phase_delay);
637
638                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
639
640                 if (cur_match) {
641                         if (prev_match) {
642                                 length++;
643                         } else {
644                                 start_window = phase_delay;
645                                 length = 1;
646                         }
647                 }
648
649                 if (length > max_len) {
650                         max_window = start_window;
651                         max_len = length;
652                 }
653
654                 prev_match = cur_match;
655                 phase_delay += 4;
656         }
657
658         if (!max_len) {
659                 ret = -EIO;
660                 goto tuning_error;
661         }
662
663         val = readl(&mmc_base->ac12);
664         if (!(val & AC12_SCLK_SEL)) {
665                 ret = -EIO;
666                 goto tuning_error;
667         }
668
669         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
670         omap_hsmmc_set_dll(mmc, phase_delay);
671
672         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
673         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
674
675         return 0;
676
677 tuning_error:
678
679         omap_hsmmc_disable_tuning(mmc);
680         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
681         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
682
683         return ret;
684 }
685 #endif
686
687 static void omap_hsmmc_send_init_stream(struct udevice *dev)
688 {
689         struct omap_hsmmc_data *priv = dev_get_priv(dev);
690         struct hsmmc *mmc_base = priv->base_addr;
691
692         mmc_init_stream(mmc_base);
693 }
694 #endif
695
696 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
697 {
698         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
699         struct hsmmc *mmc_base = priv->base_addr;
700         u32 irq_mask = INT_EN_MASK;
701
702         /*
703          * TODO: Errata i802 indicates only DCRC interrupts can occur during
704          * tuning procedure and DCRC should be disabled. But see occurences
705          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
706          * interrupts occur along with BRR, so the data is actually in the
707          * buffer. It has to be debugged why these interrutps occur
708          */
709         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
710                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
711
712         writel(irq_mask, &mmc_base->ie);
713 }
714
715 static int omap_hsmmc_init_setup(struct mmc *mmc)
716 {
717         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
718         struct hsmmc *mmc_base;
719         unsigned int reg_val;
720         unsigned int dsor;
721         ulong start;
722
723         mmc_base = priv->base_addr;
724         mmc_board_init(mmc);
725
726         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
727                 &mmc_base->sysconfig);
728         start = get_timer(0);
729         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
730                 if (get_timer(0) - start > MAX_RETRY_MS) {
731                         printf("%s: timedout waiting for cc2!\n", __func__);
732                         return -ETIMEDOUT;
733                 }
734         }
735         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
736         start = get_timer(0);
737         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
738                 if (get_timer(0) - start > MAX_RETRY_MS) {
739                         printf("%s: timedout waiting for softresetall!\n",
740                                 __func__);
741                         return -ETIMEDOUT;
742                 }
743         }
744 #ifdef CONFIG_MMC_OMAP_HS_ADMA
745         reg_val = readl(&mmc_base->hl_hwinfo);
746         if (reg_val & MADMA_EN)
747                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
748 #endif
749
750 #if CONFIG_IS_ENABLED(DM_MMC)
751         reg_val = omap_hsmmc_set_capabilities(mmc);
752         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ?
753                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
754 #else
755         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
756         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
757                 &mmc_base->capa);
758 #endif
759
760         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
761
762         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
763                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
764                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
765
766         dsor = 240;
767         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
768                 (ICE_STOP | DTO_15THDTO));
769         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
770                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
771         start = get_timer(0);
772         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
773                 if (get_timer(0) - start > MAX_RETRY_MS) {
774                         printf("%s: timedout waiting for ics!\n", __func__);
775                         return -ETIMEDOUT;
776                 }
777         }
778         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
779
780         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
781
782         mmc_enable_irq(mmc, NULL);
783
784 #if !CONFIG_IS_ENABLED(DM_MMC)
785         mmc_init_stream(mmc_base);
786 #endif
787
788         return 0;
789 }
790
791 /*
792  * MMC controller internal finite state machine reset
793  *
794  * Used to reset command or data internal state machines, using respectively
795  * SRC or SRD bit of SYSCTL register
796  */
797 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
798 {
799         ulong start;
800
801         mmc_reg_out(&mmc_base->sysctl, bit, bit);
802
803         /*
804          * CMD(DAT) lines reset procedures are slightly different
805          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
806          * According to OMAP3 TRM:
807          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
808          * returns to 0x0.
809          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
810          * procedure steps must be as follows:
811          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
812          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
813          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
814          * 3. Wait until the SRC (SRD) bit returns to 0x0
815          *    (reset procedure is completed).
816          */
817 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
818         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
819         if (!(readl(&mmc_base->sysctl) & bit)) {
820                 start = get_timer(0);
821                 while (!(readl(&mmc_base->sysctl) & bit)) {
822                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
823                                 return;
824                 }
825         }
826 #endif
827         start = get_timer(0);
828         while ((readl(&mmc_base->sysctl) & bit) != 0) {
829                 if (get_timer(0) - start > MAX_RETRY_MS) {
830                         printf("%s: timedout waiting for sysctl %x to clear\n",
831                                 __func__, bit);
832                         return;
833                 }
834         }
835 }
836
837 #ifdef CONFIG_MMC_OMAP_HS_ADMA
838 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
839 {
840         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
841         struct omap_hsmmc_adma_desc *desc;
842         u8 attr;
843
844         desc = &priv->adma_desc_table[priv->desc_slot];
845
846         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
847         if (!end)
848                 priv->desc_slot++;
849         else
850                 attr |= ADMA_DESC_ATTR_END;
851
852         desc->len = len;
853         desc->addr = (u32)buf;
854         desc->reserved = 0;
855         desc->attr = attr;
856 }
857
858 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
859                                           struct mmc_data *data)
860 {
861         uint total_len = data->blocksize * data->blocks;
862         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
863         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
864         int i = desc_count;
865         char *buf;
866
867         priv->desc_slot = 0;
868         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
869                                 memalign(ARCH_DMA_MINALIGN, desc_count *
870                                 sizeof(struct omap_hsmmc_adma_desc));
871
872         if (data->flags & MMC_DATA_READ)
873                 buf = data->dest;
874         else
875                 buf = (char *)data->src;
876
877         while (--i) {
878                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
879                 buf += ADMA_MAX_LEN;
880                 total_len -= ADMA_MAX_LEN;
881         }
882
883         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
884
885         flush_dcache_range((long)priv->adma_desc_table,
886                            (long)priv->adma_desc_table +
887                            ROUND(desc_count *
888                            sizeof(struct omap_hsmmc_adma_desc),
889                            ARCH_DMA_MINALIGN));
890 }
891
892 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
893 {
894         struct hsmmc *mmc_base;
895         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
896         u32 val;
897         char *buf;
898
899         mmc_base = priv->base_addr;
900         omap_hsmmc_prepare_adma_table(mmc, data);
901
902         if (data->flags & MMC_DATA_READ)
903                 buf = data->dest;
904         else
905                 buf = (char *)data->src;
906
907         val = readl(&mmc_base->hctl);
908         val |= DMA_SELECT;
909         writel(val, &mmc_base->hctl);
910
911         val = readl(&mmc_base->con);
912         val |= DMA_MASTER;
913         writel(val, &mmc_base->con);
914
915         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
916
917         flush_dcache_range((u32)buf,
918                            (u32)buf +
919                            ROUND(data->blocksize * data->blocks,
920                                  ARCH_DMA_MINALIGN));
921 }
922
923 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
924 {
925         struct hsmmc *mmc_base;
926         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
927         u32 val;
928
929         mmc_base = priv->base_addr;
930
931         val = readl(&mmc_base->con);
932         val &= ~DMA_MASTER;
933         writel(val, &mmc_base->con);
934
935         val = readl(&mmc_base->hctl);
936         val &= ~DMA_SELECT;
937         writel(val, &mmc_base->hctl);
938
939         kfree(priv->adma_desc_table);
940 }
941 #else
942 #define omap_hsmmc_adma_desc
943 #define omap_hsmmc_prepare_adma_table
944 #define omap_hsmmc_prepare_data
945 #define omap_hsmmc_dma_cleanup
946 #endif
947
948 #if !CONFIG_IS_ENABLED(DM_MMC)
949 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
950                         struct mmc_data *data)
951 {
952         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
953 #else
954 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
955                         struct mmc_data *data)
956 {
957         struct omap_hsmmc_data *priv = dev_get_priv(dev);
958         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
959         struct mmc *mmc = upriv->mmc;
960 #endif
961         struct hsmmc *mmc_base;
962         unsigned int flags, mmc_stat;
963         ulong start;
964         priv->last_cmd = cmd->cmdidx;
965
966         mmc_base = priv->base_addr;
967
968         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
969                 return 0;
970
971         start = get_timer(0);
972         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
973                 if (get_timer(0) - start > MAX_RETRY_MS) {
974                         printf("%s: timedout waiting on cmd inhibit to clear\n",
975                                         __func__);
976                         return -ETIMEDOUT;
977                 }
978         }
979         writel(0xFFFFFFFF, &mmc_base->stat);
980         start = get_timer(0);
981         while (readl(&mmc_base->stat)) {
982                 if (get_timer(0) - start > MAX_RETRY_MS) {
983                         printf("%s: timedout waiting for STAT (%x) to clear\n",
984                                 __func__, readl(&mmc_base->stat));
985                         return -ETIMEDOUT;
986                 }
987         }
988         /*
989          * CMDREG
990          * CMDIDX[13:8] : Command index
991          * DATAPRNT[5]  : Data Present Select
992          * ENCMDIDX[4]  : Command Index Check Enable
993          * ENCMDCRC[3]  : Command CRC Check Enable
994          * RSPTYP[1:0]
995          *      00 = No Response
996          *      01 = Length 136
997          *      10 = Length 48
998          *      11 = Length 48 Check busy after response
999          */
1000         /* Delay added before checking the status of frq change
1001          * retry not supported by mmc.c(core file)
1002          */
1003         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1004                 udelay(50000); /* wait 50 ms */
1005
1006         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1007                 flags = 0;
1008         else if (cmd->resp_type & MMC_RSP_136)
1009                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1010         else if (cmd->resp_type & MMC_RSP_BUSY)
1011                 flags = RSP_TYPE_LGHT48B;
1012         else
1013                 flags = RSP_TYPE_LGHT48;
1014
1015         /* enable default flags */
1016         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1017                         MSBS_SGLEBLK);
1018         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1019
1020         if (cmd->resp_type & MMC_RSP_CRC)
1021                 flags |= CCCE_CHECK;
1022         if (cmd->resp_type & MMC_RSP_OPCODE)
1023                 flags |= CICE_CHECK;
1024
1025         if (data) {
1026                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1027                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1028                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1029                         data->blocksize = 512;
1030                         writel(data->blocksize | (data->blocks << 16),
1031                                                         &mmc_base->blk);
1032                 } else
1033                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1034
1035                 if (data->flags & MMC_DATA_READ)
1036                         flags |= (DP_DATA | DDIR_READ);
1037                 else
1038                         flags |= (DP_DATA | DDIR_WRITE);
1039
1040 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1041                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1042                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1043                         omap_hsmmc_prepare_data(mmc, data);
1044                         flags |= DE_ENABLE;
1045                 }
1046 #endif
1047         }
1048
1049         mmc_enable_irq(mmc, cmd);
1050
1051         writel(cmd->cmdarg, &mmc_base->arg);
1052         udelay(20);             /* To fix "No status update" error on eMMC */
1053         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1054
1055         start = get_timer(0);
1056         do {
1057                 mmc_stat = readl(&mmc_base->stat);
1058                 if (get_timer(start) > MAX_RETRY_MS) {
1059                         printf("%s : timeout: No status update\n", __func__);
1060                         return -ETIMEDOUT;
1061                 }
1062         } while (!mmc_stat);
1063
1064         if ((mmc_stat & IE_CTO) != 0) {
1065                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1066                 return -ETIMEDOUT;
1067         } else if ((mmc_stat & ERRI_MASK) != 0)
1068                 return -1;
1069
1070         if (mmc_stat & CC_MASK) {
1071                 writel(CC_MASK, &mmc_base->stat);
1072                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1073                         if (cmd->resp_type & MMC_RSP_136) {
1074                                 /* response type 2 */
1075                                 cmd->response[3] = readl(&mmc_base->rsp10);
1076                                 cmd->response[2] = readl(&mmc_base->rsp32);
1077                                 cmd->response[1] = readl(&mmc_base->rsp54);
1078                                 cmd->response[0] = readl(&mmc_base->rsp76);
1079                         } else
1080                                 /* response types 1, 1b, 3, 4, 5, 6 */
1081                                 cmd->response[0] = readl(&mmc_base->rsp10);
1082                 }
1083         }
1084
1085 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1086         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1087             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1088                 u32 sz_mb, timeout;
1089
1090                 if (mmc_stat & IE_ADMAE) {
1091                         omap_hsmmc_dma_cleanup(mmc);
1092                         return -EIO;
1093                 }
1094
1095                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1096                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1097                 if (timeout < MAX_RETRY_MS)
1098                         timeout = MAX_RETRY_MS;
1099
1100                 start = get_timer(0);
1101                 do {
1102                         mmc_stat = readl(&mmc_base->stat);
1103                         if (mmc_stat & TC_MASK) {
1104                                 writel(readl(&mmc_base->stat) | TC_MASK,
1105                                        &mmc_base->stat);
1106                                 break;
1107                         }
1108                         if (get_timer(start) > timeout) {
1109                                 printf("%s : DMA timeout: No status update\n",
1110                                        __func__);
1111                                 return -ETIMEDOUT;
1112                         }
1113                 } while (1);
1114
1115                 omap_hsmmc_dma_cleanup(mmc);
1116                 return 0;
1117         }
1118 #endif
1119
1120         if (data && (data->flags & MMC_DATA_READ)) {
1121                 mmc_read_data(mmc_base, data->dest,
1122                                 data->blocksize * data->blocks);
1123         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1124                 mmc_write_data(mmc_base, data->src,
1125                                 data->blocksize * data->blocks);
1126         }
1127         return 0;
1128 }
1129
1130 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1131 {
1132         unsigned int *output_buf = (unsigned int *)buf;
1133         unsigned int mmc_stat;
1134         unsigned int count;
1135
1136         /*
1137          * Start Polled Read
1138          */
1139         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1140         count /= 4;
1141
1142         while (size) {
1143                 ulong start = get_timer(0);
1144                 do {
1145                         mmc_stat = readl(&mmc_base->stat);
1146                         if (get_timer(0) - start > MAX_RETRY_MS) {
1147                                 printf("%s: timedout waiting for status!\n",
1148                                                 __func__);
1149                                 return -ETIMEDOUT;
1150                         }
1151                 } while (mmc_stat == 0);
1152
1153                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1154                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1155
1156                 if ((mmc_stat & ERRI_MASK) != 0)
1157                         return 1;
1158
1159                 if (mmc_stat & BRR_MASK) {
1160                         unsigned int k;
1161
1162                         writel(readl(&mmc_base->stat) | BRR_MASK,
1163                                 &mmc_base->stat);
1164                         for (k = 0; k < count; k++) {
1165                                 *output_buf = readl(&mmc_base->data);
1166                                 output_buf++;
1167                         }
1168                         size -= (count*4);
1169                 }
1170
1171                 if (mmc_stat & BWR_MASK)
1172                         writel(readl(&mmc_base->stat) | BWR_MASK,
1173                                 &mmc_base->stat);
1174
1175                 if (mmc_stat & TC_MASK) {
1176                         writel(readl(&mmc_base->stat) | TC_MASK,
1177                                 &mmc_base->stat);
1178                         break;
1179                 }
1180         }
1181         return 0;
1182 }
1183
1184 #if CONFIG_IS_ENABLED(MMC_WRITE)
1185 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1186                           unsigned int size)
1187 {
1188         unsigned int *input_buf = (unsigned int *)buf;
1189         unsigned int mmc_stat;
1190         unsigned int count;
1191
1192         /*
1193          * Start Polled Write
1194          */
1195         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1196         count /= 4;
1197
1198         while (size) {
1199                 ulong start = get_timer(0);
1200                 do {
1201                         mmc_stat = readl(&mmc_base->stat);
1202                         if (get_timer(0) - start > MAX_RETRY_MS) {
1203                                 printf("%s: timedout waiting for status!\n",
1204                                                 __func__);
1205                                 return -ETIMEDOUT;
1206                         }
1207                 } while (mmc_stat == 0);
1208
1209                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1210                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1211
1212                 if ((mmc_stat & ERRI_MASK) != 0)
1213                         return 1;
1214
1215                 if (mmc_stat & BWR_MASK) {
1216                         unsigned int k;
1217
1218                         writel(readl(&mmc_base->stat) | BWR_MASK,
1219                                         &mmc_base->stat);
1220                         for (k = 0; k < count; k++) {
1221                                 writel(*input_buf, &mmc_base->data);
1222                                 input_buf++;
1223                         }
1224                         size -= (count*4);
1225                 }
1226
1227                 if (mmc_stat & BRR_MASK)
1228                         writel(readl(&mmc_base->stat) | BRR_MASK,
1229                                 &mmc_base->stat);
1230
1231                 if (mmc_stat & TC_MASK) {
1232                         writel(readl(&mmc_base->stat) | TC_MASK,
1233                                 &mmc_base->stat);
1234                         break;
1235                 }
1236         }
1237         return 0;
1238 }
1239 #else
1240 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1241                           unsigned int size)
1242 {
1243         return -ENOTSUPP;
1244 }
1245 #endif
1246 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1247 {
1248         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1249 }
1250
1251 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1252 {
1253         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1254 }
1255
1256 static void omap_hsmmc_set_clock(struct mmc *mmc)
1257 {
1258         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1259         struct hsmmc *mmc_base;
1260         unsigned int dsor = 0;
1261         ulong start;
1262
1263         mmc_base = priv->base_addr;
1264         omap_hsmmc_stop_clock(mmc_base);
1265
1266         /* TODO: Is setting DTO required here? */
1267         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1268                     (ICE_STOP | DTO_15THDTO));
1269
1270         if (mmc->clock != 0) {
1271                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1272                 if (dsor > CLKD_MAX)
1273                         dsor = CLKD_MAX;
1274         } else {
1275                 dsor = CLKD_MAX;
1276         }
1277
1278         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1279                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1280
1281         start = get_timer(0);
1282         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1283                 if (get_timer(0) - start > MAX_RETRY_MS) {
1284                         printf("%s: timedout waiting for ics!\n", __func__);
1285                         return;
1286                 }
1287         }
1288
1289         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1290         mmc->clock = priv->clock;
1291         omap_hsmmc_start_clock(mmc_base);
1292 }
1293
1294 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1295 {
1296         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1297         struct hsmmc *mmc_base;
1298
1299         mmc_base = priv->base_addr;
1300         /* configue bus width */
1301         switch (mmc->bus_width) {
1302         case 8:
1303                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1304                         &mmc_base->con);
1305                 break;
1306
1307         case 4:
1308                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1309                         &mmc_base->con);
1310                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1311                         &mmc_base->hctl);
1312                 break;
1313
1314         case 1:
1315         default:
1316                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1317                         &mmc_base->con);
1318                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1319                         &mmc_base->hctl);
1320                 break;
1321         }
1322
1323         priv->bus_width = mmc->bus_width;
1324 }
1325
1326 #if !CONFIG_IS_ENABLED(DM_MMC)
1327 static int omap_hsmmc_set_ios(struct mmc *mmc)
1328 {
1329         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1330 #else
1331 static int omap_hsmmc_set_ios(struct udevice *dev)
1332 {
1333         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1334         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1335         struct mmc *mmc = upriv->mmc;
1336 #endif
1337         struct hsmmc *mmc_base = priv->base_addr;
1338         int ret = 0;
1339
1340         if (priv->bus_width != mmc->bus_width)
1341                 omap_hsmmc_set_bus_width(mmc);
1342
1343         if (priv->clock != mmc->clock)
1344                 omap_hsmmc_set_clock(mmc);
1345
1346         if (mmc->clk_disable)
1347                 omap_hsmmc_stop_clock(mmc_base);
1348         else
1349                 omap_hsmmc_start_clock(mmc_base);
1350
1351 #if CONFIG_IS_ENABLED(DM_MMC)
1352         if (priv->mode != mmc->selected_mode)
1353                 omap_hsmmc_set_timing(mmc);
1354
1355 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1356         if (priv->signal_voltage != mmc->signal_voltage)
1357                 ret = omap_hsmmc_set_signal_voltage(mmc);
1358 #endif
1359 #endif
1360         return ret;
1361 }
1362
1363 #ifdef OMAP_HSMMC_USE_GPIO
1364 #if CONFIG_IS_ENABLED(DM_MMC)
1365 static int omap_hsmmc_getcd(struct udevice *dev)
1366 {
1367         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1368         int value;
1369
1370         value = dm_gpio_get_value(&priv->cd_gpio);
1371         /* if no CD return as 1 */
1372         if (value < 0)
1373                 return 1;
1374
1375         if (priv->cd_inverted)
1376                 return !value;
1377         return value;
1378 }
1379
1380 static int omap_hsmmc_getwp(struct udevice *dev)
1381 {
1382         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1383         int value;
1384
1385         value = dm_gpio_get_value(&priv->wp_gpio);
1386         /* if no WP return as 0 */
1387         if (value < 0)
1388                 return 0;
1389         return value;
1390 }
1391 #else
1392 static int omap_hsmmc_getcd(struct mmc *mmc)
1393 {
1394         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1395         int cd_gpio;
1396
1397         /* if no CD return as 1 */
1398         cd_gpio = priv->cd_gpio;
1399         if (cd_gpio < 0)
1400                 return 1;
1401
1402         /* NOTE: assumes card detect signal is active-low */
1403         return !gpio_get_value(cd_gpio);
1404 }
1405
1406 static int omap_hsmmc_getwp(struct mmc *mmc)
1407 {
1408         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1409         int wp_gpio;
1410
1411         /* if no WP return as 0 */
1412         wp_gpio = priv->wp_gpio;
1413         if (wp_gpio < 0)
1414                 return 0;
1415
1416         /* NOTE: assumes write protect signal is active-high */
1417         return gpio_get_value(wp_gpio);
1418 }
1419 #endif
1420 #endif
1421
1422 #if CONFIG_IS_ENABLED(DM_MMC)
1423 static const struct dm_mmc_ops omap_hsmmc_ops = {
1424         .send_cmd       = omap_hsmmc_send_cmd,
1425         .set_ios        = omap_hsmmc_set_ios,
1426 #ifdef OMAP_HSMMC_USE_GPIO
1427         .get_cd         = omap_hsmmc_getcd,
1428         .get_wp         = omap_hsmmc_getwp,
1429 #endif
1430 #ifdef MMC_SUPPORTS_TUNING
1431         .execute_tuning = omap_hsmmc_execute_tuning,
1432 #endif
1433         .send_init_stream       = omap_hsmmc_send_init_stream,
1434 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1435         .wait_dat0      = omap_hsmmc_wait_dat0,
1436 #endif
1437 };
1438 #else
1439 static const struct mmc_ops omap_hsmmc_ops = {
1440         .send_cmd       = omap_hsmmc_send_cmd,
1441         .set_ios        = omap_hsmmc_set_ios,
1442         .init           = omap_hsmmc_init_setup,
1443 #ifdef OMAP_HSMMC_USE_GPIO
1444         .getcd          = omap_hsmmc_getcd,
1445         .getwp          = omap_hsmmc_getwp,
1446 #endif
1447 };
1448 #endif
1449
1450 #if !CONFIG_IS_ENABLED(DM_MMC)
1451 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1452                 int wp_gpio)
1453 {
1454         struct mmc *mmc;
1455         struct omap_hsmmc_data *priv;
1456         struct mmc_config *cfg;
1457         uint host_caps_val;
1458
1459         priv = calloc(1, sizeof(*priv));
1460         if (priv == NULL)
1461                 return -1;
1462
1463         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1464
1465         switch (dev_index) {
1466         case 0:
1467                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1468                 break;
1469 #ifdef OMAP_HSMMC2_BASE
1470         case 1:
1471                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1472 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1473         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1474         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1475                 defined(CONFIG_HSMMC2_8BIT)
1476                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1477                 host_caps_val |= MMC_MODE_8BIT;
1478 #endif
1479                 break;
1480 #endif
1481 #ifdef OMAP_HSMMC3_BASE
1482         case 2:
1483                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1484 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1485                 /* Enable 8-bit interface for eMMC on DRA7XX */
1486                 host_caps_val |= MMC_MODE_8BIT;
1487 #endif
1488                 break;
1489 #endif
1490         default:
1491                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1492                 return 1;
1493         }
1494 #ifdef OMAP_HSMMC_USE_GPIO
1495         /* on error gpio values are set to -1, which is what we want */
1496         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1497         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1498 #endif
1499
1500         cfg = &priv->cfg;
1501
1502         cfg->name = "OMAP SD/MMC";
1503         cfg->ops = &omap_hsmmc_ops;
1504
1505         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1506         cfg->host_caps = host_caps_val & ~host_caps_mask;
1507
1508         cfg->f_min = 400000;
1509
1510         if (f_max != 0)
1511                 cfg->f_max = f_max;
1512         else {
1513                 if (cfg->host_caps & MMC_MODE_HS) {
1514                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1515                                 cfg->f_max = 52000000;
1516                         else
1517                                 cfg->f_max = 26000000;
1518                 } else
1519                         cfg->f_max = 20000000;
1520         }
1521
1522         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1523
1524 #if defined(CONFIG_OMAP34XX)
1525         /*
1526          * Silicon revs 2.1 and older do not support multiblock transfers.
1527          */
1528         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1529                 cfg->b_max = 1;
1530 #endif
1531
1532         mmc = mmc_create(cfg, priv);
1533         if (mmc == NULL)
1534                 return -1;
1535
1536         return 0;
1537 }
1538 #else
1539
1540 #ifdef CONFIG_IODELAY_RECALIBRATION
1541 static struct pad_conf_entry *
1542 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1543 {
1544         int index = 0;
1545         struct pad_conf_entry *padconf;
1546
1547         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1548         if (!padconf) {
1549                 debug("failed to allocate memory\n");
1550                 return 0;
1551         }
1552
1553         while (index < count) {
1554                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1555                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1556                 index++;
1557         }
1558
1559         return padconf;
1560 }
1561
1562 static struct iodelay_cfg_entry *
1563 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1564 {
1565         int index = 0;
1566         struct iodelay_cfg_entry *iodelay;
1567
1568         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1569         if (!iodelay) {
1570                 debug("failed to allocate memory\n");
1571                 return 0;
1572         }
1573
1574         while (index < count) {
1575                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1576                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1577                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1578                 index++;
1579         }
1580
1581         return iodelay;
1582 }
1583
1584 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1585                                                    const char *name, int *len)
1586 {
1587         const void *fdt = gd->fdt_blob;
1588         int offset;
1589         const fdt32_t *pinctrl;
1590
1591         offset = fdt_node_offset_by_phandle(fdt, phandle);
1592         if (offset < 0) {
1593                 debug("failed to get pinctrl node %s.\n",
1594                       fdt_strerror(offset));
1595                 return 0;
1596         }
1597
1598         pinctrl = fdt_getprop(fdt, offset, name, len);
1599         if (!pinctrl) {
1600                 debug("failed to get property %s\n", name);
1601                 return 0;
1602         }
1603
1604         return pinctrl;
1605 }
1606
1607 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1608                                                 char *prop_name)
1609 {
1610         const void *fdt = gd->fdt_blob;
1611         const __be32 *phandle;
1612         int node = dev_of_offset(mmc->dev);
1613
1614         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1615         if (!phandle) {
1616                 debug("failed to get property %s\n", prop_name);
1617                 return 0;
1618         }
1619
1620         return fdt32_to_cpu(*phandle);
1621 }
1622
1623 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1624                                                char *prop_name)
1625 {
1626         const void *fdt = gd->fdt_blob;
1627         const __be32 *phandle;
1628         int len;
1629         int count;
1630         int node = dev_of_offset(mmc->dev);
1631
1632         phandle = fdt_getprop(fdt, node, prop_name, &len);
1633         if (!phandle) {
1634                 debug("failed to get property %s\n", prop_name);
1635                 return 0;
1636         }
1637
1638         /* No manual mode iodelay values if count < 2 */
1639         count = len / sizeof(*phandle);
1640         if (count < 2)
1641                 return 0;
1642
1643         return fdt32_to_cpu(*(phandle + 1));
1644 }
1645
1646 static struct pad_conf_entry *
1647 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1648 {
1649         int len;
1650         int count;
1651         struct pad_conf_entry *padconf;
1652         u32 phandle;
1653         const fdt32_t *pinctrl;
1654
1655         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1656         if (!phandle)
1657                 return ERR_PTR(-EINVAL);
1658
1659         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1660                                                &len);
1661         if (!pinctrl)
1662                 return ERR_PTR(-EINVAL);
1663
1664         count = (len / sizeof(*pinctrl)) / 2;
1665         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1666         if (!padconf)
1667                 return ERR_PTR(-EINVAL);
1668
1669         *npads = count;
1670
1671         return padconf;
1672 }
1673
1674 static struct iodelay_cfg_entry *
1675 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1676 {
1677         int len;
1678         int count;
1679         struct iodelay_cfg_entry *iodelay;
1680         u32 phandle;
1681         const fdt32_t *pinctrl;
1682
1683         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1684         /* Not all modes have manual mode iodelay values. So its not fatal */
1685         if (!phandle)
1686                 return 0;
1687
1688         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1689                                                &len);
1690         if (!pinctrl)
1691                 return ERR_PTR(-EINVAL);
1692
1693         count = (len / sizeof(*pinctrl)) / 3;
1694         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1695         if (!iodelay)
1696                 return ERR_PTR(-EINVAL);
1697
1698         *niodelay = count;
1699
1700         return iodelay;
1701 }
1702
1703 static struct omap_hsmmc_pinctrl_state *
1704 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1705 {
1706         int index;
1707         int npads = 0;
1708         int niodelays = 0;
1709         const void *fdt = gd->fdt_blob;
1710         int node = dev_of_offset(mmc->dev);
1711         char prop_name[11];
1712         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1713
1714         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1715                          malloc(sizeof(*pinctrl_state));
1716         if (!pinctrl_state) {
1717                 debug("failed to allocate memory\n");
1718                 return 0;
1719         }
1720
1721         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1722         if (index < 0) {
1723                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1724                 goto err_pinctrl_state;
1725         }
1726
1727         sprintf(prop_name, "pinctrl-%d", index);
1728
1729         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1730                                                          &npads);
1731         if (IS_ERR(pinctrl_state->padconf))
1732                 goto err_pinctrl_state;
1733         pinctrl_state->npads = npads;
1734
1735         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1736                                                         &niodelays);
1737         if (IS_ERR(pinctrl_state->iodelay))
1738                 goto err_padconf;
1739         pinctrl_state->niodelays = niodelays;
1740
1741         return pinctrl_state;
1742
1743 err_padconf:
1744         kfree(pinctrl_state->padconf);
1745
1746 err_pinctrl_state:
1747         kfree(pinctrl_state);
1748         return 0;
1749 }
1750
1751 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1752         do {                                                            \
1753                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1754                 char str[20];                                           \
1755                 if (!(cfg->host_caps & capmask))                        \
1756                         break;                                          \
1757                                                                         \
1758                 if (priv->hw_rev) {                                     \
1759                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1760                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1761                 }                                                       \
1762                                                                         \
1763                 if (!s)                                                 \
1764                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1765                                                                         \
1766                 if (!s && !optional) {                                  \
1767                         debug("%s: no pinctrl for %s\n",                \
1768                               mmc->dev->name, #mode);                   \
1769                         cfg->host_caps &= ~(capmask);                   \
1770                 } else {                                                \
1771                         priv->mode##_pinctrl_state = s;                 \
1772                 }                                                       \
1773         } while (0)
1774
1775 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1776 {
1777         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1778         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1779         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1780
1781         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1782                 return 0;
1783
1784         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1785         if (!default_pinctrl) {
1786                 printf("no pinctrl state for default mode\n");
1787                 return -EINVAL;
1788         }
1789
1790         priv->default_pinctrl_state = default_pinctrl;
1791
1792         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1793         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1794         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1795         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1796         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1797
1798         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1799         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1800         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1801
1802         return 0;
1803 }
1804 #endif
1805
1806 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1807 #ifdef CONFIG_OMAP54XX
1808 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1809 {
1810         return NULL;
1811 }
1812 #endif
1813
1814 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1815 {
1816         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1817         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1818
1819         struct mmc_config *cfg = &plat->cfg;
1820 #ifdef CONFIG_OMAP54XX
1821         const struct mmc_platform_fixups *fixups;
1822 #endif
1823         const void *fdt = gd->fdt_blob;
1824         int node = dev_of_offset(dev);
1825         int ret;
1826
1827         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1828                                       sizeof(struct hsmmc *),
1829                                       MAP_NOCACHE);
1830
1831         ret = mmc_of_parse(dev, cfg);
1832         if (ret < 0)
1833                 return ret;
1834
1835         if (!cfg->f_max)
1836                 cfg->f_max = 52000000;
1837         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1838         cfg->f_min = 400000;
1839         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1840         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1841         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1842                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1843         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1844                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1845         if (of_data)
1846                 plat->controller_flags |= of_data->controller_flags;
1847
1848 #ifdef CONFIG_OMAP54XX
1849         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1850         if (fixups) {
1851                 plat->hw_rev = fixups->hw_rev;
1852                 cfg->host_caps &= ~fixups->unsupported_caps;
1853                 cfg->f_max = fixups->max_freq;
1854         }
1855 #endif
1856
1857 #ifdef OMAP_HSMMC_USE_GPIO
1858         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1859 #endif
1860
1861         return 0;
1862 }
1863 #endif
1864
1865 #ifdef CONFIG_BLK
1866
1867 static int omap_hsmmc_bind(struct udevice *dev)
1868 {
1869         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1870         plat->mmc = calloc(1, sizeof(struct mmc));
1871         return mmc_bind(dev, plat->mmc, &plat->cfg);
1872 }
1873 #endif
1874 static int omap_hsmmc_probe(struct udevice *dev)
1875 {
1876         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1877         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1878         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1879         struct mmc_config *cfg = &plat->cfg;
1880         struct mmc *mmc;
1881 #ifdef CONFIG_IODELAY_RECALIBRATION
1882         int ret;
1883 #endif
1884
1885         cfg->name = "OMAP SD/MMC";
1886         priv->base_addr = plat->base_addr;
1887         priv->controller_flags = plat->controller_flags;
1888         priv->hw_rev = plat->hw_rev;
1889 #ifdef OMAP_HSMMC_USE_GPIO
1890         priv->cd_inverted = plat->cd_inverted;
1891 #endif
1892
1893 #ifdef CONFIG_BLK
1894         mmc = plat->mmc;
1895 #else
1896         mmc = mmc_create(cfg, priv);
1897         if (mmc == NULL)
1898                 return -1;
1899 #endif
1900 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1901         device_get_supply_regulator(dev, "pbias-supply",
1902                                     &priv->pbias_supply);
1903 #endif
1904 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1905         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1906         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1907 #endif
1908
1909         mmc->dev = dev;
1910         upriv->mmc = mmc;
1911
1912 #ifdef CONFIG_IODELAY_RECALIBRATION
1913         ret = omap_hsmmc_get_pinctrl_state(mmc);
1914         /*
1915          * disable high speed modes for the platforms that require IO delay
1916          * and for which we don't have this information
1917          */
1918         if ((ret < 0) &&
1919             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1920                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1921                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1922                                     UHS_CAPS);
1923         }
1924 #endif
1925
1926         return omap_hsmmc_init_setup(mmc);
1927 }
1928
1929 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1930
1931 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1932         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1933 };
1934
1935 static const struct udevice_id omap_hsmmc_ids[] = {
1936         { .compatible = "ti,omap3-hsmmc" },
1937         { .compatible = "ti,omap4-hsmmc" },
1938         { .compatible = "ti,am33xx-hsmmc" },
1939         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1940         { }
1941 };
1942 #endif
1943
1944 U_BOOT_DRIVER(omap_hsmmc) = {
1945         .name   = "omap_hsmmc",
1946         .id     = UCLASS_MMC,
1947 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1948         .of_match = omap_hsmmc_ids,
1949         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1950         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1951 #endif
1952 #ifdef CONFIG_BLK
1953         .bind = omap_hsmmc_bind,
1954 #endif
1955         .ops = &omap_hsmmc_ops,
1956         .probe  = omap_hsmmc_probe,
1957         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1958         .flags  = DM_FLAG_PRE_RELOC,
1959 };
1960 #endif