NAND: Fix integer overflow in ONFI detection of chips >= 4GiB
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <common.h>
36
37 #define ENOTSUPP 524 /* Operation is not supported */
38
39 #include <malloc.h>
40 #include <watchdog.h>
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46
47 #ifdef CONFIG_MTD_PARTITIONS
48 #include <linux/mtd/partitions.h>
49 #endif
50
51 #include <asm/io.h>
52 #include <asm/errno.h>
53
54 /*
55 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
56 * a flash. NAND flash is initialized prior to interrupts so standard timers
57 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
58 * which is greater than (max NAND reset time / NAND status read time).
59 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
60 */
61 #ifndef CONFIG_SYS_NAND_RESET_CNT
62 #define CONFIG_SYS_NAND_RESET_CNT 200000
63 #endif
64
65 /* Define default oob placement schemes for large and small page devices */
66 static struct nand_ecclayout nand_oob_8 = {
67 .eccbytes = 3,
68 .eccpos = {0, 1, 2},
69 .oobfree = {
70 {.offset = 3,
71 .length = 2},
72 {.offset = 6,
73 .length = 2}}
74 };
75
76 static struct nand_ecclayout nand_oob_16 = {
77 .eccbytes = 6,
78 .eccpos = {0, 1, 2, 3, 6, 7},
79 .oobfree = {
80 {.offset = 8,
81 . length = 8}}
82 };
83
84 static struct nand_ecclayout nand_oob_64 = {
85 .eccbytes = 24,
86 .eccpos = {
87 40, 41, 42, 43, 44, 45, 46, 47,
88 48, 49, 50, 51, 52, 53, 54, 55,
89 56, 57, 58, 59, 60, 61, 62, 63},
90 .oobfree = {
91 {.offset = 2,
92 .length = 38}}
93 };
94
95 static struct nand_ecclayout nand_oob_128 = {
96 .eccbytes = 48,
97 .eccpos = {
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100, 101, 102, 103,
101 104, 105, 106, 107, 108, 109, 110, 111,
102 112, 113, 114, 115, 116, 117, 118, 119,
103 120, 121, 122, 123, 124, 125, 126, 127},
104 .oobfree = {
105 {.offset = 2,
106 .length = 78}}
107 };
108
109
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
111 int new_state);
112
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
115
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
117
118 /**
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
121 *
122 * Deselect, release chip lock and wake up anyone waiting on the device
123 */
124 static void nand_release_device (struct mtd_info *mtd)
125 {
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
128 }
129
130 /**
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
133 *
134 * Default read function for 8bit buswith
135 */
136 static uint8_t nand_read_byte(struct mtd_info *mtd)
137 {
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
140 }
141
142 /**
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
145 *
146 * Default read function for 16bit buswith with
147 * endianess conversion
148 */
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
150 {
151 struct nand_chip *chip = mtd->priv;
152 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
153 }
154
155 /**
156 * nand_read_word - [DEFAULT] read one word from the chip
157 * @mtd: MTD device structure
158 *
159 * Default read function for 16bit buswith without
160 * endianess conversion
161 */
162 static u16 nand_read_word(struct mtd_info *mtd)
163 {
164 struct nand_chip *chip = mtd->priv;
165 return readw(chip->IO_ADDR_R);
166 }
167
168 /**
169 * nand_select_chip - [DEFAULT] control CE line
170 * @mtd: MTD device structure
171 * @chipnr: chipnumber to select, -1 for deselect
172 *
173 * Default select function for 1 chip devices.
174 */
175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
176 {
177 struct nand_chip *chip = mtd->priv;
178
179 switch (chipnr) {
180 case -1:
181 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
182 break;
183 case 0:
184 break;
185
186 default:
187 BUG();
188 }
189 }
190
191 /**
192 * nand_write_buf - [DEFAULT] write buffer to chip
193 * @mtd: MTD device structure
194 * @buf: data buffer
195 * @len: number of bytes to write
196 *
197 * Default write function for 8bit buswith
198 */
199 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
200 {
201 int i;
202 struct nand_chip *chip = mtd->priv;
203
204 for (i = 0; i < len; i++)
205 writeb(buf[i], chip->IO_ADDR_W);
206 }
207
208 /**
209 * nand_read_buf - [DEFAULT] read chip data into buffer
210 * @mtd: MTD device structure
211 * @buf: buffer to store date
212 * @len: number of bytes to read
213 *
214 * Default read function for 8bit buswith
215 */
216 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
217 {
218 int i;
219 struct nand_chip *chip = mtd->priv;
220
221 for (i = 0; i < len; i++)
222 buf[i] = readb(chip->IO_ADDR_R);
223 }
224
225 /**
226 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
227 * @mtd: MTD device structure
228 * @buf: buffer containing the data to compare
229 * @len: number of bytes to compare
230 *
231 * Default verify function for 8bit buswith
232 */
233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
234 {
235 int i;
236 struct nand_chip *chip = mtd->priv;
237
238 for (i = 0; i < len; i++)
239 if (buf[i] != readb(chip->IO_ADDR_R))
240 return -EFAULT;
241 return 0;
242 }
243
244 /**
245 * nand_write_buf16 - [DEFAULT] write buffer to chip
246 * @mtd: MTD device structure
247 * @buf: data buffer
248 * @len: number of bytes to write
249 *
250 * Default write function for 16bit buswith
251 */
252 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
253 {
254 int i;
255 struct nand_chip *chip = mtd->priv;
256 u16 *p = (u16 *) buf;
257 len >>= 1;
258
259 for (i = 0; i < len; i++)
260 writew(p[i], chip->IO_ADDR_W);
261
262 }
263
264 /**
265 * nand_read_buf16 - [DEFAULT] read chip data into buffer
266 * @mtd: MTD device structure
267 * @buf: buffer to store date
268 * @len: number of bytes to read
269 *
270 * Default read function for 16bit buswith
271 */
272 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
273 {
274 int i;
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
277 len >>= 1;
278
279 for (i = 0; i < len; i++)
280 p[i] = readw(chip->IO_ADDR_R);
281 }
282
283 /**
284 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
285 * @mtd: MTD device structure
286 * @buf: buffer containing the data to compare
287 * @len: number of bytes to compare
288 *
289 * Default verify function for 16bit buswith
290 */
291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
292 {
293 int i;
294 struct nand_chip *chip = mtd->priv;
295 u16 *p = (u16 *) buf;
296 len >>= 1;
297
298 for (i = 0; i < len; i++)
299 if (p[i] != readw(chip->IO_ADDR_R))
300 return -EFAULT;
301
302 return 0;
303 }
304
305 /**
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
309 * @getchip: 0, if the chip is already selected
310 *
311 * Check, if the block is bad.
312 */
313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
314 {
315 int page, chipnr, res = 0;
316 struct nand_chip *chip = mtd->priv;
317 u16 bad;
318
319 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
320
321 if (getchip) {
322 chipnr = (int)(ofs >> chip->chip_shift);
323
324 nand_get_device(chip, mtd, FL_READING);
325
326 /* Select the NAND device */
327 chip->select_chip(mtd, chipnr);
328 }
329
330 if (chip->options & NAND_BUSWIDTH_16) {
331 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
332 page);
333 bad = cpu_to_le16(chip->read_word(mtd));
334 if (chip->badblockpos & 0x1)
335 bad >>= 8;
336 if ((bad & 0xFF) != 0xff)
337 res = 1;
338 } else {
339 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
340 if (chip->read_byte(mtd) != 0xff)
341 res = 1;
342 }
343
344 if (getchip)
345 nand_release_device(mtd);
346
347 return res;
348 }
349
350 /**
351 * nand_default_block_markbad - [DEFAULT] mark a block bad
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
354 *
355 * This is the default implementation, which can be overridden by
356 * a hardware specific driver.
357 */
358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
359 {
360 struct nand_chip *chip = mtd->priv;
361 uint8_t buf[2] = { 0, 0 };
362 int block, ret;
363
364 /* Get block number */
365 block = (int)(ofs >> chip->bbt_erase_shift);
366 if (chip->bbt)
367 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
368
369 /* Do we have a flash based bad block table ? */
370 if (chip->options & NAND_USE_FLASH_BBT)
371 ret = nand_update_bbt(mtd, ofs);
372 else {
373 /* We write two bytes, so we dont have to mess with 16 bit
374 * access
375 */
376 nand_get_device(chip, mtd, FL_WRITING);
377 ofs += mtd->oobsize;
378 chip->ops.len = chip->ops.ooblen = 2;
379 chip->ops.datbuf = NULL;
380 chip->ops.oobbuf = buf;
381 chip->ops.ooboffs = chip->badblockpos & ~0x01;
382
383 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
384 nand_release_device(mtd);
385 }
386 if (!ret)
387 mtd->ecc_stats.badblocks++;
388
389 return ret;
390 }
391
392 /**
393 * nand_check_wp - [GENERIC] check if the chip is write protected
394 * @mtd: MTD device structure
395 * Check, if the device is write protected
396 *
397 * The function expects, that the device is already selected
398 */
399 static int nand_check_wp(struct mtd_info *mtd)
400 {
401 struct nand_chip *chip = mtd->priv;
402 /* Check the WP bit */
403 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
404 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
405 }
406
407 /**
408 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
409 * @mtd: MTD device structure
410 * @ofs: offset from device start
411 * @getchip: 0, if the chip is already selected
412 * @allowbbt: 1, if its allowed to access the bbt area
413 *
414 * Check, if the block is bad. Either by reading the bad block table or
415 * calling of the scan function.
416 */
417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
418 int allowbbt)
419 {
420 struct nand_chip *chip = mtd->priv;
421
422 if (!(chip->options & NAND_BBT_SCANNED)) {
423 chip->options |= NAND_BBT_SCANNED;
424 chip->scan_bbt(mtd);
425 }
426
427 if (!chip->bbt)
428 return chip->block_bad(mtd, ofs, getchip);
429
430 /* Return info from the table */
431 return nand_isbad_bbt(mtd, ofs, allowbbt);
432 }
433
434 /*
435 * Wait for the ready pin, after a command
436 * The timeout is catched later.
437 */
438 void nand_wait_ready(struct mtd_info *mtd)
439 {
440 struct nand_chip *chip = mtd->priv;
441 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
442 u32 time_start;
443
444 time_start = get_timer(0);
445
446 /* wait until command is processed or timeout occures */
447 while (get_timer(time_start) < timeo) {
448 if (chip->dev_ready)
449 if (chip->dev_ready(mtd))
450 break;
451 }
452 }
453
454 /**
455 * nand_command - [DEFAULT] Send command to NAND device
456 * @mtd: MTD device structure
457 * @command: the command to be sent
458 * @column: the column address for this command, -1 if none
459 * @page_addr: the page address for this command, -1 if none
460 *
461 * Send command to NAND device. This function is used for small page
462 * devices (256/512 Bytes per page)
463 */
464 static void nand_command(struct mtd_info *mtd, unsigned int command,
465 int column, int page_addr)
466 {
467 register struct nand_chip *chip = mtd->priv;
468 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
469 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
470
471 /*
472 * Write out the command to the device.
473 */
474 if (command == NAND_CMD_SEQIN) {
475 int readcmd;
476
477 if (column >= mtd->writesize) {
478 /* OOB area */
479 column -= mtd->writesize;
480 readcmd = NAND_CMD_READOOB;
481 } else if (column < 256) {
482 /* First 256 bytes --> READ0 */
483 readcmd = NAND_CMD_READ0;
484 } else {
485 column -= 256;
486 readcmd = NAND_CMD_READ1;
487 }
488 chip->cmd_ctrl(mtd, readcmd, ctrl);
489 ctrl &= ~NAND_CTRL_CHANGE;
490 }
491 chip->cmd_ctrl(mtd, command, ctrl);
492
493 /*
494 * Address cycle, when necessary
495 */
496 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
497 /* Serially input address */
498 if (column != -1) {
499 /* Adjust columns for 16 bit buswidth */
500 if (chip->options & NAND_BUSWIDTH_16)
501 column >>= 1;
502 chip->cmd_ctrl(mtd, column, ctrl);
503 ctrl &= ~NAND_CTRL_CHANGE;
504 }
505 if (page_addr != -1) {
506 chip->cmd_ctrl(mtd, page_addr, ctrl);
507 ctrl &= ~NAND_CTRL_CHANGE;
508 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
509 /* One more address cycle for devices > 32MiB */
510 if (chip->chipsize > (32 << 20))
511 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
512 }
513 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
514
515 /*
516 * program and erase have their own busy handlers
517 * status and sequential in needs no delay
518 */
519 switch (command) {
520
521 case NAND_CMD_PAGEPROG:
522 case NAND_CMD_ERASE1:
523 case NAND_CMD_ERASE2:
524 case NAND_CMD_SEQIN:
525 case NAND_CMD_STATUS:
526 return;
527
528 case NAND_CMD_RESET:
529 if (chip->dev_ready)
530 break;
531 udelay(chip->chip_delay);
532 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
533 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
534 chip->cmd_ctrl(mtd,
535 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
536 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
537 (rst_sts_cnt--));
538 return;
539
540 /* This applies to read commands */
541 default:
542 /*
543 * If we don't have access to the busy pin, we apply the given
544 * command delay
545 */
546 if (!chip->dev_ready) {
547 udelay(chip->chip_delay);
548 return;
549 }
550 }
551 /* Apply this short delay always to ensure that we do wait tWB in
552 * any case on any machine. */
553 ndelay(100);
554
555 nand_wait_ready(mtd);
556 }
557
558 /**
559 * nand_command_lp - [DEFAULT] Send command to NAND large page device
560 * @mtd: MTD device structure
561 * @command: the command to be sent
562 * @column: the column address for this command, -1 if none
563 * @page_addr: the page address for this command, -1 if none
564 *
565 * Send command to NAND device. This is the version for the new large page
566 * devices We dont have the separate regions as we have in the small page
567 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
568 */
569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
570 int column, int page_addr)
571 {
572 register struct nand_chip *chip = mtd->priv;
573 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
574
575 /* Emulate NAND_CMD_READOOB */
576 if (command == NAND_CMD_READOOB) {
577 column += mtd->writesize;
578 command = NAND_CMD_READ0;
579 }
580
581 /* Command latch cycle */
582 chip->cmd_ctrl(mtd, command & 0xff,
583 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
584
585 if (column != -1 || page_addr != -1) {
586 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
587
588 /* Serially input address */
589 if (column != -1) {
590 /* Adjust columns for 16 bit buswidth */
591 if (chip->options & NAND_BUSWIDTH_16)
592 column >>= 1;
593 chip->cmd_ctrl(mtd, column, ctrl);
594 ctrl &= ~NAND_CTRL_CHANGE;
595 chip->cmd_ctrl(mtd, column >> 8, ctrl);
596 }
597 if (page_addr != -1) {
598 chip->cmd_ctrl(mtd, page_addr, ctrl);
599 chip->cmd_ctrl(mtd, page_addr >> 8,
600 NAND_NCE | NAND_ALE);
601 /* One more address cycle for devices > 128MiB */
602 if (chip->chipsize > (128 << 20))
603 chip->cmd_ctrl(mtd, page_addr >> 16,
604 NAND_NCE | NAND_ALE);
605 }
606 }
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
608
609 /*
610 * program and erase have their own busy handlers
611 * status, sequential in, and deplete1 need no delay
612 */
613 switch (command) {
614
615 case NAND_CMD_CACHEDPROG:
616 case NAND_CMD_PAGEPROG:
617 case NAND_CMD_ERASE1:
618 case NAND_CMD_ERASE2:
619 case NAND_CMD_SEQIN:
620 case NAND_CMD_RNDIN:
621 case NAND_CMD_STATUS:
622 case NAND_CMD_DEPLETE1:
623 return;
624
625 /*
626 * read error status commands require only a short delay
627 */
628 case NAND_CMD_STATUS_ERROR:
629 case NAND_CMD_STATUS_ERROR0:
630 case NAND_CMD_STATUS_ERROR1:
631 case NAND_CMD_STATUS_ERROR2:
632 case NAND_CMD_STATUS_ERROR3:
633 udelay(chip->chip_delay);
634 return;
635
636 case NAND_CMD_RESET:
637 if (chip->dev_ready)
638 break;
639 udelay(chip->chip_delay);
640 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
641 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
642 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
643 NAND_NCE | NAND_CTRL_CHANGE);
644 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
645 (rst_sts_cnt--));
646 return;
647
648 case NAND_CMD_RNDOUT:
649 /* No ready / busy check necessary */
650 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
651 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653 NAND_NCE | NAND_CTRL_CHANGE);
654 return;
655
656 case NAND_CMD_READ0:
657 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
658 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
660 NAND_NCE | NAND_CTRL_CHANGE);
661
662 /* This applies to read commands */
663 default:
664 /*
665 * If we don't have access to the busy pin, we apply the given
666 * command delay
667 */
668 if (!chip->dev_ready) {
669 udelay(chip->chip_delay);
670 return;
671 }
672 }
673
674 /* Apply this short delay always to ensure that we do wait tWB in
675 * any case on any machine. */
676 ndelay(100);
677
678 nand_wait_ready(mtd);
679 }
680
681 /**
682 * nand_get_device - [GENERIC] Get chip for selected access
683 * @chip: the nand chip descriptor
684 * @mtd: MTD device structure
685 * @new_state: the state which is requested
686 *
687 * Get the device and lock it for exclusive access
688 */
689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
690 {
691 this->state = new_state;
692 return 0;
693 }
694
695 /**
696 * nand_wait - [DEFAULT] wait until the command is done
697 * @mtd: MTD device structure
698 * @chip: NAND chip structure
699 *
700 * Wait for command done. This applies to erase and program only
701 * Erase can take up to 400ms and program up to 20ms according to
702 * general NAND and SmartMedia specs
703 */
704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
705 {
706 unsigned long timeo;
707 int state = this->state;
708 u32 time_start;
709
710 if (state == FL_ERASING)
711 timeo = (CONFIG_SYS_HZ * 400) / 1000;
712 else
713 timeo = (CONFIG_SYS_HZ * 20) / 1000;
714
715 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
716 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
717 else
718 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
719
720 time_start = get_timer(0);
721
722 while (1) {
723 if (get_timer(time_start) > timeo) {
724 printf("Timeout!");
725 return 0x01;
726 }
727
728 if (this->dev_ready) {
729 if (this->dev_ready(mtd))
730 break;
731 } else {
732 if (this->read_byte(mtd) & NAND_STATUS_READY)
733 break;
734 }
735 }
736 #ifdef PPCHAMELON_NAND_TIMER_HACK
737 time_start = get_timer(0);
738 while (get_timer(time_start) < 10)
739 ;
740 #endif /* PPCHAMELON_NAND_TIMER_HACK */
741
742 return this->read_byte(mtd);
743 }
744
745 /**
746 * nand_read_page_raw - [Intern] read raw page data without ecc
747 * @mtd: mtd info structure
748 * @chip: nand chip info structure
749 * @buf: buffer to store read data
750 * @page: page number to read
751 *
752 * Not for syndrome calculating ecc controllers, which use a special oob layout
753 */
754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
755 uint8_t *buf, int page)
756 {
757 chip->read_buf(mtd, buf, mtd->writesize);
758 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
759 return 0;
760 }
761
762 /**
763 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
764 * @mtd: mtd info structure
765 * @chip: nand chip info structure
766 * @buf: buffer to store read data
767 * @page: page number to read
768 *
769 * We need a special oob layout and handling even when OOB isn't used.
770 */
771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
772 uint8_t *buf, int page)
773 {
774 int eccsize = chip->ecc.size;
775 int eccbytes = chip->ecc.bytes;
776 uint8_t *oob = chip->oob_poi;
777 int steps, size;
778
779 for (steps = chip->ecc.steps; steps > 0; steps--) {
780 chip->read_buf(mtd, buf, eccsize);
781 buf += eccsize;
782
783 if (chip->ecc.prepad) {
784 chip->read_buf(mtd, oob, chip->ecc.prepad);
785 oob += chip->ecc.prepad;
786 }
787
788 chip->read_buf(mtd, oob, eccbytes);
789 oob += eccbytes;
790
791 if (chip->ecc.postpad) {
792 chip->read_buf(mtd, oob, chip->ecc.postpad);
793 oob += chip->ecc.postpad;
794 }
795 }
796
797 size = mtd->oobsize - (oob - chip->oob_poi);
798 if (size)
799 chip->read_buf(mtd, oob, size);
800
801 return 0;
802 }
803
804 /**
805 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
806 * @mtd: mtd info structure
807 * @chip: nand chip info structure
808 * @buf: buffer to store read data
809 * @page: page number to read
810 */
811 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
812 uint8_t *buf, int page)
813 {
814 int i, eccsize = chip->ecc.size;
815 int eccbytes = chip->ecc.bytes;
816 int eccsteps = chip->ecc.steps;
817 uint8_t *p = buf;
818 uint8_t *ecc_calc = chip->buffers->ecccalc;
819 uint8_t *ecc_code = chip->buffers->ecccode;
820 uint32_t *eccpos = chip->ecc.layout->eccpos;
821
822 chip->ecc.read_page_raw(mtd, chip, buf, page);
823
824 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
825 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
826
827 for (i = 0; i < chip->ecc.total; i++)
828 ecc_code[i] = chip->oob_poi[eccpos[i]];
829
830 eccsteps = chip->ecc.steps;
831 p = buf;
832
833 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
834 int stat;
835
836 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
837 if (stat < 0)
838 mtd->ecc_stats.failed++;
839 else
840 mtd->ecc_stats.corrected += stat;
841 }
842 return 0;
843 }
844
845 /**
846 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
847 * @mtd: mtd info structure
848 * @chip: nand chip info structure
849 * @data_offs: offset of requested data within the page
850 * @readlen: data length
851 * @bufpoi: buffer to store read data
852 */
853 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
854 {
855 int start_step, end_step, num_steps;
856 uint32_t *eccpos = chip->ecc.layout->eccpos;
857 uint8_t *p;
858 int data_col_addr, i, gaps = 0;
859 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
860 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
861
862 /* Column address wihin the page aligned to ECC size (256bytes). */
863 start_step = data_offs / chip->ecc.size;
864 end_step = (data_offs + readlen - 1) / chip->ecc.size;
865 num_steps = end_step - start_step + 1;
866
867 /* Data size aligned to ECC ecc.size*/
868 datafrag_len = num_steps * chip->ecc.size;
869 eccfrag_len = num_steps * chip->ecc.bytes;
870
871 data_col_addr = start_step * chip->ecc.size;
872 /* If we read not a page aligned data */
873 if (data_col_addr != 0)
874 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
875
876 p = bufpoi + data_col_addr;
877 chip->read_buf(mtd, p, datafrag_len);
878
879 /* Calculate ECC */
880 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
881 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
882
883 /* The performance is faster if to position offsets
884 according to ecc.pos. Let make sure here that
885 there are no gaps in ecc positions */
886 for (i = 0; i < eccfrag_len - 1; i++) {
887 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
888 eccpos[i + start_step * chip->ecc.bytes + 1]) {
889 gaps = 1;
890 break;
891 }
892 }
893 if (gaps) {
894 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
895 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
896 } else {
897 /* send the command to read the particular ecc bytes */
898 /* take care about buswidth alignment in read_buf */
899 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
900 aligned_len = eccfrag_len;
901 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
902 aligned_len++;
903 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
904 aligned_len++;
905
906 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
907 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
908 }
909
910 for (i = 0; i < eccfrag_len; i++)
911 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
912
913 p = bufpoi + data_col_addr;
914 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
915 int stat;
916
917 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
918 if (stat == -1)
919 mtd->ecc_stats.failed++;
920 else
921 mtd->ecc_stats.corrected += stat;
922 }
923 return 0;
924 }
925
926 /**
927 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
928 * @mtd: mtd info structure
929 * @chip: nand chip info structure
930 * @buf: buffer to store read data
931 * @page: page number to read
932 *
933 * Not for syndrome calculating ecc controllers which need a special oob layout
934 */
935 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
936 uint8_t *buf, int page)
937 {
938 int i, eccsize = chip->ecc.size;
939 int eccbytes = chip->ecc.bytes;
940 int eccsteps = chip->ecc.steps;
941 uint8_t *p = buf;
942 uint8_t *ecc_calc = chip->buffers->ecccalc;
943 uint8_t *ecc_code = chip->buffers->ecccode;
944 uint32_t *eccpos = chip->ecc.layout->eccpos;
945
946 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
947 chip->ecc.hwctl(mtd, NAND_ECC_READ);
948 chip->read_buf(mtd, p, eccsize);
949 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
950 }
951 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
952
953 for (i = 0; i < chip->ecc.total; i++)
954 ecc_code[i] = chip->oob_poi[eccpos[i]];
955
956 eccsteps = chip->ecc.steps;
957 p = buf;
958
959 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
960 int stat;
961
962 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
963 if (stat < 0)
964 mtd->ecc_stats.failed++;
965 else
966 mtd->ecc_stats.corrected += stat;
967 }
968 return 0;
969 }
970
971 /**
972 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
973 * @mtd: mtd info structure
974 * @chip: nand chip info structure
975 * @buf: buffer to store read data
976 * @page: page number to read
977 *
978 * Hardware ECC for large page chips, require OOB to be read first.
979 * For this ECC mode, the write_page method is re-used from ECC_HW.
980 * These methods read/write ECC from the OOB area, unlike the
981 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
982 * "infix ECC" scheme and reads/writes ECC from the data area, by
983 * overwriting the NAND manufacturer bad block markings.
984 */
985 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
986 struct nand_chip *chip, uint8_t *buf, int page)
987 {
988 int i, eccsize = chip->ecc.size;
989 int eccbytes = chip->ecc.bytes;
990 int eccsteps = chip->ecc.steps;
991 uint8_t *p = buf;
992 uint8_t *ecc_code = chip->buffers->ecccode;
993 uint32_t *eccpos = chip->ecc.layout->eccpos;
994 uint8_t *ecc_calc = chip->buffers->ecccalc;
995
996 /* Read the OOB area first */
997 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
998 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
999 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1000
1001 for (i = 0; i < chip->ecc.total; i++)
1002 ecc_code[i] = chip->oob_poi[eccpos[i]];
1003
1004 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1005 int stat;
1006
1007 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1008 chip->read_buf(mtd, p, eccsize);
1009 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1010
1011 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1012 if (stat < 0)
1013 mtd->ecc_stats.failed++;
1014 else
1015 mtd->ecc_stats.corrected += stat;
1016 }
1017 return 0;
1018 }
1019
1020 /**
1021 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1025 * @page: page number to read
1026 *
1027 * The hw generator calculates the error syndrome automatically. Therefor
1028 * we need a special oob layout and handling.
1029 */
1030 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1031 uint8_t *buf, int page)
1032 {
1033 int i, eccsize = chip->ecc.size;
1034 int eccbytes = chip->ecc.bytes;
1035 int eccsteps = chip->ecc.steps;
1036 uint8_t *p = buf;
1037 uint8_t *oob = chip->oob_poi;
1038
1039 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1040 int stat;
1041
1042 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043 chip->read_buf(mtd, p, eccsize);
1044
1045 if (chip->ecc.prepad) {
1046 chip->read_buf(mtd, oob, chip->ecc.prepad);
1047 oob += chip->ecc.prepad;
1048 }
1049
1050 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1051 chip->read_buf(mtd, oob, eccbytes);
1052 stat = chip->ecc.correct(mtd, p, oob, NULL);
1053
1054 if (stat < 0)
1055 mtd->ecc_stats.failed++;
1056 else
1057 mtd->ecc_stats.corrected += stat;
1058
1059 oob += eccbytes;
1060
1061 if (chip->ecc.postpad) {
1062 chip->read_buf(mtd, oob, chip->ecc.postpad);
1063 oob += chip->ecc.postpad;
1064 }
1065 }
1066
1067 /* Calculate remaining oob bytes */
1068 i = mtd->oobsize - (oob - chip->oob_poi);
1069 if (i)
1070 chip->read_buf(mtd, oob, i);
1071
1072 return 0;
1073 }
1074
1075 /**
1076 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1077 * @chip: nand chip structure
1078 * @oob: oob destination address
1079 * @ops: oob ops structure
1080 * @len: size of oob to transfer
1081 */
1082 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1083 struct mtd_oob_ops *ops, size_t len)
1084 {
1085 switch(ops->mode) {
1086
1087 case MTD_OOB_PLACE:
1088 case MTD_OOB_RAW:
1089 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1090 return oob + len;
1091
1092 case MTD_OOB_AUTO: {
1093 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1094 uint32_t boffs = 0, roffs = ops->ooboffs;
1095 size_t bytes = 0;
1096
1097 for(; free->length && len; free++, len -= bytes) {
1098 /* Read request not from offset 0 ? */
1099 if (unlikely(roffs)) {
1100 if (roffs >= free->length) {
1101 roffs -= free->length;
1102 continue;
1103 }
1104 boffs = free->offset + roffs;
1105 bytes = min_t(size_t, len,
1106 (free->length - roffs));
1107 roffs = 0;
1108 } else {
1109 bytes = min_t(size_t, len, free->length);
1110 boffs = free->offset;
1111 }
1112 memcpy(oob, chip->oob_poi + boffs, bytes);
1113 oob += bytes;
1114 }
1115 return oob;
1116 }
1117 default:
1118 BUG();
1119 }
1120 return NULL;
1121 }
1122
1123 /**
1124 * nand_do_read_ops - [Internal] Read data with ECC
1125 *
1126 * @mtd: MTD device structure
1127 * @from: offset to read from
1128 * @ops: oob ops structure
1129 *
1130 * Internal function. Called with chip held.
1131 */
1132 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1133 struct mtd_oob_ops *ops)
1134 {
1135 int chipnr, page, realpage, col, bytes, aligned;
1136 struct nand_chip *chip = mtd->priv;
1137 struct mtd_ecc_stats stats;
1138 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1139 int sndcmd = 1;
1140 int ret = 0;
1141 uint32_t readlen = ops->len;
1142 uint32_t oobreadlen = ops->ooblen;
1143 uint8_t *bufpoi, *oob, *buf;
1144
1145 stats = mtd->ecc_stats;
1146
1147 chipnr = (int)(from >> chip->chip_shift);
1148 chip->select_chip(mtd, chipnr);
1149
1150 realpage = (int)(from >> chip->page_shift);
1151 page = realpage & chip->pagemask;
1152
1153 col = (int)(from & (mtd->writesize - 1));
1154
1155 buf = ops->datbuf;
1156 oob = ops->oobbuf;
1157
1158 while(1) {
1159 WATCHDOG_RESET();
1160
1161 bytes = min(mtd->writesize - col, readlen);
1162 aligned = (bytes == mtd->writesize);
1163
1164 /* Is the current page in the buffer ? */
1165 if (realpage != chip->pagebuf || oob) {
1166 bufpoi = aligned ? buf : chip->buffers->databuf;
1167
1168 if (likely(sndcmd)) {
1169 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1170 sndcmd = 0;
1171 }
1172
1173 /* Now read the page into the buffer */
1174 if (unlikely(ops->mode == MTD_OOB_RAW))
1175 ret = chip->ecc.read_page_raw(mtd, chip,
1176 bufpoi, page);
1177 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1178 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1179 else
1180 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1181 page);
1182 if (ret < 0)
1183 break;
1184
1185 /* Transfer not aligned data */
1186 if (!aligned) {
1187 if (!NAND_SUBPAGE_READ(chip) && !oob)
1188 chip->pagebuf = realpage;
1189 memcpy(buf, chip->buffers->databuf + col, bytes);
1190 }
1191
1192 buf += bytes;
1193
1194 if (unlikely(oob)) {
1195 /* Raw mode does data:oob:data:oob */
1196 if (ops->mode != MTD_OOB_RAW) {
1197 int toread = min(oobreadlen,
1198 chip->ecc.layout->oobavail);
1199 if (toread) {
1200 oob = nand_transfer_oob(chip,
1201 oob, ops, toread);
1202 oobreadlen -= toread;
1203 }
1204 } else
1205 buf = nand_transfer_oob(chip,
1206 buf, ops, mtd->oobsize);
1207 }
1208
1209 if (!(chip->options & NAND_NO_READRDY)) {
1210 /*
1211 * Apply delay or wait for ready/busy pin. Do
1212 * this before the AUTOINCR check, so no
1213 * problems arise if a chip which does auto
1214 * increment is marked as NOAUTOINCR by the
1215 * board driver.
1216 */
1217 if (!chip->dev_ready)
1218 udelay(chip->chip_delay);
1219 else
1220 nand_wait_ready(mtd);
1221 }
1222 } else {
1223 memcpy(buf, chip->buffers->databuf + col, bytes);
1224 buf += bytes;
1225 }
1226
1227 readlen -= bytes;
1228
1229 if (!readlen)
1230 break;
1231
1232 /* For subsequent reads align to page boundary. */
1233 col = 0;
1234 /* Increment page address */
1235 realpage++;
1236
1237 page = realpage & chip->pagemask;
1238 /* Check, if we cross a chip boundary */
1239 if (!page) {
1240 chipnr++;
1241 chip->select_chip(mtd, -1);
1242 chip->select_chip(mtd, chipnr);
1243 }
1244
1245 /* Check, if the chip supports auto page increment
1246 * or if we have hit a block boundary.
1247 */
1248 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1249 sndcmd = 1;
1250 }
1251
1252 ops->retlen = ops->len - (size_t) readlen;
1253 if (oob)
1254 ops->oobretlen = ops->ooblen - oobreadlen;
1255
1256 if (ret)
1257 return ret;
1258
1259 if (mtd->ecc_stats.failed - stats.failed)
1260 return -EBADMSG;
1261
1262 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1263 }
1264
1265 /**
1266 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1267 * @mtd: MTD device structure
1268 * @from: offset to read from
1269 * @len: number of bytes to read
1270 * @retlen: pointer to variable to store the number of read bytes
1271 * @buf: the databuffer to put data
1272 *
1273 * Get hold of the chip and call nand_do_read
1274 */
1275 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1276 size_t *retlen, uint8_t *buf)
1277 {
1278 struct nand_chip *chip = mtd->priv;
1279 int ret;
1280
1281 /* Do not allow reads past end of device */
1282 if ((from + len) > mtd->size)
1283 return -EINVAL;
1284 if (!len)
1285 return 0;
1286
1287 nand_get_device(chip, mtd, FL_READING);
1288
1289 chip->ops.len = len;
1290 chip->ops.datbuf = buf;
1291 chip->ops.oobbuf = NULL;
1292
1293 ret = nand_do_read_ops(mtd, from, &chip->ops);
1294
1295 *retlen = chip->ops.retlen;
1296
1297 nand_release_device(mtd);
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1304 * @mtd: mtd info structure
1305 * @chip: nand chip info structure
1306 * @page: page number to read
1307 * @sndcmd: flag whether to issue read command or not
1308 */
1309 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1310 int page, int sndcmd)
1311 {
1312 if (sndcmd) {
1313 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1314 sndcmd = 0;
1315 }
1316 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1317 return sndcmd;
1318 }
1319
1320 /**
1321 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1322 * with syndromes
1323 * @mtd: mtd info structure
1324 * @chip: nand chip info structure
1325 * @page: page number to read
1326 * @sndcmd: flag whether to issue read command or not
1327 */
1328 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1329 int page, int sndcmd)
1330 {
1331 uint8_t *buf = chip->oob_poi;
1332 int length = mtd->oobsize;
1333 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1334 int eccsize = chip->ecc.size;
1335 uint8_t *bufpoi = buf;
1336 int i, toread, sndrnd = 0, pos;
1337
1338 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1339 for (i = 0; i < chip->ecc.steps; i++) {
1340 if (sndrnd) {
1341 pos = eccsize + i * (eccsize + chunk);
1342 if (mtd->writesize > 512)
1343 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1344 else
1345 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1346 } else
1347 sndrnd = 1;
1348 toread = min_t(int, length, chunk);
1349 chip->read_buf(mtd, bufpoi, toread);
1350 bufpoi += toread;
1351 length -= toread;
1352 }
1353 if (length > 0)
1354 chip->read_buf(mtd, bufpoi, length);
1355
1356 return 1;
1357 }
1358
1359 /**
1360 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1361 * @mtd: mtd info structure
1362 * @chip: nand chip info structure
1363 * @page: page number to write
1364 */
1365 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1366 int page)
1367 {
1368 int status = 0;
1369 const uint8_t *buf = chip->oob_poi;
1370 int length = mtd->oobsize;
1371
1372 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1373 chip->write_buf(mtd, buf, length);
1374 /* Send command to program the OOB data */
1375 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1376
1377 status = chip->waitfunc(mtd, chip);
1378
1379 return status & NAND_STATUS_FAIL ? -EIO : 0;
1380 }
1381
1382 /**
1383 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1384 * with syndrome - only for large page flash !
1385 * @mtd: mtd info structure
1386 * @chip: nand chip info structure
1387 * @page: page number to write
1388 */
1389 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1390 struct nand_chip *chip, int page)
1391 {
1392 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1393 int eccsize = chip->ecc.size, length = mtd->oobsize;
1394 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1395 const uint8_t *bufpoi = chip->oob_poi;
1396
1397 /*
1398 * data-ecc-data-ecc ... ecc-oob
1399 * or
1400 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1401 */
1402 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1403 pos = steps * (eccsize + chunk);
1404 steps = 0;
1405 } else
1406 pos = eccsize;
1407
1408 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1409 for (i = 0; i < steps; i++) {
1410 if (sndcmd) {
1411 if (mtd->writesize <= 512) {
1412 uint32_t fill = 0xFFFFFFFF;
1413
1414 len = eccsize;
1415 while (len > 0) {
1416 int num = min_t(int, len, 4);
1417 chip->write_buf(mtd, (uint8_t *)&fill,
1418 num);
1419 len -= num;
1420 }
1421 } else {
1422 pos = eccsize + i * (eccsize + chunk);
1423 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1424 }
1425 } else
1426 sndcmd = 1;
1427 len = min_t(int, length, chunk);
1428 chip->write_buf(mtd, bufpoi, len);
1429 bufpoi += len;
1430 length -= len;
1431 }
1432 if (length > 0)
1433 chip->write_buf(mtd, bufpoi, length);
1434
1435 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1436 status = chip->waitfunc(mtd, chip);
1437
1438 return status & NAND_STATUS_FAIL ? -EIO : 0;
1439 }
1440
1441 /**
1442 * nand_do_read_oob - [Intern] NAND read out-of-band
1443 * @mtd: MTD device structure
1444 * @from: offset to read from
1445 * @ops: oob operations description structure
1446 *
1447 * NAND read out-of-band data from the spare area
1448 */
1449 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1450 struct mtd_oob_ops *ops)
1451 {
1452 int page, realpage, chipnr, sndcmd = 1;
1453 struct nand_chip *chip = mtd->priv;
1454 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1455 int readlen = ops->ooblen;
1456 int len;
1457 uint8_t *buf = ops->oobbuf;
1458
1459 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1460 (unsigned long long)from, readlen);
1461
1462 if (ops->mode == MTD_OOB_AUTO)
1463 len = chip->ecc.layout->oobavail;
1464 else
1465 len = mtd->oobsize;
1466
1467 if (unlikely(ops->ooboffs >= len)) {
1468 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1469 "Attempt to start read outside oob\n");
1470 return -EINVAL;
1471 }
1472
1473 /* Do not allow reads past end of device */
1474 if (unlikely(from >= mtd->size ||
1475 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1476 (from >> chip->page_shift)) * len)) {
1477 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1478 "Attempt read beyond end of device\n");
1479 return -EINVAL;
1480 }
1481
1482 chipnr = (int)(from >> chip->chip_shift);
1483 chip->select_chip(mtd, chipnr);
1484
1485 /* Shift to get page */
1486 realpage = (int)(from >> chip->page_shift);
1487 page = realpage & chip->pagemask;
1488
1489 while(1) {
1490 WATCHDOG_RESET();
1491 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1492
1493 len = min(len, readlen);
1494 buf = nand_transfer_oob(chip, buf, ops, len);
1495
1496 if (!(chip->options & NAND_NO_READRDY)) {
1497 /*
1498 * Apply delay or wait for ready/busy pin. Do this
1499 * before the AUTOINCR check, so no problems arise if a
1500 * chip which does auto increment is marked as
1501 * NOAUTOINCR by the board driver.
1502 */
1503 if (!chip->dev_ready)
1504 udelay(chip->chip_delay);
1505 else
1506 nand_wait_ready(mtd);
1507 }
1508
1509 readlen -= len;
1510 if (!readlen)
1511 break;
1512
1513 /* Increment page address */
1514 realpage++;
1515
1516 page = realpage & chip->pagemask;
1517 /* Check, if we cross a chip boundary */
1518 if (!page) {
1519 chipnr++;
1520 chip->select_chip(mtd, -1);
1521 chip->select_chip(mtd, chipnr);
1522 }
1523
1524 /* Check, if the chip supports auto page increment
1525 * or if we have hit a block boundary.
1526 */
1527 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1528 sndcmd = 1;
1529 }
1530
1531 ops->oobretlen = ops->ooblen;
1532 return 0;
1533 }
1534
1535 /**
1536 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1537 * @mtd: MTD device structure
1538 * @from: offset to read from
1539 * @ops: oob operation description structure
1540 *
1541 * NAND read data and/or out-of-band data
1542 */
1543 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1544 struct mtd_oob_ops *ops)
1545 {
1546 struct nand_chip *chip = mtd->priv;
1547 int ret = -ENOTSUPP;
1548
1549 ops->retlen = 0;
1550
1551 /* Do not allow reads past end of device */
1552 if (ops->datbuf && (from + ops->len) > mtd->size) {
1553 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1554 "Attempt read beyond end of device\n");
1555 return -EINVAL;
1556 }
1557
1558 nand_get_device(chip, mtd, FL_READING);
1559
1560 switch(ops->mode) {
1561 case MTD_OOB_PLACE:
1562 case MTD_OOB_AUTO:
1563 case MTD_OOB_RAW:
1564 break;
1565
1566 default:
1567 goto out;
1568 }
1569
1570 if (!ops->datbuf)
1571 ret = nand_do_read_oob(mtd, from, ops);
1572 else
1573 ret = nand_do_read_ops(mtd, from, ops);
1574
1575 out:
1576 nand_release_device(mtd);
1577 return ret;
1578 }
1579
1580
1581 /**
1582 * nand_write_page_raw - [Intern] raw page write function
1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1585 * @buf: data buffer
1586 *
1587 * Not for syndrome calculating ecc controllers, which use a special oob layout
1588 */
1589 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1590 const uint8_t *buf)
1591 {
1592 chip->write_buf(mtd, buf, mtd->writesize);
1593 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1594 }
1595
1596 /**
1597 * nand_write_page_raw_syndrome - [Intern] raw page write function
1598 * @mtd: mtd info structure
1599 * @chip: nand chip info structure
1600 * @buf: data buffer
1601 *
1602 * We need a special oob layout and handling even when ECC isn't checked.
1603 */
1604 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1605 const uint8_t *buf)
1606 {
1607 int eccsize = chip->ecc.size;
1608 int eccbytes = chip->ecc.bytes;
1609 uint8_t *oob = chip->oob_poi;
1610 int steps, size;
1611
1612 for (steps = chip->ecc.steps; steps > 0; steps--) {
1613 chip->write_buf(mtd, buf, eccsize);
1614 buf += eccsize;
1615
1616 if (chip->ecc.prepad) {
1617 chip->write_buf(mtd, oob, chip->ecc.prepad);
1618 oob += chip->ecc.prepad;
1619 }
1620
1621 chip->read_buf(mtd, oob, eccbytes);
1622 oob += eccbytes;
1623
1624 if (chip->ecc.postpad) {
1625 chip->write_buf(mtd, oob, chip->ecc.postpad);
1626 oob += chip->ecc.postpad;
1627 }
1628 }
1629
1630 size = mtd->oobsize - (oob - chip->oob_poi);
1631 if (size)
1632 chip->write_buf(mtd, oob, size);
1633 }
1634 /**
1635 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1636 * @mtd: mtd info structure
1637 * @chip: nand chip info structure
1638 * @buf: data buffer
1639 */
1640 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1641 const uint8_t *buf)
1642 {
1643 int i, eccsize = chip->ecc.size;
1644 int eccbytes = chip->ecc.bytes;
1645 int eccsteps = chip->ecc.steps;
1646 uint8_t *ecc_calc = chip->buffers->ecccalc;
1647 const uint8_t *p = buf;
1648 uint32_t *eccpos = chip->ecc.layout->eccpos;
1649
1650 /* Software ecc calculation */
1651 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1652 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1653
1654 for (i = 0; i < chip->ecc.total; i++)
1655 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1656
1657 chip->ecc.write_page_raw(mtd, chip, buf);
1658 }
1659
1660 /**
1661 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1662 * @mtd: mtd info structure
1663 * @chip: nand chip info structure
1664 * @buf: data buffer
1665 */
1666 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1667 const uint8_t *buf)
1668 {
1669 int i, eccsize = chip->ecc.size;
1670 int eccbytes = chip->ecc.bytes;
1671 int eccsteps = chip->ecc.steps;
1672 uint8_t *ecc_calc = chip->buffers->ecccalc;
1673 const uint8_t *p = buf;
1674 uint32_t *eccpos = chip->ecc.layout->eccpos;
1675
1676 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1677 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1678 chip->write_buf(mtd, p, eccsize);
1679 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1680 }
1681
1682 for (i = 0; i < chip->ecc.total; i++)
1683 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1684
1685 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1686 }
1687
1688 /**
1689 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1690 * @mtd: mtd info structure
1691 * @chip: nand chip info structure
1692 * @buf: data buffer
1693 *
1694 * The hw generator calculates the error syndrome automatically. Therefor
1695 * we need a special oob layout and handling.
1696 */
1697 static void nand_write_page_syndrome(struct mtd_info *mtd,
1698 struct nand_chip *chip, const uint8_t *buf)
1699 {
1700 int i, eccsize = chip->ecc.size;
1701 int eccbytes = chip->ecc.bytes;
1702 int eccsteps = chip->ecc.steps;
1703 const uint8_t *p = buf;
1704 uint8_t *oob = chip->oob_poi;
1705
1706 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1707
1708 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1709 chip->write_buf(mtd, p, eccsize);
1710
1711 if (chip->ecc.prepad) {
1712 chip->write_buf(mtd, oob, chip->ecc.prepad);
1713 oob += chip->ecc.prepad;
1714 }
1715
1716 chip->ecc.calculate(mtd, p, oob);
1717 chip->write_buf(mtd, oob, eccbytes);
1718 oob += eccbytes;
1719
1720 if (chip->ecc.postpad) {
1721 chip->write_buf(mtd, oob, chip->ecc.postpad);
1722 oob += chip->ecc.postpad;
1723 }
1724 }
1725
1726 /* Calculate remaining oob bytes */
1727 i = mtd->oobsize - (oob - chip->oob_poi);
1728 if (i)
1729 chip->write_buf(mtd, oob, i);
1730 }
1731
1732 /**
1733 * nand_write_page - [REPLACEABLE] write one page
1734 * @mtd: MTD device structure
1735 * @chip: NAND chip descriptor
1736 * @buf: the data to write
1737 * @page: page number to write
1738 * @cached: cached programming
1739 * @raw: use _raw version of write_page
1740 */
1741 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1742 const uint8_t *buf, int page, int cached, int raw)
1743 {
1744 int status;
1745
1746 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1747
1748 if (unlikely(raw))
1749 chip->ecc.write_page_raw(mtd, chip, buf);
1750 else
1751 chip->ecc.write_page(mtd, chip, buf);
1752
1753 /*
1754 * Cached progamming disabled for now, Not sure if its worth the
1755 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1756 */
1757 cached = 0;
1758
1759 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1760
1761 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762 status = chip->waitfunc(mtd, chip);
1763 /*
1764 * See if operation failed and additional status checks are
1765 * available
1766 */
1767 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1768 status = chip->errstat(mtd, chip, FL_WRITING, status,
1769 page);
1770
1771 if (status & NAND_STATUS_FAIL)
1772 return -EIO;
1773 } else {
1774 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1775 status = chip->waitfunc(mtd, chip);
1776 }
1777
1778 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1779 /* Send command to read back the data */
1780 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1781
1782 if (chip->verify_buf(mtd, buf, mtd->writesize))
1783 return -EIO;
1784 #endif
1785 return 0;
1786 }
1787
1788 /**
1789 * nand_fill_oob - [Internal] Transfer client buffer to oob
1790 * @chip: nand chip structure
1791 * @oob: oob data buffer
1792 * @ops: oob ops structure
1793 */
1794 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1795 struct mtd_oob_ops *ops)
1796 {
1797 size_t len = ops->ooblen;
1798
1799 switch(ops->mode) {
1800
1801 case MTD_OOB_PLACE:
1802 case MTD_OOB_RAW:
1803 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1804 return oob + len;
1805
1806 case MTD_OOB_AUTO: {
1807 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1808 uint32_t boffs = 0, woffs = ops->ooboffs;
1809 size_t bytes = 0;
1810
1811 for(; free->length && len; free++, len -= bytes) {
1812 /* Write request not from offset 0 ? */
1813 if (unlikely(woffs)) {
1814 if (woffs >= free->length) {
1815 woffs -= free->length;
1816 continue;
1817 }
1818 boffs = free->offset + woffs;
1819 bytes = min_t(size_t, len,
1820 (free->length - woffs));
1821 woffs = 0;
1822 } else {
1823 bytes = min_t(size_t, len, free->length);
1824 boffs = free->offset;
1825 }
1826 memcpy(chip->oob_poi + boffs, oob, bytes);
1827 oob += bytes;
1828 }
1829 return oob;
1830 }
1831 default:
1832 BUG();
1833 }
1834 return NULL;
1835 }
1836
1837 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1838
1839 /**
1840 * nand_do_write_ops - [Internal] NAND write with ECC
1841 * @mtd: MTD device structure
1842 * @to: offset to write to
1843 * @ops: oob operations description structure
1844 *
1845 * NAND write with ECC
1846 */
1847 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1848 struct mtd_oob_ops *ops)
1849 {
1850 int chipnr, realpage, page, blockmask, column;
1851 struct nand_chip *chip = mtd->priv;
1852 uint32_t writelen = ops->len;
1853 uint8_t *oob = ops->oobbuf;
1854 uint8_t *buf = ops->datbuf;
1855 int ret, subpage;
1856
1857 ops->retlen = 0;
1858 if (!writelen)
1859 return 0;
1860
1861 column = to & (mtd->writesize - 1);
1862 subpage = column || (writelen & (mtd->writesize - 1));
1863
1864 if (subpage && oob)
1865 return -EINVAL;
1866
1867 chipnr = (int)(to >> chip->chip_shift);
1868 chip->select_chip(mtd, chipnr);
1869
1870 /* Check, if it is write protected */
1871 if (nand_check_wp(mtd)) {
1872 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1873 return -EIO;
1874 }
1875
1876 realpage = (int)(to >> chip->page_shift);
1877 page = realpage & chip->pagemask;
1878 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1879
1880 /* Invalidate the page cache, when we write to the cached page */
1881 if (to <= (chip->pagebuf << chip->page_shift) &&
1882 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1883 chip->pagebuf = -1;
1884
1885 /* If we're not given explicit OOB data, let it be 0xFF */
1886 if (likely(!oob))
1887 memset(chip->oob_poi, 0xff, mtd->oobsize);
1888
1889 while(1) {
1890 WATCHDOG_RESET();
1891
1892 int bytes = mtd->writesize;
1893 int cached = writelen > bytes && page != blockmask;
1894 uint8_t *wbuf = buf;
1895
1896 /* Partial page write ? */
1897 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1898 cached = 0;
1899 bytes = min_t(int, bytes - column, (int) writelen);
1900 chip->pagebuf = -1;
1901 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1902 memcpy(&chip->buffers->databuf[column], buf, bytes);
1903 wbuf = chip->buffers->databuf;
1904 }
1905
1906 if (unlikely(oob))
1907 oob = nand_fill_oob(chip, oob, ops);
1908
1909 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1910 (ops->mode == MTD_OOB_RAW));
1911 if (ret)
1912 break;
1913
1914 writelen -= bytes;
1915 if (!writelen)
1916 break;
1917
1918 column = 0;
1919 buf += bytes;
1920 realpage++;
1921
1922 page = realpage & chip->pagemask;
1923 /* Check, if we cross a chip boundary */
1924 if (!page) {
1925 chipnr++;
1926 chip->select_chip(mtd, -1);
1927 chip->select_chip(mtd, chipnr);
1928 }
1929 }
1930
1931 ops->retlen = ops->len - writelen;
1932 if (unlikely(oob))
1933 ops->oobretlen = ops->ooblen;
1934 return ret;
1935 }
1936
1937 /**
1938 * nand_write - [MTD Interface] NAND write with ECC
1939 * @mtd: MTD device structure
1940 * @to: offset to write to
1941 * @len: number of bytes to write
1942 * @retlen: pointer to variable to store the number of written bytes
1943 * @buf: the data to write
1944 *
1945 * NAND write with ECC
1946 */
1947 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1948 size_t *retlen, const uint8_t *buf)
1949 {
1950 struct nand_chip *chip = mtd->priv;
1951 int ret;
1952
1953 /* Do not allow reads past end of device */
1954 if ((to + len) > mtd->size)
1955 return -EINVAL;
1956 if (!len)
1957 return 0;
1958
1959 nand_get_device(chip, mtd, FL_WRITING);
1960
1961 chip->ops.len = len;
1962 chip->ops.datbuf = (uint8_t *)buf;
1963 chip->ops.oobbuf = NULL;
1964
1965 ret = nand_do_write_ops(mtd, to, &chip->ops);
1966
1967 *retlen = chip->ops.retlen;
1968
1969 nand_release_device(mtd);
1970
1971 return ret;
1972 }
1973
1974 /**
1975 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1976 * @mtd: MTD device structure
1977 * @to: offset to write to
1978 * @ops: oob operation description structure
1979 *
1980 * NAND write out-of-band
1981 */
1982 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1983 struct mtd_oob_ops *ops)
1984 {
1985 int chipnr, page, status, len;
1986 struct nand_chip *chip = mtd->priv;
1987
1988 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1989 (unsigned int)to, (int)ops->ooblen);
1990
1991 if (ops->mode == MTD_OOB_AUTO)
1992 len = chip->ecc.layout->oobavail;
1993 else
1994 len = mtd->oobsize;
1995
1996 /* Do not allow write past end of page */
1997 if ((ops->ooboffs + ops->ooblen) > len) {
1998 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1999 "Attempt to write past end of page\n");
2000 return -EINVAL;
2001 }
2002
2003 if (unlikely(ops->ooboffs >= len)) {
2004 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2005 "Attempt to start write outside oob\n");
2006 return -EINVAL;
2007 }
2008
2009 /* Do not allow reads past end of device */
2010 if (unlikely(to >= mtd->size ||
2011 ops->ooboffs + ops->ooblen >
2012 ((mtd->size >> chip->page_shift) -
2013 (to >> chip->page_shift)) * len)) {
2014 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2015 "Attempt write beyond end of device\n");
2016 return -EINVAL;
2017 }
2018
2019 chipnr = (int)(to >> chip->chip_shift);
2020 chip->select_chip(mtd, chipnr);
2021
2022 /* Shift to get page */
2023 page = (int)(to >> chip->page_shift);
2024
2025 /*
2026 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2027 * of my DiskOnChip 2000 test units) will clear the whole data page too
2028 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2029 * it in the doc2000 driver in August 1999. dwmw2.
2030 */
2031 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2032
2033 /* Check, if it is write protected */
2034 if (nand_check_wp(mtd))
2035 return -EROFS;
2036
2037 /* Invalidate the page cache, if we write to the cached page */
2038 if (page == chip->pagebuf)
2039 chip->pagebuf = -1;
2040
2041 memset(chip->oob_poi, 0xff, mtd->oobsize);
2042 nand_fill_oob(chip, ops->oobbuf, ops);
2043 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2044 memset(chip->oob_poi, 0xff, mtd->oobsize);
2045
2046 if (status)
2047 return status;
2048
2049 ops->oobretlen = ops->ooblen;
2050
2051 return 0;
2052 }
2053
2054 /**
2055 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2056 * @mtd: MTD device structure
2057 * @to: offset to write to
2058 * @ops: oob operation description structure
2059 */
2060 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2061 struct mtd_oob_ops *ops)
2062 {
2063 struct nand_chip *chip = mtd->priv;
2064 int ret = -ENOTSUPP;
2065
2066 ops->retlen = 0;
2067
2068 /* Do not allow writes past end of device */
2069 if (ops->datbuf && (to + ops->len) > mtd->size) {
2070 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2071 "Attempt read beyond end of device\n");
2072 return -EINVAL;
2073 }
2074
2075 nand_get_device(chip, mtd, FL_WRITING);
2076
2077 switch(ops->mode) {
2078 case MTD_OOB_PLACE:
2079 case MTD_OOB_AUTO:
2080 case MTD_OOB_RAW:
2081 break;
2082
2083 default:
2084 goto out;
2085 }
2086
2087 if (!ops->datbuf)
2088 ret = nand_do_write_oob(mtd, to, ops);
2089 else
2090 ret = nand_do_write_ops(mtd, to, ops);
2091
2092 out:
2093 nand_release_device(mtd);
2094 return ret;
2095 }
2096
2097 /**
2098 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2099 * @mtd: MTD device structure
2100 * @page: the page address of the block which will be erased
2101 *
2102 * Standard erase command for NAND chips
2103 */
2104 static void single_erase_cmd(struct mtd_info *mtd, int page)
2105 {
2106 struct nand_chip *chip = mtd->priv;
2107 /* Send commands to erase a block */
2108 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2109 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2110 }
2111
2112 /**
2113 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2114 * @mtd: MTD device structure
2115 * @page: the page address of the block which will be erased
2116 *
2117 * AND multi block erase command function
2118 * Erase 4 consecutive blocks
2119 */
2120 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2121 {
2122 struct nand_chip *chip = mtd->priv;
2123 /* Send commands to erase a block */
2124 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2125 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2126 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2127 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2128 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2129 }
2130
2131 /**
2132 * nand_erase - [MTD Interface] erase block(s)
2133 * @mtd: MTD device structure
2134 * @instr: erase instruction
2135 *
2136 * Erase one ore more blocks
2137 */
2138 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2139 {
2140 return nand_erase_nand(mtd, instr, 0);
2141 }
2142
2143 #define BBT_PAGE_MASK 0xffffff3f
2144 /**
2145 * nand_erase_nand - [Internal] erase block(s)
2146 * @mtd: MTD device structure
2147 * @instr: erase instruction
2148 * @allowbbt: allow erasing the bbt area
2149 *
2150 * Erase one ore more blocks
2151 */
2152 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2153 int allowbbt)
2154 {
2155 int page, status, pages_per_block, ret, chipnr;
2156 struct nand_chip *chip = mtd->priv;
2157 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2158 unsigned int bbt_masked_page = 0xffffffff;
2159 loff_t len;
2160
2161 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2162 "len = %llu\n", (unsigned long long) instr->addr,
2163 (unsigned long long) instr->len);
2164
2165 /* Start address must align on block boundary */
2166 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2167 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2168 return -EINVAL;
2169 }
2170
2171 /* Length must align on block boundary */
2172 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2173 MTDDEBUG (MTD_DEBUG_LEVEL0,
2174 "nand_erase: Length not block aligned\n");
2175 return -EINVAL;
2176 }
2177
2178 /* Do not allow erase past end of device */
2179 if ((instr->len + instr->addr) > mtd->size) {
2180 MTDDEBUG (MTD_DEBUG_LEVEL0,
2181 "nand_erase: Erase past end of device\n");
2182 return -EINVAL;
2183 }
2184
2185 instr->fail_addr = 0xffffffff;
2186
2187 /* Grab the lock and see if the device is available */
2188 nand_get_device(chip, mtd, FL_ERASING);
2189
2190 /* Shift to get first page */
2191 page = (int)(instr->addr >> chip->page_shift);
2192 chipnr = (int)(instr->addr >> chip->chip_shift);
2193
2194 /* Calculate pages in each block */
2195 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2196
2197 /* Select the NAND device */
2198 chip->select_chip(mtd, chipnr);
2199
2200 /* Check, if it is write protected */
2201 if (nand_check_wp(mtd)) {
2202 MTDDEBUG (MTD_DEBUG_LEVEL0,
2203 "nand_erase: Device is write protected!!!\n");
2204 instr->state = MTD_ERASE_FAILED;
2205 goto erase_exit;
2206 }
2207
2208 /*
2209 * If BBT requires refresh, set the BBT page mask to see if the BBT
2210 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2211 * can not be matched. This is also done when the bbt is actually
2212 * erased to avoid recusrsive updates
2213 */
2214 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2215 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2216
2217 /* Loop through the pages */
2218 len = instr->len;
2219
2220 instr->state = MTD_ERASING;
2221
2222 while (len) {
2223 WATCHDOG_RESET();
2224 /*
2225 * heck if we have a bad block, we do not erase bad blocks !
2226 */
2227 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2228 chip->page_shift, 0, allowbbt)) {
2229 printk(KERN_WARNING "nand_erase: attempt to erase a "
2230 "bad block at page 0x%08x\n", page);
2231 instr->state = MTD_ERASE_FAILED;
2232 goto erase_exit;
2233 }
2234
2235 /*
2236 * Invalidate the page cache, if we erase the block which
2237 * contains the current cached page
2238 */
2239 if (page <= chip->pagebuf && chip->pagebuf <
2240 (page + pages_per_block))
2241 chip->pagebuf = -1;
2242
2243 chip->erase_cmd(mtd, page & chip->pagemask);
2244
2245 status = chip->waitfunc(mtd, chip);
2246
2247 /*
2248 * See if operation failed and additional status checks are
2249 * available
2250 */
2251 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2252 status = chip->errstat(mtd, chip, FL_ERASING,
2253 status, page);
2254
2255 /* See if block erase succeeded */
2256 if (status & NAND_STATUS_FAIL) {
2257 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2258 "Failed erase, page 0x%08x\n", page);
2259 instr->state = MTD_ERASE_FAILED;
2260 instr->fail_addr = ((loff_t)page << chip->page_shift);
2261 goto erase_exit;
2262 }
2263
2264 /*
2265 * If BBT requires refresh, set the BBT rewrite flag to the
2266 * page being erased
2267 */
2268 if (bbt_masked_page != 0xffffffff &&
2269 (page & BBT_PAGE_MASK) == bbt_masked_page)
2270 rewrite_bbt[chipnr] =
2271 ((loff_t)page << chip->page_shift);
2272
2273 /* Increment page address and decrement length */
2274 len -= (1 << chip->phys_erase_shift);
2275 page += pages_per_block;
2276
2277 /* Check, if we cross a chip boundary */
2278 if (len && !(page & chip->pagemask)) {
2279 chipnr++;
2280 chip->select_chip(mtd, -1);
2281 chip->select_chip(mtd, chipnr);
2282
2283 /*
2284 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2285 * page mask to see if this BBT should be rewritten
2286 */
2287 if (bbt_masked_page != 0xffffffff &&
2288 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2289 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2290 BBT_PAGE_MASK;
2291 }
2292 }
2293 instr->state = MTD_ERASE_DONE;
2294
2295 erase_exit:
2296
2297 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2298
2299 /* Deselect and wake up anyone waiting on the device */
2300 nand_release_device(mtd);
2301
2302 /* Do call back function */
2303 if (!ret)
2304 mtd_erase_callback(instr);
2305
2306 /*
2307 * If BBT requires refresh and erase was successful, rewrite any
2308 * selected bad block tables
2309 */
2310 if (bbt_masked_page == 0xffffffff || ret)
2311 return ret;
2312
2313 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2314 if (!rewrite_bbt[chipnr])
2315 continue;
2316 /* update the BBT for chip */
2317 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2318 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2319 chip->bbt_td->pages[chipnr]);
2320 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2321 }
2322
2323 /* Return more or less happy */
2324 return ret;
2325 }
2326
2327 /**
2328 * nand_sync - [MTD Interface] sync
2329 * @mtd: MTD device structure
2330 *
2331 * Sync is actually a wait for chip ready function
2332 */
2333 static void nand_sync(struct mtd_info *mtd)
2334 {
2335 struct nand_chip *chip = mtd->priv;
2336
2337 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2338
2339 /* Grab the lock and see if the device is available */
2340 nand_get_device(chip, mtd, FL_SYNCING);
2341 /* Release it and go back */
2342 nand_release_device(mtd);
2343 }
2344
2345 /**
2346 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2347 * @mtd: MTD device structure
2348 * @offs: offset relative to mtd start
2349 */
2350 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2351 {
2352 /* Check for invalid offset */
2353 if (offs > mtd->size)
2354 return -EINVAL;
2355
2356 return nand_block_checkbad(mtd, offs, 1, 0);
2357 }
2358
2359 /**
2360 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2361 * @mtd: MTD device structure
2362 * @ofs: offset relative to mtd start
2363 */
2364 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2365 {
2366 struct nand_chip *chip = mtd->priv;
2367 int ret;
2368
2369 if ((ret = nand_block_isbad(mtd, ofs))) {
2370 /* If it was bad already, return success and do nothing. */
2371 if (ret > 0)
2372 return 0;
2373 return ret;
2374 }
2375
2376 return chip->block_markbad(mtd, ofs);
2377 }
2378
2379 /*
2380 * Set default functions
2381 */
2382 static void nand_set_defaults(struct nand_chip *chip, int busw)
2383 {
2384 /* check for proper chip_delay setup, set 20us if not */
2385 if (!chip->chip_delay)
2386 chip->chip_delay = 20;
2387
2388 /* check, if a user supplied command function given */
2389 if (chip->cmdfunc == NULL)
2390 chip->cmdfunc = nand_command;
2391
2392 /* check, if a user supplied wait function given */
2393 if (chip->waitfunc == NULL)
2394 chip->waitfunc = nand_wait;
2395
2396 if (!chip->select_chip)
2397 chip->select_chip = nand_select_chip;
2398 if (!chip->read_byte)
2399 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2400 if (!chip->read_word)
2401 chip->read_word = nand_read_word;
2402 if (!chip->block_bad)
2403 chip->block_bad = nand_block_bad;
2404 if (!chip->block_markbad)
2405 chip->block_markbad = nand_default_block_markbad;
2406 if (!chip->write_buf)
2407 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2408 if (!chip->read_buf)
2409 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2410 if (!chip->verify_buf)
2411 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2412 if (!chip->scan_bbt)
2413 chip->scan_bbt = nand_default_bbt;
2414 if (!chip->controller)
2415 chip->controller = &chip->hwcontrol;
2416 }
2417
2418 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2419 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2420 {
2421 int i;
2422
2423 while (len--) {
2424 crc ^= *p++ << 8;
2425 for (i = 0; i < 8; i++)
2426 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2427 }
2428
2429 return crc;
2430 }
2431
2432 /*
2433 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2434 */
2435 static int nand_flash_detect_onfi(struct mtd_info *mtd,
2436 struct nand_chip *chip,
2437 int *busw)
2438 {
2439 struct nand_onfi_params *p = &chip->onfi_params;
2440 int i;
2441 int val;
2442
2443 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2444 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2445 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2446 return 0;
2447
2448 printk(KERN_INFO "ONFI flash detected\n");
2449 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2450 for (i = 0; i < 3; i++) {
2451 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2452 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2453 le16_to_cpu(p->crc)) {
2454 printk(KERN_INFO "ONFI param page %d valid\n", i);
2455 break;
2456 }
2457 }
2458
2459 if (i == 3)
2460 return 0;
2461
2462 /* check version */
2463 val = le16_to_cpu(p->revision);
2464 if (val == 1 || val > (1 << 4)) {
2465 printk(KERN_INFO "%s: unsupported ONFI "
2466 "version: %d\n", __func__, val);
2467 return 0;
2468 }
2469
2470 if (val & (1 << 4))
2471 chip->onfi_version = 22;
2472 else if (val & (1 << 3))
2473 chip->onfi_version = 21;
2474 else if (val & (1 << 2))
2475 chip->onfi_version = 20;
2476 else
2477 chip->onfi_version = 10;
2478
2479 if (!mtd->name)
2480 mtd->name = p->model;
2481
2482 mtd->writesize = le32_to_cpu(p->byte_per_page);
2483 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2484 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2485 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2486 *busw = 0;
2487 if (le16_to_cpu(p->features) & 1)
2488 *busw = NAND_BUSWIDTH_16;
2489
2490 return 1;
2491 }
2492 #else
2493 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2494 struct nand_chip *chip,
2495 int *busw)
2496 {
2497 return 0;
2498 }
2499 #endif
2500
2501 static void nand_flash_detect_non_onfi(struct mtd_info *mtd,
2502 struct nand_chip *chip,
2503 const struct nand_flash_dev *type,
2504 int *busw)
2505 {
2506 /* Newer devices have all the information in additional id bytes */
2507 if (!type->pagesize) {
2508 int extid;
2509 /* The 3rd id byte holds MLC / multichip data */
2510 chip->cellinfo = chip->read_byte(mtd);
2511 /* The 4th id byte is the important one */
2512 extid = chip->read_byte(mtd);
2513 /* Calc pagesize */
2514 mtd->writesize = 1024 << (extid & 0x3);
2515 extid >>= 2;
2516 /* Calc oobsize */
2517 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2518 extid >>= 2;
2519 /* Calc blocksize. Blocksize is multiples of 64KiB */
2520 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2521 extid >>= 2;
2522 /* Get buswidth information */
2523 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2524
2525 } else {
2526 /*
2527 * Old devices have chip data hardcoded in the device id table
2528 */
2529 mtd->erasesize = type->erasesize;
2530 mtd->writesize = type->pagesize;
2531 mtd->oobsize = mtd->writesize / 32;
2532 *busw = type->options & NAND_BUSWIDTH_16;
2533 }
2534 }
2535
2536 /*
2537 * Get the flash and manufacturer id and lookup if the type is supported
2538 */
2539 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2540 struct nand_chip *chip,
2541 int busw,
2542 int *maf_id, int *dev_id,
2543 const struct nand_flash_dev *type)
2544 {
2545 int ret, maf_idx;
2546 int tmp_id, tmp_manf;
2547
2548 /* Select the device */
2549 chip->select_chip(mtd, 0);
2550
2551 /*
2552 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2553 * after power-up
2554 */
2555 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2556
2557 /* Send the command for reading device ID */
2558 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2559
2560 /* Read manufacturer and device IDs */
2561 *maf_id = chip->read_byte(mtd);
2562 *dev_id = chip->read_byte(mtd);
2563
2564 /* Try again to make sure, as some systems the bus-hold or other
2565 * interface concerns can cause random data which looks like a
2566 * possibly credible NAND flash to appear. If the two results do
2567 * not match, ignore the device completely.
2568 */
2569
2570 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2571
2572 /* Read manufacturer and device IDs */
2573
2574 tmp_manf = chip->read_byte(mtd);
2575 tmp_id = chip->read_byte(mtd);
2576
2577 if (tmp_manf != *maf_id || tmp_id != *dev_id) {
2578 printk(KERN_INFO "%s: second ID read did not match "
2579 "%02x,%02x against %02x,%02x\n", __func__,
2580 *maf_id, *dev_id, tmp_manf, tmp_id);
2581 return ERR_PTR(-ENODEV);
2582 }
2583
2584 if (!type)
2585 type = nand_flash_ids;
2586
2587 for (; type->name != NULL; type++)
2588 if (*dev_id == type->id)
2589 break;
2590
2591 if (!type->name) {
2592 /* supress warning if there is no nand */
2593 if (*maf_id != 0x00 && *maf_id != 0xff &&
2594 *dev_id != 0x00 && *dev_id != 0xff)
2595 printk(KERN_INFO "%s: unknown NAND device: "
2596 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2597 __func__, *maf_id, *dev_id);
2598 return ERR_PTR(-ENODEV);
2599 }
2600
2601 if (!mtd->name)
2602 mtd->name = type->name;
2603
2604 chip->chipsize = (uint64_t)type->chipsize << 20;
2605 chip->onfi_version = 0;
2606
2607 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2608 if (!ret)
2609 nand_flash_detect_non_onfi(mtd, chip, type, &busw);
2610
2611 /* Get chip options, preserve non chip based options */
2612 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2613 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2614
2615 /*
2616 * Set chip as a default. Board drivers can override it, if necessary
2617 */
2618 chip->options |= NAND_NO_AUTOINCR;
2619
2620 /* Try to identify manufacturer */
2621 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2622 if (nand_manuf_ids[maf_idx].id == *maf_id)
2623 break;
2624 }
2625
2626 /*
2627 * Check, if buswidth is correct. Hardware drivers should set
2628 * chip correct !
2629 */
2630 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2631 printk(KERN_INFO "NAND device: Manufacturer ID:"
2632 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2633 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2634 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2635 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2636 busw ? 16 : 8);
2637 return ERR_PTR(-EINVAL);
2638 }
2639
2640 /* Calculate the address shift from the page size */
2641 chip->page_shift = ffs(mtd->writesize) - 1;
2642 /* Convert chipsize to number of pages per chip -1. */
2643 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2644
2645 chip->bbt_erase_shift = chip->phys_erase_shift =
2646 ffs(mtd->erasesize) - 1;
2647 if (chip->chipsize & 0xffffffff)
2648 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2649 else
2650 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2651
2652 /* Set the bad block position */
2653 chip->badblockpos = mtd->writesize > 512 ?
2654 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2655
2656 /* Check if chip is a not a samsung device. Do not clear the
2657 * options for chips which are not having an extended id.
2658 */
2659 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2660 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2661
2662 /* Check for AND chips with 4 page planes */
2663 if (chip->options & NAND_4PAGE_ARRAY)
2664 chip->erase_cmd = multi_erase_cmd;
2665 else
2666 chip->erase_cmd = single_erase_cmd;
2667
2668 /* Do not replace user supplied command function ! */
2669 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2670 chip->cmdfunc = nand_command_lp;
2671
2672 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2673 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2674 nand_manuf_ids[maf_idx].name, type->name);
2675
2676 return type;
2677 }
2678
2679 /**
2680 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2681 * @mtd: MTD device structure
2682 * @maxchips: Number of chips to scan for
2683 * @table: Alternative NAND ID table
2684 *
2685 * This is the first phase of the normal nand_scan() function. It
2686 * reads the flash ID and sets up MTD fields accordingly.
2687 *
2688 * The mtd->owner field must be set to the module of the caller.
2689 */
2690 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2691 const struct nand_flash_dev *table)
2692 {
2693 int i, busw, nand_maf_id, nand_dev_id;
2694 struct nand_chip *chip = mtd->priv;
2695 const struct nand_flash_dev *type;
2696
2697 /* Get buswidth to select the correct functions */
2698 busw = chip->options & NAND_BUSWIDTH_16;
2699 /* Set the default functions */
2700 nand_set_defaults(chip, busw);
2701
2702 /* Read the flash type */
2703 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, &nand_dev_id, table);
2704
2705 if (IS_ERR(type)) {
2706 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2707 printk(KERN_WARNING "No NAND device found!!!\n");
2708 #endif
2709 chip->select_chip(mtd, -1);
2710 return PTR_ERR(type);
2711 }
2712
2713 /* Check for a chip array */
2714 for (i = 1; i < maxchips; i++) {
2715 chip->select_chip(mtd, i);
2716 /* See comment in nand_get_flash_type for reset */
2717 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2718 /* Send the command for reading device ID */
2719 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2720 /* Read manufacturer and device IDs */
2721 if (nand_maf_id != chip->read_byte(mtd) ||
2722 nand_dev_id != chip->read_byte(mtd))
2723 break;
2724 }
2725 #ifdef DEBUG
2726 if (i > 1)
2727 printk(KERN_INFO "%d NAND chips detected\n", i);
2728 #endif
2729
2730 /* Store the number of chips and calc total size for mtd */
2731 chip->numchips = i;
2732 mtd->size = i * chip->chipsize;
2733
2734 return 0;
2735 }
2736
2737
2738 /**
2739 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2740 * @mtd: MTD device structure
2741 *
2742 * This is the second phase of the normal nand_scan() function. It
2743 * fills out all the uninitialized function pointers with the defaults
2744 * and scans for a bad block table if appropriate.
2745 */
2746 int nand_scan_tail(struct mtd_info *mtd)
2747 {
2748 int i;
2749 struct nand_chip *chip = mtd->priv;
2750
2751 if (!(chip->options & NAND_OWN_BUFFERS))
2752 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2753 if (!chip->buffers)
2754 return -ENOMEM;
2755
2756 /* Set the internal oob buffer location, just after the page data */
2757 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2758
2759 /*
2760 * If no default placement scheme is given, select an appropriate one
2761 */
2762 if (!chip->ecc.layout) {
2763 switch (mtd->oobsize) {
2764 case 8:
2765 chip->ecc.layout = &nand_oob_8;
2766 break;
2767 case 16:
2768 chip->ecc.layout = &nand_oob_16;
2769 break;
2770 case 64:
2771 chip->ecc.layout = &nand_oob_64;
2772 break;
2773 case 128:
2774 chip->ecc.layout = &nand_oob_128;
2775 break;
2776 default:
2777 printk(KERN_WARNING "No oob scheme defined for "
2778 "oobsize %d\n", mtd->oobsize);
2779 }
2780 }
2781
2782 if (!chip->write_page)
2783 chip->write_page = nand_write_page;
2784
2785 /*
2786 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2787 * selected and we have 256 byte pagesize fallback to software ECC
2788 */
2789
2790 switch (chip->ecc.mode) {
2791 case NAND_ECC_HW_OOB_FIRST:
2792 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2793 if (!chip->ecc.calculate || !chip->ecc.correct ||
2794 !chip->ecc.hwctl) {
2795 printk(KERN_WARNING "No ECC functions supplied, "
2796 "Hardware ECC not possible\n");
2797 BUG();
2798 }
2799 if (!chip->ecc.read_page)
2800 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2801
2802 case NAND_ECC_HW:
2803 /* Use standard hwecc read page function ? */
2804 if (!chip->ecc.read_page)
2805 chip->ecc.read_page = nand_read_page_hwecc;
2806 if (!chip->ecc.write_page)
2807 chip->ecc.write_page = nand_write_page_hwecc;
2808 if (!chip->ecc.read_page_raw)
2809 chip->ecc.read_page_raw = nand_read_page_raw;
2810 if (!chip->ecc.write_page_raw)
2811 chip->ecc.write_page_raw = nand_write_page_raw;
2812 if (!chip->ecc.read_oob)
2813 chip->ecc.read_oob = nand_read_oob_std;
2814 if (!chip->ecc.write_oob)
2815 chip->ecc.write_oob = nand_write_oob_std;
2816
2817 case NAND_ECC_HW_SYNDROME:
2818 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2819 !chip->ecc.hwctl) &&
2820 (!chip->ecc.read_page ||
2821 chip->ecc.read_page == nand_read_page_hwecc ||
2822 !chip->ecc.write_page ||
2823 chip->ecc.write_page == nand_write_page_hwecc)) {
2824 printk(KERN_WARNING "No ECC functions supplied, "
2825 "Hardware ECC not possible\n");
2826 BUG();
2827 }
2828 /* Use standard syndrome read/write page function ? */
2829 if (!chip->ecc.read_page)
2830 chip->ecc.read_page = nand_read_page_syndrome;
2831 if (!chip->ecc.write_page)
2832 chip->ecc.write_page = nand_write_page_syndrome;
2833 if (!chip->ecc.read_page_raw)
2834 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2835 if (!chip->ecc.write_page_raw)
2836 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2837 if (!chip->ecc.read_oob)
2838 chip->ecc.read_oob = nand_read_oob_syndrome;
2839 if (!chip->ecc.write_oob)
2840 chip->ecc.write_oob = nand_write_oob_syndrome;
2841
2842 if (mtd->writesize >= chip->ecc.size)
2843 break;
2844 printk(KERN_WARNING "%d byte HW ECC not possible on "
2845 "%d byte page size, fallback to SW ECC\n",
2846 chip->ecc.size, mtd->writesize);
2847 chip->ecc.mode = NAND_ECC_SOFT;
2848
2849 case NAND_ECC_SOFT:
2850 chip->ecc.calculate = nand_calculate_ecc;
2851 chip->ecc.correct = nand_correct_data;
2852 chip->ecc.read_page = nand_read_page_swecc;
2853 chip->ecc.read_subpage = nand_read_subpage;
2854 chip->ecc.write_page = nand_write_page_swecc;
2855 chip->ecc.read_page_raw = nand_read_page_raw;
2856 chip->ecc.write_page_raw = nand_write_page_raw;
2857 chip->ecc.read_oob = nand_read_oob_std;
2858 chip->ecc.write_oob = nand_write_oob_std;
2859 chip->ecc.size = 256;
2860 chip->ecc.bytes = 3;
2861 break;
2862
2863 case NAND_ECC_NONE:
2864 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2865 "This is not recommended !!\n");
2866 chip->ecc.read_page = nand_read_page_raw;
2867 chip->ecc.write_page = nand_write_page_raw;
2868 chip->ecc.read_oob = nand_read_oob_std;
2869 chip->ecc.read_page_raw = nand_read_page_raw;
2870 chip->ecc.write_page_raw = nand_write_page_raw;
2871 chip->ecc.write_oob = nand_write_oob_std;
2872 chip->ecc.size = mtd->writesize;
2873 chip->ecc.bytes = 0;
2874 break;
2875
2876 default:
2877 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2878 chip->ecc.mode);
2879 BUG();
2880 }
2881
2882 /*
2883 * The number of bytes available for a client to place data into
2884 * the out of band area
2885 */
2886 chip->ecc.layout->oobavail = 0;
2887 for (i = 0; chip->ecc.layout->oobfree[i].length
2888 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2889 chip->ecc.layout->oobavail +=
2890 chip->ecc.layout->oobfree[i].length;
2891 mtd->oobavail = chip->ecc.layout->oobavail;
2892
2893 /*
2894 * Set the number of read / write steps for one page depending on ECC
2895 * mode
2896 */
2897 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2898 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2899 printk(KERN_WARNING "Invalid ecc parameters\n");
2900 BUG();
2901 }
2902 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2903
2904 /*
2905 * Allow subpage writes up to ecc.steps. Not possible for MLC
2906 * FLASH.
2907 */
2908 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2909 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2910 switch(chip->ecc.steps) {
2911 case 2:
2912 mtd->subpage_sft = 1;
2913 break;
2914 case 4:
2915 case 8:
2916 case 16:
2917 mtd->subpage_sft = 2;
2918 break;
2919 }
2920 }
2921 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2922
2923 /* Initialize state */
2924 chip->state = FL_READY;
2925
2926 /* De-select the device */
2927 chip->select_chip(mtd, -1);
2928
2929 /* Invalidate the pagebuffer reference */
2930 chip->pagebuf = -1;
2931
2932 /* Fill in remaining MTD driver data */
2933 mtd->type = MTD_NANDFLASH;
2934 mtd->flags = MTD_CAP_NANDFLASH;
2935 mtd->erase = nand_erase;
2936 mtd->point = NULL;
2937 mtd->unpoint = NULL;
2938 mtd->read = nand_read;
2939 mtd->write = nand_write;
2940 mtd->read_oob = nand_read_oob;
2941 mtd->write_oob = nand_write_oob;
2942 mtd->sync = nand_sync;
2943 mtd->lock = NULL;
2944 mtd->unlock = NULL;
2945 mtd->block_isbad = nand_block_isbad;
2946 mtd->block_markbad = nand_block_markbad;
2947
2948 /* propagate ecc.layout to mtd_info */
2949 mtd->ecclayout = chip->ecc.layout;
2950
2951 /* Check, if we should skip the bad block table scan */
2952 if (chip->options & NAND_SKIP_BBTSCAN)
2953 chip->options |= NAND_BBT_SCANNED;
2954
2955 return 0;
2956 }
2957
2958 /**
2959 * nand_scan - [NAND Interface] Scan for the NAND device
2960 * @mtd: MTD device structure
2961 * @maxchips: Number of chips to scan for
2962 *
2963 * This fills out all the uninitialized function pointers
2964 * with the defaults.
2965 * The flash ID is read and the mtd/chip structures are
2966 * filled with the appropriate values.
2967 * The mtd->owner field must be set to the module of the caller
2968 *
2969 */
2970 int nand_scan(struct mtd_info *mtd, int maxchips)
2971 {
2972 int ret;
2973
2974 ret = nand_scan_ident(mtd, maxchips, NULL);
2975 if (!ret)
2976 ret = nand_scan_tail(mtd);
2977 return ret;
2978 }
2979
2980 /**
2981 * nand_release - [NAND Interface] Free resources held by the NAND device
2982 * @mtd: MTD device structure
2983 */
2984 void nand_release(struct mtd_info *mtd)
2985 {
2986 struct nand_chip *chip = mtd->priv;
2987
2988 #ifdef CONFIG_MTD_PARTITIONS
2989 /* Deregister partitions */
2990 del_mtd_partitions(mtd);
2991 #endif
2992
2993 /* Free bad block table memory */
2994 kfree(chip->bbt);
2995 if (!(chip->options & NAND_OWN_BUFFERS))
2996 kfree(chip->buffers);
2997 }