3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/rawnand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <linux/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8
= {
60 static struct nand_ecclayout nand_oob_16
= {
62 .eccpos
= {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64
= {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128
= {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
95 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
96 struct mtd_oob_ops
*ops
);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger
);
104 static int check_offs_len(struct mtd_info
*mtd
,
105 loff_t ofs
, uint64_t len
)
107 struct nand_chip
*chip
= mtd_to_nand(mtd
);
110 /* Start address must align on block boundary */
111 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__
);
116 /* Length must align on block boundary */
117 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__
);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info
*mtd
)
133 struct nand_chip
*chip
= mtd_to_nand(mtd
);
135 /* De-select the NAND device */
136 chip
->select_chip(mtd
, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info
*mtd
)
147 struct nand_chip
*chip
= mtd_to_nand(mtd
);
148 return readb(chip
->IO_ADDR_R
);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
160 struct nand_chip
*chip
= mtd_to_nand(mtd
);
161 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16
nand_read_word(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd_to_nand(mtd
);
173 return readw(chip
->IO_ADDR_R
);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
185 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
208 struct nand_chip
*chip
= mtd_to_nand(mtd
);
210 chip
->write_buf(mtd
, &byte
, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
222 struct nand_chip
*chip
= mtd_to_nand(mtd
);
223 uint16_t word
= byte
;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 static void iowrite8_rep(void *addr
, const uint8_t *buf
, int len
)
248 for (i
= 0; i
< len
; i
++)
249 writeb(buf
[i
], addr
);
251 static void ioread8_rep(void *addr
, uint8_t *buf
, int len
)
255 for (i
= 0; i
< len
; i
++)
256 buf
[i
] = readb(addr
);
259 static void ioread16_rep(void *addr
, void *buf
, int len
)
262 u16
*p
= (u16
*) buf
;
264 for (i
= 0; i
< len
; i
++)
268 static void iowrite16_rep(void *addr
, void *buf
, int len
)
271 u16
*p
= (u16
*) buf
;
273 for (i
= 0; i
< len
; i
++)
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
281 * @len: number of bytes to write
283 * Default write function for 8bit buswidth.
285 void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
287 struct nand_chip
*chip
= mtd_to_nand(mtd
);
289 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
298 * Default read function for 8bit buswidth.
300 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
302 struct nand_chip
*chip
= mtd_to_nand(mtd
);
304 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
311 * @len: number of bytes to write
313 * Default write function for 16bit buswidth.
315 void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
317 struct nand_chip
*chip
= mtd_to_nand(mtd
);
318 u16
*p
= (u16
*) buf
;
320 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
329 * Default read function for 16bit buswidth.
331 void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
333 struct nand_chip
*chip
= mtd_to_nand(mtd
);
334 u16
*p
= (u16
*) buf
;
336 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
344 * Check, if the block is bad.
346 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
348 int page
, res
= 0, i
= 0;
349 struct nand_chip
*chip
= mtd_to_nand(mtd
);
352 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
353 ofs
+= mtd
->erasesize
- mtd
->writesize
;
355 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
358 if (chip
->options
& NAND_BUSWIDTH_16
) {
359 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
360 chip
->badblockpos
& 0xFE, page
);
361 bad
= cpu_to_le16(chip
->read_word(mtd
));
362 if (chip
->badblockpos
& 0x1)
367 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
369 bad
= chip
->read_byte(mtd
);
372 if (likely(chip
->badblockbits
== 8))
375 res
= hweight8(bad
) < chip
->badblockbits
;
376 ofs
+= mtd
->writesize
;
377 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
379 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
393 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
395 struct nand_chip
*chip
= mtd_to_nand(mtd
);
396 struct mtd_oob_ops ops
;
397 uint8_t buf
[2] = { 0, 0 };
398 int ret
= 0, res
, i
= 0;
400 memset(&ops
, 0, sizeof(ops
));
402 ops
.ooboffs
= chip
->badblockpos
;
403 if (chip
->options
& NAND_BUSWIDTH_16
) {
404 ops
.ooboffs
&= ~0x01;
405 ops
.len
= ops
.ooblen
= 2;
407 ops
.len
= ops
.ooblen
= 1;
409 ops
.mode
= MTD_OPS_PLACE_OOB
;
411 /* Write to first/last page(s) if necessary */
412 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
413 ofs
+= mtd
->erasesize
- mtd
->writesize
;
415 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
420 ofs
+= mtd
->writesize
;
421 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
443 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
445 struct nand_chip
*chip
= mtd_to_nand(mtd
);
448 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
449 struct erase_info einfo
;
451 /* Attempt erase before marking OOB */
452 memset(&einfo
, 0, sizeof(einfo
));
455 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
456 nand_erase_nand(mtd
, &einfo
, 0);
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd
, FL_WRITING
);
460 ret
= chip
->block_markbad(mtd
, ofs
);
461 nand_release_device(mtd
);
464 /* Mark block bad in BBT */
466 res
= nand_markbad_bbt(mtd
, ofs
);
472 mtd
->ecc_stats
.badblocks
++;
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
484 static int nand_check_wp(struct mtd_info
*mtd
)
486 struct nand_chip
*chip
= mtd_to_nand(mtd
);
488 /* Broken xD cards report WP despite being writable */
489 if (chip
->options
& NAND_BROKEN_XD
)
492 /* Check the WP bit */
493 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
494 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
502 * Check if the block is marked as reserved.
504 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
506 struct nand_chip
*chip
= mtd_to_nand(mtd
);
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd
, ofs
);
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
523 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
525 struct nand_chip
*chip
= mtd_to_nand(mtd
);
527 if (!(chip
->options
& NAND_SKIP_BBTSCAN
) &&
528 !(chip
->options
& NAND_BBT_SCANNED
)) {
529 chip
->options
|= NAND_BBT_SCANNED
;
534 return chip
->block_bad(mtd
, ofs
);
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
546 void nand_wait_ready(struct mtd_info
*mtd
)
548 struct nand_chip
*chip
= mtd_to_nand(mtd
);
549 u32 timeo
= (CONFIG_SYS_HZ
* 400) / 1000;
552 time_start
= get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start
) < timeo
) {
556 if (chip
->dev_ready(mtd
))
560 if (!chip
->dev_ready(mtd
))
561 pr_warn("timeout while waiting for chip to become ready\n");
563 EXPORT_SYMBOL_GPL(nand_wait_ready
);
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
570 * Wait for status ready (i.e. command done) or timeout.
572 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
574 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
577 timeo
= (CONFIG_SYS_HZ
* timeo
) / 1000;
578 time_start
= get_timer(0);
579 while (get_timer(time_start
) < timeo
) {
580 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
597 int column
, int page_addr
)
599 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
600 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
602 /* Write out the command to the device */
603 if (command
== NAND_CMD_SEQIN
) {
606 if (column
>= mtd
->writesize
) {
608 column
-= mtd
->writesize
;
609 readcmd
= NAND_CMD_READOOB
;
610 } else if (column
< 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd
= NAND_CMD_READ0
;
615 readcmd
= NAND_CMD_READ1
;
617 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
618 ctrl
&= ~NAND_CTRL_CHANGE
;
620 chip
->cmd_ctrl(mtd
, command
, ctrl
);
622 /* Address cycle, when necessary */
623 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip
->options
& NAND_BUSWIDTH_16
&&
628 !nand_opcode_8bits(command
))
630 chip
->cmd_ctrl(mtd
, column
, ctrl
);
631 ctrl
&= ~NAND_CTRL_CHANGE
;
633 if (page_addr
!= -1) {
634 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
635 ctrl
&= ~NAND_CTRL_CHANGE
;
636 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
637 if (chip
->options
& NAND_ROW_ADDR_3
)
638 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
640 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
643 * Program and erase have their own busy handlers status and sequential
648 case NAND_CMD_PAGEPROG
:
649 case NAND_CMD_ERASE1
:
650 case NAND_CMD_ERASE2
:
652 case NAND_CMD_STATUS
:
653 case NAND_CMD_READID
:
654 case NAND_CMD_SET_FEATURES
:
660 udelay(chip
->chip_delay
);
661 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
662 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
664 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
665 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
666 nand_wait_status_ready(mtd
, 250);
669 /* This applies to read commands */
672 * If we don't have access to the busy pin, we apply the given
675 if (!chip
->dev_ready
) {
676 udelay(chip
->chip_delay
);
681 * Apply this short delay always to ensure that we do wait tWB in
682 * any case on any machine.
686 nand_wait_ready(mtd
);
690 * nand_command_lp - [DEFAULT] Send command to NAND large page device
691 * @mtd: MTD device structure
692 * @command: the command to be sent
693 * @column: the column address for this command, -1 if none
694 * @page_addr: the page address for this command, -1 if none
696 * Send command to NAND device. This is the version for the new large page
697 * devices. We don't have the separate regions as we have in the small page
698 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
700 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
701 int column
, int page_addr
)
703 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
705 /* Emulate NAND_CMD_READOOB */
706 if (command
== NAND_CMD_READOOB
) {
707 column
+= mtd
->writesize
;
708 command
= NAND_CMD_READ0
;
711 /* Command latch cycle */
712 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
714 if (column
!= -1 || page_addr
!= -1) {
715 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
717 /* Serially input address */
719 /* Adjust columns for 16 bit buswidth */
720 if (chip
->options
& NAND_BUSWIDTH_16
&&
721 !nand_opcode_8bits(command
))
723 chip
->cmd_ctrl(mtd
, column
, ctrl
);
724 ctrl
&= ~NAND_CTRL_CHANGE
;
725 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
727 if (page_addr
!= -1) {
728 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
729 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
730 NAND_NCE
| NAND_ALE
);
731 if (chip
->options
& NAND_ROW_ADDR_3
)
732 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
733 NAND_NCE
| NAND_ALE
);
736 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
739 * Program and erase have their own busy handlers status, sequential
740 * in and status need no delay.
744 case NAND_CMD_CACHEDPROG
:
745 case NAND_CMD_PAGEPROG
:
746 case NAND_CMD_ERASE1
:
747 case NAND_CMD_ERASE2
:
750 case NAND_CMD_STATUS
:
751 case NAND_CMD_READID
:
752 case NAND_CMD_SET_FEATURES
:
758 udelay(chip
->chip_delay
);
759 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
760 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
761 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
762 NAND_NCE
| NAND_CTRL_CHANGE
);
763 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
764 nand_wait_status_ready(mtd
, 250);
767 case NAND_CMD_RNDOUT
:
768 /* No ready / busy check necessary */
769 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
770 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
771 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
772 NAND_NCE
| NAND_CTRL_CHANGE
);
776 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
777 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
778 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
779 NAND_NCE
| NAND_CTRL_CHANGE
);
781 /* This applies to read commands */
784 * If we don't have access to the busy pin, we apply the given
787 if (!chip
->dev_ready
) {
788 udelay(chip
->chip_delay
);
794 * Apply this short delay always to ensure that we do wait tWB in
795 * any case on any machine.
799 nand_wait_ready(mtd
);
803 * panic_nand_get_device - [GENERIC] Get chip for selected access
804 * @chip: the nand chip descriptor
805 * @mtd: MTD device structure
806 * @new_state: the state which is requested
808 * Used when in panic, no locks are taken.
810 static void panic_nand_get_device(struct nand_chip
*chip
,
811 struct mtd_info
*mtd
, int new_state
)
813 /* Hardware controller shared among independent devices */
814 chip
->controller
->active
= chip
;
815 chip
->state
= new_state
;
819 * nand_get_device - [GENERIC] Get chip for selected access
820 * @mtd: MTD device structure
821 * @new_state: the state which is requested
823 * Get the device and lock it for exclusive access
826 nand_get_device(struct mtd_info
*mtd
, int new_state
)
828 struct nand_chip
*chip
= mtd_to_nand(mtd
);
829 chip
->state
= new_state
;
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
843 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
847 for (i
= 0; i
< timeo
; i
++) {
848 if (chip
->dev_ready
) {
849 if (chip
->dev_ready(mtd
))
852 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
864 * Wait for command done. This applies to erase and program only.
866 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
869 unsigned long timeo
= 400;
871 led_trigger_event(nand_led_trigger
, LED_FULL
);
874 * Apply this short delay always to ensure that we do wait tWB in any
875 * case on any machine.
879 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
881 u32 timer
= (CONFIG_SYS_HZ
* timeo
) / 1000;
884 time_start
= get_timer(0);
885 while (get_timer(time_start
) < timer
) {
886 if (chip
->dev_ready
) {
887 if (chip
->dev_ready(mtd
))
890 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
894 led_trigger_event(nand_led_trigger
, LED_OFF
);
896 status
= (int)chip
->read_byte(mtd
);
897 /* This can happen if in case of timeout or buggy dev_ready */
898 WARN_ON(!(status
& NAND_STATUS_READY
));
903 * nand_reset_data_interface - Reset data interface and timings
904 * @chip: The NAND chip
905 * @chipnr: Internal die id
907 * Reset the Data interface and timings to ONFI mode 0.
909 * Returns 0 for success or negative error code otherwise.
911 static int nand_reset_data_interface(struct nand_chip
*chip
, int chipnr
)
913 struct mtd_info
*mtd
= nand_to_mtd(chip
);
914 const struct nand_data_interface
*conf
;
917 if (!chip
->setup_data_interface
)
921 * The ONFI specification says:
923 * To transition from NV-DDR or NV-DDR2 to the SDR data
924 * interface, the host shall use the Reset (FFh) command
925 * using SDR timing mode 0. A device in any timing mode is
926 * required to recognize Reset (FFh) command issued in SDR
930 * Configure the data interface in SDR mode and set the
931 * timings to timing mode 0.
934 conf
= nand_get_default_data_interface();
935 ret
= chip
->setup_data_interface(mtd
, chipnr
, conf
);
937 pr_err("Failed to configure data interface to SDR timing mode 0\n");
943 * nand_setup_data_interface - Setup the best data interface and timings
944 * @chip: The NAND chip
945 * @chipnr: Internal die id
947 * Find and configure the best data interface and NAND timings supported by
948 * the chip and the driver.
949 * First tries to retrieve supported timing modes from ONFI information,
950 * and if the NAND chip does not support ONFI, relies on the
951 * ->onfi_timing_mode_default specified in the nand_ids table.
953 * Returns 0 for success or negative error code otherwise.
955 static int nand_setup_data_interface(struct nand_chip
*chip
, int chipnr
)
957 struct mtd_info
*mtd
= nand_to_mtd(chip
);
960 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
964 * Ensure the timing mode has been changed on the chip side
965 * before changing timings on the controller side.
967 if (chip
->onfi_version
) {
968 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
969 chip
->onfi_timing_mode_default
,
972 ret
= chip
->onfi_set_features(mtd
, chip
,
973 ONFI_FEATURE_ADDR_TIMING_MODE
,
979 ret
= chip
->setup_data_interface(mtd
, chipnr
, chip
->data_interface
);
985 * nand_init_data_interface - find the best data interface and timings
986 * @chip: The NAND chip
988 * Find the best data interface and NAND timings supported by the chip
990 * First tries to retrieve supported timing modes from ONFI information,
991 * and if the NAND chip does not support ONFI, relies on the
992 * ->onfi_timing_mode_default specified in the nand_ids table. After this
993 * function nand_chip->data_interface is initialized with the best timing mode
996 * Returns 0 for success or negative error code otherwise.
998 static int nand_init_data_interface(struct nand_chip
*chip
)
1000 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1001 int modes
, mode
, ret
;
1003 if (!chip
->setup_data_interface
)
1007 * First try to identify the best timings from ONFI parameters and
1008 * if the NAND does not support ONFI, fallback to the default ONFI
1011 modes
= onfi_get_async_timing_mode(chip
);
1012 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1013 if (!chip
->onfi_timing_mode_default
)
1016 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1019 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1021 if (!chip
->data_interface
)
1024 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1025 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1026 NAND_SDR_IFACE
, mode
);
1030 /* Pass -1 to only */
1031 ret
= chip
->setup_data_interface(mtd
,
1032 NAND_DATA_IFACE_CHECK_ONLY
,
1033 chip
->data_interface
);
1035 chip
->onfi_timing_mode_default
= mode
;
1043 static void __maybe_unused
nand_release_data_interface(struct nand_chip
*chip
)
1045 kfree(chip
->data_interface
);
1049 * nand_reset - Reset and initialize a NAND device
1050 * @chip: The NAND chip
1051 * @chipnr: Internal die id
1053 * Returns 0 for success or negative error code otherwise
1055 int nand_reset(struct nand_chip
*chip
, int chipnr
)
1057 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1060 ret
= nand_reset_data_interface(chip
, chipnr
);
1065 * The CS line has to be released before we can apply the new NAND
1066 * interface settings, hence this weird ->select_chip() dance.
1068 chip
->select_chip(mtd
, chipnr
);
1069 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1070 chip
->select_chip(mtd
, -1);
1072 chip
->select_chip(mtd
, chipnr
);
1073 ret
= nand_setup_data_interface(chip
, chipnr
);
1074 chip
->select_chip(mtd
, -1);
1082 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1083 * @buf: buffer to test
1084 * @len: buffer length
1085 * @bitflips_threshold: maximum number of bitflips
1087 * Check if a buffer contains only 0xff, which means the underlying region
1088 * has been erased and is ready to be programmed.
1089 * The bitflips_threshold specify the maximum number of bitflips before
1090 * considering the region is not erased.
1091 * Note: The logic of this function has been extracted from the memweight
1092 * implementation, except that nand_check_erased_buf function exit before
1093 * testing the whole buffer if the number of bitflips exceed the
1094 * bitflips_threshold value.
1096 * Returns a positive number of bitflips less than or equal to
1097 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1100 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1102 const unsigned char *bitmap
= buf
;
1106 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1108 weight
= hweight8(*bitmap
);
1109 bitflips
+= BITS_PER_BYTE
- weight
;
1110 if (unlikely(bitflips
> bitflips_threshold
))
1114 for (; len
>= 4; len
-= 4, bitmap
+= 4) {
1115 weight
= hweight32(*((u32
*)bitmap
));
1116 bitflips
+= 32 - weight
;
1117 if (unlikely(bitflips
> bitflips_threshold
))
1121 for (; len
> 0; len
--, bitmap
++) {
1122 weight
= hweight8(*bitmap
);
1123 bitflips
+= BITS_PER_BYTE
- weight
;
1124 if (unlikely(bitflips
> bitflips_threshold
))
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1134 * @data: data buffer to test
1135 * @datalen: data length
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1170 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1171 void *ecc
, int ecclen
,
1172 void *extraoob
, int extraooblen
,
1173 int bitflips_threshold
)
1175 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1177 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1178 bitflips_threshold
);
1179 if (data_bitflips
< 0)
1180 return data_bitflips
;
1182 bitflips_threshold
-= data_bitflips
;
1184 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1185 if (ecc_bitflips
< 0)
1186 return ecc_bitflips
;
1188 bitflips_threshold
-= ecc_bitflips
;
1190 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1191 bitflips_threshold
);
1192 if (extraoob_bitflips
< 0)
1193 return extraoob_bitflips
;
1196 memset(data
, 0xff, datalen
);
1199 memset(ecc
, 0xff, ecclen
);
1201 if (extraoob_bitflips
)
1202 memset(extraoob
, 0xff, extraooblen
);
1204 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1206 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1213 * @oob_required: caller requires OOB data read to chip->oob_poi
1214 * @page: page number to read
1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1218 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1219 uint8_t *buf
, int oob_required
, int page
)
1221 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1223 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @oob_required: caller requires OOB data read to chip->oob_poi
1233 * @page: page number to read
1235 * We need a special oob layout and handling even when OOB isn't used.
1237 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1238 struct nand_chip
*chip
, uint8_t *buf
,
1239 int oob_required
, int page
)
1241 int eccsize
= chip
->ecc
.size
;
1242 int eccbytes
= chip
->ecc
.bytes
;
1243 uint8_t *oob
= chip
->oob_poi
;
1246 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1247 chip
->read_buf(mtd
, buf
, eccsize
);
1250 if (chip
->ecc
.prepad
) {
1251 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1252 oob
+= chip
->ecc
.prepad
;
1255 chip
->read_buf(mtd
, oob
, eccbytes
);
1258 if (chip
->ecc
.postpad
) {
1259 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1260 oob
+= chip
->ecc
.postpad
;
1264 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1266 chip
->read_buf(mtd
, oob
, size
);
1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1279 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1280 uint8_t *buf
, int oob_required
, int page
)
1282 int i
, eccsize
= chip
->ecc
.size
;
1283 int eccbytes
= chip
->ecc
.bytes
;
1284 int eccsteps
= chip
->ecc
.steps
;
1286 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1287 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1288 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1289 unsigned int max_bitflips
= 0;
1291 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1293 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1294 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1296 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1297 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1299 eccsteps
= chip
->ecc
.steps
;
1302 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1305 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1307 mtd
->ecc_stats
.failed
++;
1309 mtd
->ecc_stats
.corrected
+= stat
;
1310 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1313 return max_bitflips
;
1317 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @data_offs: offset of requested data within the page
1321 * @readlen: data length
1322 * @bufpoi: buffer to store read data
1323 * @page: page number to read
1325 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1326 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1329 int start_step
, end_step
, num_steps
;
1330 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1332 int data_col_addr
, i
, gaps
= 0;
1333 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1334 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1336 unsigned int max_bitflips
= 0;
1338 /* Column address within the page aligned to ECC size (256bytes) */
1339 start_step
= data_offs
/ chip
->ecc
.size
;
1340 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1341 num_steps
= end_step
- start_step
+ 1;
1342 index
= start_step
* chip
->ecc
.bytes
;
1344 /* Data size aligned to ECC ecc.size */
1345 datafrag_len
= num_steps
* chip
->ecc
.size
;
1346 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1348 data_col_addr
= start_step
* chip
->ecc
.size
;
1349 /* If we read not a page aligned data */
1350 if (data_col_addr
!= 0)
1351 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1353 p
= bufpoi
+ data_col_addr
;
1354 chip
->read_buf(mtd
, p
, datafrag_len
);
1357 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1358 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1361 * The performance is faster if we position offsets according to
1362 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1364 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1365 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1371 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1372 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1375 * Send the command to read the particular ECC bytes take care
1376 * about buswidth alignment in read_buf.
1378 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1379 aligned_len
= eccfrag_len
;
1380 if (eccpos
[index
] & (busw
- 1))
1382 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1385 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1386 mtd
->writesize
+ aligned_pos
, -1);
1387 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1390 for (i
= 0; i
< eccfrag_len
; i
++)
1391 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1393 p
= bufpoi
+ data_col_addr
;
1394 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1397 stat
= chip
->ecc
.correct(mtd
, p
,
1398 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1399 if (stat
== -EBADMSG
&&
1400 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1401 /* check for empty pages with bitflips */
1402 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1403 &chip
->buffers
->ecccode
[i
],
1406 chip
->ecc
.strength
);
1410 mtd
->ecc_stats
.failed
++;
1412 mtd
->ecc_stats
.corrected
+= stat
;
1413 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1416 return max_bitflips
;
1420 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1424 * @oob_required: caller requires OOB data read to chip->oob_poi
1425 * @page: page number to read
1427 * Not for syndrome calculating ECC controllers which need a special oob layout.
1429 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1430 uint8_t *buf
, int oob_required
, int page
)
1432 int i
, eccsize
= chip
->ecc
.size
;
1433 int eccbytes
= chip
->ecc
.bytes
;
1434 int eccsteps
= chip
->ecc
.steps
;
1436 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1437 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1438 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1439 unsigned int max_bitflips
= 0;
1441 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1442 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1443 chip
->read_buf(mtd
, p
, eccsize
);
1444 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1446 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1448 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1449 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1451 eccsteps
= chip
->ecc
.steps
;
1454 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1457 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1458 if (stat
== -EBADMSG
&&
1459 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1460 /* check for empty pages with bitflips */
1461 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1462 &ecc_code
[i
], eccbytes
,
1464 chip
->ecc
.strength
);
1468 mtd
->ecc_stats
.failed
++;
1470 mtd
->ecc_stats
.corrected
+= stat
;
1471 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1474 return max_bitflips
;
1478 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @buf: buffer to store read data
1482 * @oob_required: caller requires OOB data read to chip->oob_poi
1483 * @page: page number to read
1485 * Hardware ECC for large page chips, require OOB to be read first. For this
1486 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1487 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1488 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1489 * the data area, by overwriting the NAND manufacturer bad block markings.
1491 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1492 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1494 int i
, eccsize
= chip
->ecc
.size
;
1495 int eccbytes
= chip
->ecc
.bytes
;
1496 int eccsteps
= chip
->ecc
.steps
;
1498 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1499 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1500 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1501 unsigned int max_bitflips
= 0;
1503 /* Read the OOB area first */
1504 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1505 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1506 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1508 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1509 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1511 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1514 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1515 chip
->read_buf(mtd
, p
, eccsize
);
1516 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1518 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1519 if (stat
== -EBADMSG
&&
1520 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1521 /* check for empty pages with bitflips */
1522 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1523 &ecc_code
[i
], eccbytes
,
1525 chip
->ecc
.strength
);
1529 mtd
->ecc_stats
.failed
++;
1531 mtd
->ecc_stats
.corrected
+= stat
;
1532 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1535 return max_bitflips
;
1539 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: buffer to store read data
1543 * @oob_required: caller requires OOB data read to chip->oob_poi
1544 * @page: page number to read
1546 * The hw generator calculates the error syndrome automatically. Therefore we
1547 * need a special oob layout and handling.
1549 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1550 uint8_t *buf
, int oob_required
, int page
)
1552 int i
, eccsize
= chip
->ecc
.size
;
1553 int eccbytes
= chip
->ecc
.bytes
;
1554 int eccsteps
= chip
->ecc
.steps
;
1555 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1557 uint8_t *oob
= chip
->oob_poi
;
1558 unsigned int max_bitflips
= 0;
1560 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1563 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1564 chip
->read_buf(mtd
, p
, eccsize
);
1566 if (chip
->ecc
.prepad
) {
1567 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1568 oob
+= chip
->ecc
.prepad
;
1571 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1572 chip
->read_buf(mtd
, oob
, eccbytes
);
1573 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1577 if (chip
->ecc
.postpad
) {
1578 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1579 oob
+= chip
->ecc
.postpad
;
1582 if (stat
== -EBADMSG
&&
1583 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1584 /* check for empty pages with bitflips */
1585 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1589 chip
->ecc
.strength
);
1593 mtd
->ecc_stats
.failed
++;
1595 mtd
->ecc_stats
.corrected
+= stat
;
1596 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1600 /* Calculate remaining oob bytes */
1601 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1603 chip
->read_buf(mtd
, oob
, i
);
1605 return max_bitflips
;
1609 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1610 * @chip: nand chip structure
1611 * @oob: oob destination address
1612 * @ops: oob ops structure
1613 * @len: size of oob to transfer
1615 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1616 struct mtd_oob_ops
*ops
, size_t len
)
1618 switch (ops
->mode
) {
1620 case MTD_OPS_PLACE_OOB
:
1622 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1625 case MTD_OPS_AUTO_OOB
: {
1626 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1627 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1630 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1631 /* Read request not from offset 0? */
1632 if (unlikely(roffs
)) {
1633 if (roffs
>= free
->length
) {
1634 roffs
-= free
->length
;
1637 boffs
= free
->offset
+ roffs
;
1638 bytes
= min_t(size_t, len
,
1639 (free
->length
- roffs
));
1642 bytes
= min_t(size_t, len
, free
->length
);
1643 boffs
= free
->offset
;
1645 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1657 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1658 * @mtd: MTD device structure
1659 * @retry_mode: the retry mode to use
1661 * Some vendors supply a special command to shift the Vt threshold, to be used
1662 * when there are too many bitflips in a page (i.e., ECC error). After setting
1663 * a new threshold, the host should retry reading the page.
1665 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1667 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1669 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1671 if (retry_mode
>= chip
->read_retries
)
1674 if (!chip
->setup_read_retry
)
1677 return chip
->setup_read_retry(mtd
, retry_mode
);
1681 * nand_do_read_ops - [INTERN] Read data with ECC
1682 * @mtd: MTD device structure
1683 * @from: offset to read from
1684 * @ops: oob ops structure
1686 * Internal function. Called with chip held.
1688 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1689 struct mtd_oob_ops
*ops
)
1691 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1692 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1694 uint32_t readlen
= ops
->len
;
1695 uint32_t oobreadlen
= ops
->ooblen
;
1696 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1698 uint8_t *bufpoi
, *oob
, *buf
;
1700 unsigned int max_bitflips
= 0;
1702 bool ecc_fail
= false;
1704 chipnr
= (int)(from
>> chip
->chip_shift
);
1705 chip
->select_chip(mtd
, chipnr
);
1707 realpage
= (int)(from
>> chip
->page_shift
);
1708 page
= realpage
& chip
->pagemask
;
1710 col
= (int)(from
& (mtd
->writesize
- 1));
1714 oob_required
= oob
? 1 : 0;
1717 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1720 bytes
= min(mtd
->writesize
- col
, readlen
);
1721 aligned
= (bytes
== mtd
->writesize
);
1725 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1726 use_bufpoi
= !IS_ALIGNED((unsigned long)buf
,
1731 /* Is the current page in the buffer? */
1732 if (realpage
!= chip
->pagebuf
|| oob
) {
1733 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1735 if (use_bufpoi
&& aligned
)
1736 pr_debug("%s: using read bounce buffer for buf@%p\n",
1740 if (nand_standard_page_accessors(&chip
->ecc
))
1741 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1744 * Now read the page into the buffer. Absent an error,
1745 * the read methods return max bitflips per ecc step.
1747 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1748 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1751 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1753 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1757 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1758 oob_required
, page
);
1761 /* Invalidate page cache */
1766 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1768 /* Transfer not aligned data */
1770 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1771 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1772 (ops
->mode
!= MTD_OPS_RAW
)) {
1773 chip
->pagebuf
= realpage
;
1774 chip
->pagebuf_bitflips
= ret
;
1776 /* Invalidate page cache */
1779 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1782 if (unlikely(oob
)) {
1783 int toread
= min(oobreadlen
, max_oobsize
);
1786 oob
= nand_transfer_oob(chip
,
1788 oobreadlen
-= toread
;
1792 if (chip
->options
& NAND_NEED_READRDY
) {
1793 /* Apply delay or wait for ready/busy pin */
1794 if (!chip
->dev_ready
)
1795 udelay(chip
->chip_delay
);
1797 nand_wait_ready(mtd
);
1800 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1801 if (retry_mode
+ 1 < chip
->read_retries
) {
1803 ret
= nand_setup_read_retry(mtd
,
1808 /* Reset failures; retry */
1809 mtd
->ecc_stats
.failed
= ecc_failures
;
1812 /* No more retry modes; real failure */
1819 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1821 max_bitflips
= max_t(unsigned int, max_bitflips
,
1822 chip
->pagebuf_bitflips
);
1827 /* Reset to retry mode 0 */
1829 ret
= nand_setup_read_retry(mtd
, 0);
1838 /* For subsequent reads align to page boundary */
1840 /* Increment page address */
1843 page
= realpage
& chip
->pagemask
;
1844 /* Check, if we cross a chip boundary */
1847 chip
->select_chip(mtd
, -1);
1848 chip
->select_chip(mtd
, chipnr
);
1851 chip
->select_chip(mtd
, -1);
1853 ops
->retlen
= ops
->len
- (size_t) readlen
;
1855 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1863 return max_bitflips
;
1867 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1868 * @mtd: MTD device structure
1869 * @from: offset to read from
1870 * @len: number of bytes to read
1871 * @retlen: pointer to variable to store the number of read bytes
1872 * @buf: the databuffer to put data
1874 * Get hold of the chip and call nand_do_read.
1876 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1877 size_t *retlen
, uint8_t *buf
)
1879 struct mtd_oob_ops ops
;
1882 nand_get_device(mtd
, FL_READING
);
1883 memset(&ops
, 0, sizeof(ops
));
1886 ops
.mode
= MTD_OPS_PLACE_OOB
;
1887 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1888 *retlen
= ops
.retlen
;
1889 nand_release_device(mtd
);
1894 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1895 * @mtd: mtd info structure
1896 * @chip: nand chip info structure
1897 * @page: page number to read
1899 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1902 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1903 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1908 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1910 * @mtd: mtd info structure
1911 * @chip: nand chip info structure
1912 * @page: page number to read
1914 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1917 int length
= mtd
->oobsize
;
1918 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1919 int eccsize
= chip
->ecc
.size
;
1920 uint8_t *bufpoi
= chip
->oob_poi
;
1921 int i
, toread
, sndrnd
= 0, pos
;
1923 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1924 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1926 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1927 if (mtd
->writesize
> 512)
1928 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1930 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1933 toread
= min_t(int, length
, chunk
);
1934 chip
->read_buf(mtd
, bufpoi
, toread
);
1939 chip
->read_buf(mtd
, bufpoi
, length
);
1945 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1946 * @mtd: mtd info structure
1947 * @chip: nand chip info structure
1948 * @page: page number to write
1950 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1954 const uint8_t *buf
= chip
->oob_poi
;
1955 int length
= mtd
->oobsize
;
1957 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1958 chip
->write_buf(mtd
, buf
, length
);
1959 /* Send command to program the OOB data */
1960 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1962 status
= chip
->waitfunc(mtd
, chip
);
1964 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1968 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1969 * with syndrome - only for large page flash
1970 * @mtd: mtd info structure
1971 * @chip: nand chip info structure
1972 * @page: page number to write
1974 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1975 struct nand_chip
*chip
, int page
)
1977 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1978 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1979 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1980 const uint8_t *bufpoi
= chip
->oob_poi
;
1983 * data-ecc-data-ecc ... ecc-oob
1985 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1987 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1988 pos
= steps
* (eccsize
+ chunk
);
1993 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1994 for (i
= 0; i
< steps
; i
++) {
1996 if (mtd
->writesize
<= 512) {
1997 uint32_t fill
= 0xFFFFFFFF;
2001 int num
= min_t(int, len
, 4);
2002 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2007 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2008 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2012 len
= min_t(int, length
, chunk
);
2013 chip
->write_buf(mtd
, bufpoi
, len
);
2018 chip
->write_buf(mtd
, bufpoi
, length
);
2020 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2021 status
= chip
->waitfunc(mtd
, chip
);
2023 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2027 * nand_do_read_oob - [INTERN] NAND read out-of-band
2028 * @mtd: MTD device structure
2029 * @from: offset to read from
2030 * @ops: oob operations description structure
2032 * NAND read out-of-band data from the spare area.
2034 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2035 struct mtd_oob_ops
*ops
)
2037 int page
, realpage
, chipnr
;
2038 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2039 struct mtd_ecc_stats stats
;
2040 int readlen
= ops
->ooblen
;
2042 uint8_t *buf
= ops
->oobbuf
;
2045 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2046 __func__
, (unsigned long long)from
, readlen
);
2048 stats
= mtd
->ecc_stats
;
2050 len
= mtd_oobavail(mtd
, ops
);
2052 if (unlikely(ops
->ooboffs
>= len
)) {
2053 pr_debug("%s: attempt to start read outside oob\n",
2058 /* Do not allow reads past end of device */
2059 if (unlikely(from
>= mtd
->size
||
2060 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2061 (from
>> chip
->page_shift
)) * len
)) {
2062 pr_debug("%s: attempt to read beyond end of device\n",
2067 chipnr
= (int)(from
>> chip
->chip_shift
);
2068 chip
->select_chip(mtd
, chipnr
);
2070 /* Shift to get page */
2071 realpage
= (int)(from
>> chip
->page_shift
);
2072 page
= realpage
& chip
->pagemask
;
2077 if (ops
->mode
== MTD_OPS_RAW
)
2078 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2080 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2085 len
= min(len
, readlen
);
2086 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
2088 if (chip
->options
& NAND_NEED_READRDY
) {
2089 /* Apply delay or wait for ready/busy pin */
2090 if (!chip
->dev_ready
)
2091 udelay(chip
->chip_delay
);
2093 nand_wait_ready(mtd
);
2100 /* Increment page address */
2103 page
= realpage
& chip
->pagemask
;
2104 /* Check, if we cross a chip boundary */
2107 chip
->select_chip(mtd
, -1);
2108 chip
->select_chip(mtd
, chipnr
);
2111 chip
->select_chip(mtd
, -1);
2113 ops
->oobretlen
= ops
->ooblen
- readlen
;
2118 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2121 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2125 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2126 * @mtd: MTD device structure
2127 * @from: offset to read from
2128 * @ops: oob operation description structure
2130 * NAND read data and/or out-of-band data.
2132 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2133 struct mtd_oob_ops
*ops
)
2135 int ret
= -ENOTSUPP
;
2139 /* Do not allow reads past end of device */
2140 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2141 pr_debug("%s: attempt to read beyond end of device\n",
2146 nand_get_device(mtd
, FL_READING
);
2148 switch (ops
->mode
) {
2149 case MTD_OPS_PLACE_OOB
:
2150 case MTD_OPS_AUTO_OOB
:
2159 ret
= nand_do_read_oob(mtd
, from
, ops
);
2161 ret
= nand_do_read_ops(mtd
, from
, ops
);
2164 nand_release_device(mtd
);
2170 * nand_write_page_raw - [INTERN] raw page write function
2171 * @mtd: mtd info structure
2172 * @chip: nand chip info structure
2174 * @oob_required: must write chip->oob_poi to OOB
2175 * @page: page number to write
2177 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2179 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2180 const uint8_t *buf
, int oob_required
, int page
)
2182 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2184 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2190 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2191 * @mtd: mtd info structure
2192 * @chip: nand chip info structure
2194 * @oob_required: must write chip->oob_poi to OOB
2195 * @page: page number to write
2197 * We need a special oob layout and handling even when ECC isn't checked.
2199 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2200 struct nand_chip
*chip
,
2201 const uint8_t *buf
, int oob_required
,
2204 int eccsize
= chip
->ecc
.size
;
2205 int eccbytes
= chip
->ecc
.bytes
;
2206 uint8_t *oob
= chip
->oob_poi
;
2209 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2210 chip
->write_buf(mtd
, buf
, eccsize
);
2213 if (chip
->ecc
.prepad
) {
2214 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2215 oob
+= chip
->ecc
.prepad
;
2218 chip
->write_buf(mtd
, oob
, eccbytes
);
2221 if (chip
->ecc
.postpad
) {
2222 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2223 oob
+= chip
->ecc
.postpad
;
2227 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2229 chip
->write_buf(mtd
, oob
, size
);
2234 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2235 * @mtd: mtd info structure
2236 * @chip: nand chip info structure
2238 * @oob_required: must write chip->oob_poi to OOB
2239 * @page: page number to write
2241 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2242 const uint8_t *buf
, int oob_required
,
2245 int i
, eccsize
= chip
->ecc
.size
;
2246 int eccbytes
= chip
->ecc
.bytes
;
2247 int eccsteps
= chip
->ecc
.steps
;
2248 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2249 const uint8_t *p
= buf
;
2250 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2252 /* Software ECC calculation */
2253 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2254 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2256 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2257 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2259 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2263 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2264 * @mtd: mtd info structure
2265 * @chip: nand chip info structure
2267 * @oob_required: must write chip->oob_poi to OOB
2268 * @page: page number to write
2270 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2271 const uint8_t *buf
, int oob_required
,
2274 int i
, eccsize
= chip
->ecc
.size
;
2275 int eccbytes
= chip
->ecc
.bytes
;
2276 int eccsteps
= chip
->ecc
.steps
;
2277 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2278 const uint8_t *p
= buf
;
2279 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2281 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2282 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2283 chip
->write_buf(mtd
, p
, eccsize
);
2284 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2287 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2288 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2290 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2297 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2298 * @mtd: mtd info structure
2299 * @chip: nand chip info structure
2300 * @offset: column address of subpage within the page
2301 * @data_len: data length
2303 * @oob_required: must write chip->oob_poi to OOB
2304 * @page: page number to write
2306 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2307 struct nand_chip
*chip
, uint32_t offset
,
2308 uint32_t data_len
, const uint8_t *buf
,
2309 int oob_required
, int page
)
2311 uint8_t *oob_buf
= chip
->oob_poi
;
2312 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2313 int ecc_size
= chip
->ecc
.size
;
2314 int ecc_bytes
= chip
->ecc
.bytes
;
2315 int ecc_steps
= chip
->ecc
.steps
;
2316 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2317 uint32_t start_step
= offset
/ ecc_size
;
2318 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2319 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2322 for (step
= 0; step
< ecc_steps
; step
++) {
2323 /* configure controller for WRITE access */
2324 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2326 /* write data (untouched subpages already masked by 0xFF) */
2327 chip
->write_buf(mtd
, buf
, ecc_size
);
2329 /* mask ECC of un-touched subpages by padding 0xFF */
2330 if ((step
< start_step
) || (step
> end_step
))
2331 memset(ecc_calc
, 0xff, ecc_bytes
);
2333 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2335 /* mask OOB of un-touched subpages by padding 0xFF */
2336 /* if oob_required, preserve OOB metadata of written subpage */
2337 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2338 memset(oob_buf
, 0xff, oob_bytes
);
2341 ecc_calc
+= ecc_bytes
;
2342 oob_buf
+= oob_bytes
;
2345 /* copy calculated ECC for whole page to chip->buffer->oob */
2346 /* this include masked-value(0xFF) for unwritten subpages */
2347 ecc_calc
= chip
->buffers
->ecccalc
;
2348 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2349 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2351 /* write OOB buffer to NAND device */
2352 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2359 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2360 * @mtd: mtd info structure
2361 * @chip: nand chip info structure
2363 * @oob_required: must write chip->oob_poi to OOB
2364 * @page: page number to write
2366 * The hw generator calculates the error syndrome automatically. Therefore we
2367 * need a special oob layout and handling.
2369 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2370 struct nand_chip
*chip
,
2371 const uint8_t *buf
, int oob_required
,
2374 int i
, eccsize
= chip
->ecc
.size
;
2375 int eccbytes
= chip
->ecc
.bytes
;
2376 int eccsteps
= chip
->ecc
.steps
;
2377 const uint8_t *p
= buf
;
2378 uint8_t *oob
= chip
->oob_poi
;
2380 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2382 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2383 chip
->write_buf(mtd
, p
, eccsize
);
2385 if (chip
->ecc
.prepad
) {
2386 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2387 oob
+= chip
->ecc
.prepad
;
2390 chip
->ecc
.calculate(mtd
, p
, oob
);
2391 chip
->write_buf(mtd
, oob
, eccbytes
);
2394 if (chip
->ecc
.postpad
) {
2395 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2396 oob
+= chip
->ecc
.postpad
;
2400 /* Calculate remaining oob bytes */
2401 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2403 chip
->write_buf(mtd
, oob
, i
);
2409 * nand_write_page - [REPLACEABLE] write one page
2410 * @mtd: MTD device structure
2411 * @chip: NAND chip descriptor
2412 * @offset: address offset within the page
2413 * @data_len: length of actual data to be written
2414 * @buf: the data to write
2415 * @oob_required: must write chip->oob_poi to OOB
2416 * @page: page number to write
2417 * @raw: use _raw version of write_page
2419 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2420 uint32_t offset
, int data_len
, const uint8_t *buf
,
2421 int oob_required
, int page
, int raw
)
2423 int status
, subpage
;
2425 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2426 chip
->ecc
.write_subpage
)
2427 subpage
= offset
|| (data_len
< mtd
->writesize
);
2431 if (nand_standard_page_accessors(&chip
->ecc
))
2432 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2435 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2436 oob_required
, page
);
2438 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2439 buf
, oob_required
, page
);
2441 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2447 if (nand_standard_page_accessors(&chip
->ecc
)) {
2448 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2450 status
= chip
->waitfunc(mtd
, chip
);
2451 if (status
& NAND_STATUS_FAIL
)
2459 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2460 * @mtd: MTD device structure
2461 * @oob: oob data buffer
2462 * @len: oob data write length
2463 * @ops: oob ops structure
2465 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2466 struct mtd_oob_ops
*ops
)
2468 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2471 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2472 * data from a previous OOB read.
2474 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2476 switch (ops
->mode
) {
2478 case MTD_OPS_PLACE_OOB
:
2480 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2483 case MTD_OPS_AUTO_OOB
: {
2484 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2485 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2488 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2489 /* Write request not from offset 0? */
2490 if (unlikely(woffs
)) {
2491 if (woffs
>= free
->length
) {
2492 woffs
-= free
->length
;
2495 boffs
= free
->offset
+ woffs
;
2496 bytes
= min_t(size_t, len
,
2497 (free
->length
- woffs
));
2500 bytes
= min_t(size_t, len
, free
->length
);
2501 boffs
= free
->offset
;
2503 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2514 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2517 * nand_do_write_ops - [INTERN] NAND write with ECC
2518 * @mtd: MTD device structure
2519 * @to: offset to write to
2520 * @ops: oob operations description structure
2522 * NAND write with ECC.
2524 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2525 struct mtd_oob_ops
*ops
)
2527 int chipnr
, realpage
, page
, column
;
2528 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2529 uint32_t writelen
= ops
->len
;
2531 uint32_t oobwritelen
= ops
->ooblen
;
2532 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2534 uint8_t *oob
= ops
->oobbuf
;
2535 uint8_t *buf
= ops
->datbuf
;
2537 int oob_required
= oob
? 1 : 0;
2543 /* Reject writes, which are not page aligned */
2544 if (NOTALIGNED(to
)) {
2545 pr_notice("%s: attempt to write non page aligned data\n",
2550 column
= to
& (mtd
->writesize
- 1);
2552 chipnr
= (int)(to
>> chip
->chip_shift
);
2553 chip
->select_chip(mtd
, chipnr
);
2555 /* Check, if it is write protected */
2556 if (nand_check_wp(mtd
)) {
2561 realpage
= (int)(to
>> chip
->page_shift
);
2562 page
= realpage
& chip
->pagemask
;
2564 /* Invalidate the page cache, when we write to the cached page */
2565 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2566 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2569 /* Don't allow multipage oob writes with offset */
2570 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2576 int bytes
= mtd
->writesize
;
2577 uint8_t *wbuf
= buf
;
2579 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2583 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2584 use_bufpoi
= !IS_ALIGNED((unsigned long)buf
,
2590 /* Partial page write?, or need to use bounce buffer */
2592 pr_debug("%s: using write bounce buffer for buf@%p\n",
2595 bytes
= min_t(int, bytes
- column
, writelen
);
2597 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2598 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2599 wbuf
= chip
->buffers
->databuf
;
2602 if (unlikely(oob
)) {
2603 size_t len
= min(oobwritelen
, oobmaxlen
);
2604 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2607 /* We still need to erase leftover OOB data */
2608 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2610 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2612 (ops
->mode
== MTD_OPS_RAW
));
2624 page
= realpage
& chip
->pagemask
;
2625 /* Check, if we cross a chip boundary */
2628 chip
->select_chip(mtd
, -1);
2629 chip
->select_chip(mtd
, chipnr
);
2633 ops
->retlen
= ops
->len
- writelen
;
2635 ops
->oobretlen
= ops
->ooblen
;
2638 chip
->select_chip(mtd
, -1);
2643 * panic_nand_write - [MTD Interface] NAND write with ECC
2644 * @mtd: MTD device structure
2645 * @to: offset to write to
2646 * @len: number of bytes to write
2647 * @retlen: pointer to variable to store the number of written bytes
2648 * @buf: the data to write
2650 * NAND write with ECC. Used when performing writes in interrupt context, this
2651 * may for example be called by mtdoops when writing an oops while in panic.
2653 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2654 size_t *retlen
, const uint8_t *buf
)
2656 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2657 struct mtd_oob_ops ops
;
2660 /* Wait for the device to get ready */
2661 panic_nand_wait(mtd
, chip
, 400);
2663 /* Grab the device */
2664 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2666 memset(&ops
, 0, sizeof(ops
));
2668 ops
.datbuf
= (uint8_t *)buf
;
2669 ops
.mode
= MTD_OPS_PLACE_OOB
;
2671 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2673 *retlen
= ops
.retlen
;
2678 * nand_write - [MTD Interface] NAND write with ECC
2679 * @mtd: MTD device structure
2680 * @to: offset to write to
2681 * @len: number of bytes to write
2682 * @retlen: pointer to variable to store the number of written bytes
2683 * @buf: the data to write
2685 * NAND write with ECC.
2687 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2688 size_t *retlen
, const uint8_t *buf
)
2690 struct mtd_oob_ops ops
;
2693 nand_get_device(mtd
, FL_WRITING
);
2694 memset(&ops
, 0, sizeof(ops
));
2696 ops
.datbuf
= (uint8_t *)buf
;
2697 ops
.mode
= MTD_OPS_PLACE_OOB
;
2698 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2699 *retlen
= ops
.retlen
;
2700 nand_release_device(mtd
);
2705 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2706 * @mtd: MTD device structure
2707 * @to: offset to write to
2708 * @ops: oob operation description structure
2710 * NAND write out-of-band.
2712 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2713 struct mtd_oob_ops
*ops
)
2715 int chipnr
, page
, status
, len
;
2716 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2718 pr_debug("%s: to = 0x%08x, len = %i\n",
2719 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2721 len
= mtd_oobavail(mtd
, ops
);
2723 /* Do not allow write past end of page */
2724 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2725 pr_debug("%s: attempt to write past end of page\n",
2730 if (unlikely(ops
->ooboffs
>= len
)) {
2731 pr_debug("%s: attempt to start write outside oob\n",
2736 /* Do not allow write past end of device */
2737 if (unlikely(to
>= mtd
->size
||
2738 ops
->ooboffs
+ ops
->ooblen
>
2739 ((mtd
->size
>> chip
->page_shift
) -
2740 (to
>> chip
->page_shift
)) * len
)) {
2741 pr_debug("%s: attempt to write beyond end of device\n",
2746 chipnr
= (int)(to
>> chip
->chip_shift
);
2749 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2750 * of my DiskOnChip 2000 test units) will clear the whole data page too
2751 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2752 * it in the doc2000 driver in August 1999. dwmw2.
2754 nand_reset(chip
, chipnr
);
2756 chip
->select_chip(mtd
, chipnr
);
2758 /* Shift to get page */
2759 page
= (int)(to
>> chip
->page_shift
);
2761 /* Check, if it is write protected */
2762 if (nand_check_wp(mtd
)) {
2763 chip
->select_chip(mtd
, -1);
2767 /* Invalidate the page cache, if we write to the cached page */
2768 if (page
== chip
->pagebuf
)
2771 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2773 if (ops
->mode
== MTD_OPS_RAW
)
2774 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2776 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2778 chip
->select_chip(mtd
, -1);
2783 ops
->oobretlen
= ops
->ooblen
;
2789 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2790 * @mtd: MTD device structure
2791 * @to: offset to write to
2792 * @ops: oob operation description structure
2794 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2795 struct mtd_oob_ops
*ops
)
2797 int ret
= -ENOTSUPP
;
2801 /* Do not allow writes past end of device */
2802 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2803 pr_debug("%s: attempt to write beyond end of device\n",
2808 nand_get_device(mtd
, FL_WRITING
);
2810 switch (ops
->mode
) {
2811 case MTD_OPS_PLACE_OOB
:
2812 case MTD_OPS_AUTO_OOB
:
2821 ret
= nand_do_write_oob(mtd
, to
, ops
);
2823 ret
= nand_do_write_ops(mtd
, to
, ops
);
2826 nand_release_device(mtd
);
2831 * single_erase - [GENERIC] NAND standard block erase command function
2832 * @mtd: MTD device structure
2833 * @page: the page address of the block which will be erased
2835 * Standard erase command for NAND chips. Returns NAND status.
2837 static int single_erase(struct mtd_info
*mtd
, int page
)
2839 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2840 /* Send commands to erase a block */
2841 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2842 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2844 return chip
->waitfunc(mtd
, chip
);
2848 * nand_erase - [MTD Interface] erase block(s)
2849 * @mtd: MTD device structure
2850 * @instr: erase instruction
2852 * Erase one ore more blocks.
2854 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2856 return nand_erase_nand(mtd
, instr
, 0);
2860 * nand_erase_nand - [INTERN] erase block(s)
2861 * @mtd: MTD device structure
2862 * @instr: erase instruction
2863 * @allowbbt: allow erasing the bbt area
2865 * Erase one ore more blocks.
2867 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2870 int page
, status
, pages_per_block
, ret
, chipnr
;
2871 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2874 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2875 __func__
, (unsigned long long)instr
->addr
,
2876 (unsigned long long)instr
->len
);
2878 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2881 /* Grab the lock and see if the device is available */
2882 nand_get_device(mtd
, FL_ERASING
);
2884 /* Shift to get first page */
2885 page
= (int)(instr
->addr
>> chip
->page_shift
);
2886 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2888 /* Calculate pages in each block */
2889 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2891 /* Select the NAND device */
2892 chip
->select_chip(mtd
, chipnr
);
2894 /* Check, if it is write protected */
2895 if (nand_check_wp(mtd
)) {
2896 pr_debug("%s: device is write protected!\n",
2898 instr
->state
= MTD_ERASE_FAILED
;
2902 /* Loop through the pages */
2905 instr
->state
= MTD_ERASING
;
2910 /* Check if we have a bad block, we do not erase bad blocks! */
2911 if (!instr
->scrub
&& nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2912 chip
->page_shift
, allowbbt
)) {
2913 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2915 instr
->state
= MTD_ERASE_FAILED
;
2920 * Invalidate the page cache, if we erase the block which
2921 * contains the current cached page.
2923 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2924 (page
+ pages_per_block
))
2927 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2929 /* See if block erase succeeded */
2930 if (status
& NAND_STATUS_FAIL
) {
2931 pr_debug("%s: failed erase, page 0x%08x\n",
2933 instr
->state
= MTD_ERASE_FAILED
;
2935 ((loff_t
)page
<< chip
->page_shift
);
2939 /* Increment page address and decrement length */
2940 len
-= (1ULL << chip
->phys_erase_shift
);
2941 page
+= pages_per_block
;
2943 /* Check, if we cross a chip boundary */
2944 if (len
&& !(page
& chip
->pagemask
)) {
2946 chip
->select_chip(mtd
, -1);
2947 chip
->select_chip(mtd
, chipnr
);
2950 instr
->state
= MTD_ERASE_DONE
;
2954 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2956 /* Deselect and wake up anyone waiting on the device */
2957 chip
->select_chip(mtd
, -1);
2958 nand_release_device(mtd
);
2960 /* Do call back function */
2962 mtd_erase_callback(instr
);
2964 /* Return more or less happy */
2969 * nand_sync - [MTD Interface] sync
2970 * @mtd: MTD device structure
2972 * Sync is actually a wait for chip ready function.
2974 static void nand_sync(struct mtd_info
*mtd
)
2976 pr_debug("%s: called\n", __func__
);
2978 /* Grab the lock and see if the device is available */
2979 nand_get_device(mtd
, FL_SYNCING
);
2980 /* Release it and go back */
2981 nand_release_device(mtd
);
2985 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2986 * @mtd: MTD device structure
2987 * @offs: offset relative to mtd start
2989 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2991 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2992 int chipnr
= (int)(offs
>> chip
->chip_shift
);
2995 /* Select the NAND device */
2996 nand_get_device(mtd
, FL_READING
);
2997 chip
->select_chip(mtd
, chipnr
);
2999 ret
= nand_block_checkbad(mtd
, offs
, 0);
3001 chip
->select_chip(mtd
, -1);
3002 nand_release_device(mtd
);
3008 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3009 * @mtd: MTD device structure
3010 * @ofs: offset relative to mtd start
3012 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3016 ret
= nand_block_isbad(mtd
, ofs
);
3018 /* If it was bad already, return success and do nothing */
3024 return nand_block_markbad_lowlevel(mtd
, ofs
);
3028 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3029 * @mtd: MTD device structure
3030 * @chip: nand chip info structure
3031 * @addr: feature address.
3032 * @subfeature_param: the subfeature parameters, a four bytes array.
3034 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3035 int addr
, uint8_t *subfeature_param
)
3040 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3041 if (!chip
->onfi_version
||
3042 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3043 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3047 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3048 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3049 chip
->write_byte(mtd
, subfeature_param
[i
]);
3051 status
= chip
->waitfunc(mtd
, chip
);
3052 if (status
& NAND_STATUS_FAIL
)
3058 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3059 * @mtd: MTD device structure
3060 * @chip: nand chip info structure
3061 * @addr: feature address.
3062 * @subfeature_param: the subfeature parameters, a four bytes array.
3064 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3065 int addr
, uint8_t *subfeature_param
)
3069 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3070 if (!chip
->onfi_version
||
3071 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3072 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3076 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3077 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3078 *subfeature_param
++ = chip
->read_byte(mtd
);
3082 /* Set default functions */
3083 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3085 /* check for proper chip_delay setup, set 20us if not */
3086 if (!chip
->chip_delay
)
3087 chip
->chip_delay
= 20;
3089 /* check, if a user supplied command function given */
3090 if (chip
->cmdfunc
== NULL
)
3091 chip
->cmdfunc
= nand_command
;
3093 /* check, if a user supplied wait function given */
3094 if (chip
->waitfunc
== NULL
)
3095 chip
->waitfunc
= nand_wait
;
3097 if (!chip
->select_chip
)
3098 chip
->select_chip
= nand_select_chip
;
3100 /* set for ONFI nand */
3101 if (!chip
->onfi_set_features
)
3102 chip
->onfi_set_features
= nand_onfi_set_features
;
3103 if (!chip
->onfi_get_features
)
3104 chip
->onfi_get_features
= nand_onfi_get_features
;
3106 /* If called twice, pointers that depend on busw may need to be reset */
3107 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3108 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3109 if (!chip
->read_word
)
3110 chip
->read_word
= nand_read_word
;
3111 if (!chip
->block_bad
)
3112 chip
->block_bad
= nand_block_bad
;
3113 if (!chip
->block_markbad
)
3114 chip
->block_markbad
= nand_default_block_markbad
;
3115 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3116 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3117 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3118 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3119 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3120 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3121 if (!chip
->scan_bbt
)
3122 chip
->scan_bbt
= nand_default_bbt
;
3124 if (!chip
->controller
) {
3125 chip
->controller
= &chip
->hwcontrol
;
3126 spin_lock_init(&chip
->controller
->lock
);
3127 init_waitqueue_head(&chip
->controller
->wq
);
3130 if (!chip
->buf_align
)
3131 chip
->buf_align
= 1;
3134 /* Sanitize ONFI strings so we can safely print them */
3135 static void sanitize_string(char *s
, size_t len
)
3139 /* Null terminate */
3142 /* Remove non printable chars */
3143 for (i
= 0; i
< len
- 1; i
++) {
3144 if (s
[i
] < ' ' || s
[i
] > 127)
3148 /* Remove trailing spaces */
3152 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3157 for (i
= 0; i
< 8; i
++)
3158 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3164 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3165 /* Parse the Extended Parameter Page. */
3166 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3167 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3169 struct onfi_ext_param_page
*ep
;
3170 struct onfi_ext_section
*s
;
3171 struct onfi_ext_ecc_info
*ecc
;
3177 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3178 ep
= kmalloc(len
, GFP_KERNEL
);
3182 /* Send our own NAND_CMD_PARAM. */
3183 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3185 /* Use the Change Read Column command to skip the ONFI param pages. */
3186 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3187 sizeof(*p
) * p
->num_of_param_pages
, -1);
3189 /* Read out the Extended Parameter Page. */
3190 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3191 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3192 != le16_to_cpu(ep
->crc
))) {
3193 pr_debug("fail in the CRC.\n");
3198 * Check the signature.
3199 * Do not strictly follow the ONFI spec, maybe changed in future.
3201 if (strncmp((char *)ep
->sig
, "EPPS", 4)) {
3202 pr_debug("The signature is invalid.\n");
3206 /* find the ECC section. */
3207 cursor
= (uint8_t *)(ep
+ 1);
3208 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3209 s
= ep
->sections
+ i
;
3210 if (s
->type
== ONFI_SECTION_TYPE_2
)
3212 cursor
+= s
->length
* 16;
3214 if (i
== ONFI_EXT_SECTION_MAX
) {
3215 pr_debug("We can not find the ECC section.\n");
3219 /* get the info we want. */
3220 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3222 if (!ecc
->codeword_size
) {
3223 pr_debug("Invalid codeword size\n");
3227 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3228 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3236 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3238 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3239 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3241 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3246 * Configure chip properties from Micron vendor-specific ONFI table
3248 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3249 struct nand_onfi_params
*p
)
3251 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3253 if (le16_to_cpu(p
->vendor_revision
) < 1)
3256 chip
->read_retries
= micron
->read_retry_options
;
3257 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3261 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3263 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3266 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3270 /* Try ONFI for unknown chip or LP */
3271 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3272 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3273 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3276 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3277 for (i
= 0; i
< 3; i
++) {
3278 for (j
= 0; j
< sizeof(*p
); j
++)
3279 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3280 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3281 le16_to_cpu(p
->crc
)) {
3287 pr_err("Could not find valid ONFI parameter page; aborting\n");
3292 val
= le16_to_cpu(p
->revision
);
3294 chip
->onfi_version
= 23;
3295 else if (val
& (1 << 4))
3296 chip
->onfi_version
= 22;
3297 else if (val
& (1 << 3))
3298 chip
->onfi_version
= 21;
3299 else if (val
& (1 << 2))
3300 chip
->onfi_version
= 20;
3301 else if (val
& (1 << 1))
3302 chip
->onfi_version
= 10;
3304 if (!chip
->onfi_version
) {
3305 pr_info("unsupported ONFI version: %d\n", val
);
3309 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3310 sanitize_string(p
->model
, sizeof(p
->model
));
3312 mtd
->name
= p
->model
;
3314 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3317 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3318 * (don't ask me who thought of this...). MTD assumes that these
3319 * dimensions will be power-of-2, so just truncate the remaining area.
3321 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3322 mtd
->erasesize
*= mtd
->writesize
;
3324 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3326 /* See erasesize comment */
3327 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3328 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3329 chip
->bits_per_cell
= p
->bits_per_cell
;
3331 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3332 *busw
= NAND_BUSWIDTH_16
;
3336 if (p
->ecc_bits
!= 0xff) {
3337 chip
->ecc_strength_ds
= p
->ecc_bits
;
3338 chip
->ecc_step_ds
= 512;
3339 } else if (chip
->onfi_version
>= 21 &&
3340 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3343 * The nand_flash_detect_ext_param_page() uses the
3344 * Change Read Column command which maybe not supported
3345 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3346 * now. We do not replace user supplied command function.
3348 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3349 chip
->cmdfunc
= nand_command_lp
;
3351 /* The Extended Parameter Page is supported since ONFI 2.1. */
3352 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3353 pr_warn("Failed to detect ONFI extended param page\n");
3355 pr_warn("Could not retrieve ONFI ECC requirements\n");
3358 if (p
->jedec_id
== NAND_MFR_MICRON
)
3359 nand_onfi_detect_micron(chip
, p
);
3364 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3372 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3374 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3377 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3378 struct jedec_ecc_info
*ecc
;
3382 /* Try JEDEC for unknown chip or LP */
3383 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3384 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3385 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3386 chip
->read_byte(mtd
) != 'C')
3389 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3390 for (i
= 0; i
< 3; i
++) {
3391 for (j
= 0; j
< sizeof(*p
); j
++)
3392 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3394 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3395 le16_to_cpu(p
->crc
))
3400 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3405 val
= le16_to_cpu(p
->revision
);
3407 chip
->jedec_version
= 10;
3408 else if (val
& (1 << 1))
3409 chip
->jedec_version
= 1; /* vendor specific version */
3411 if (!chip
->jedec_version
) {
3412 pr_info("unsupported JEDEC version: %d\n", val
);
3416 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3417 sanitize_string(p
->model
, sizeof(p
->model
));
3419 mtd
->name
= p
->model
;
3421 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3423 /* Please reference to the comment for nand_flash_detect_onfi. */
3424 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3425 mtd
->erasesize
*= mtd
->writesize
;
3427 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3429 /* Please reference to the comment for nand_flash_detect_onfi. */
3430 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3431 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3432 chip
->bits_per_cell
= p
->bits_per_cell
;
3434 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3435 *busw
= NAND_BUSWIDTH_16
;
3440 ecc
= &p
->ecc_info
[0];
3442 if (ecc
->codeword_size
>= 9) {
3443 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3444 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3446 pr_warn("Invalid codeword size\n");
3453 * nand_id_has_period - Check if an ID string has a given wraparound period
3454 * @id_data: the ID string
3455 * @arrlen: the length of the @id_data array
3456 * @period: the period of repitition
3458 * Check if an ID string is repeated within a given sequence of bytes at
3459 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3460 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3461 * if the repetition has a period of @period; otherwise, returns zero.
3463 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3466 for (i
= 0; i
< period
; i
++)
3467 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3468 if (id_data
[i
] != id_data
[j
])
3474 * nand_id_len - Get the length of an ID string returned by CMD_READID
3475 * @id_data: the ID string
3476 * @arrlen: the length of the @id_data array
3478 * Returns the length of the ID string, according to known wraparound/trailing
3479 * zero patterns. If no pattern exists, returns the length of the array.
3481 static int nand_id_len(u8
*id_data
, int arrlen
)
3483 int last_nonzero
, period
;
3485 /* Find last non-zero byte */
3486 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3487 if (id_data
[last_nonzero
])
3491 if (last_nonzero
< 0)
3494 /* Calculate wraparound period */
3495 for (period
= 1; period
< arrlen
; period
++)
3496 if (nand_id_has_period(id_data
, arrlen
, period
))
3499 /* There's a repeated pattern */
3500 if (period
< arrlen
)
3503 /* There are trailing zeros */
3504 if (last_nonzero
< arrlen
- 1)
3505 return last_nonzero
+ 1;
3507 /* No pattern detected */
3511 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3512 static int nand_get_bits_per_cell(u8 cellinfo
)
3516 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3517 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3522 * Many new NAND share similar device ID codes, which represent the size of the
3523 * chip. The rest of the parameters must be decoded according to generic or
3524 * manufacturer-specific "extended ID" decoding patterns.
3526 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3527 u8 id_data
[8], int *busw
)
3530 /* The 3rd id byte holds MLC / multichip data */
3531 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3532 /* The 4th id byte is the important one */
3535 id_len
= nand_id_len(id_data
, 8);
3538 * Field definitions are in the following datasheets:
3539 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3540 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3541 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3543 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3544 * ID to decide what to do.
3546 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3547 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3549 mtd
->writesize
= 2048 << (extid
& 0x03);
3552 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3572 default: /* Other cases are "reserved" (unknown) */
3573 mtd
->oobsize
= 1024;
3577 /* Calc blocksize */
3578 mtd
->erasesize
= (128 * 1024) <<
3579 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3581 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3582 !nand_is_slc(chip
)) {
3586 mtd
->writesize
= 2048 << (extid
& 0x03);
3589 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3613 /* Calc blocksize */
3614 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3616 mtd
->erasesize
= (128 * 1024) << tmp
;
3617 else if (tmp
== 0x03)
3618 mtd
->erasesize
= 768 * 1024;
3620 mtd
->erasesize
= (64 * 1024) << tmp
;
3624 mtd
->writesize
= 1024 << (extid
& 0x03);
3627 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3628 (mtd
->writesize
>> 9);
3630 /* Calc blocksize. Blocksize is multiples of 64KiB */
3631 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3633 /* Get buswidth information */
3634 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3637 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3638 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3640 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3642 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3644 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3645 nand_is_slc(chip
) &&
3646 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3647 !(id_data
[4] & 0x80) /* !BENAND */) {
3648 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3655 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3656 * decodes a matching ID table entry and assigns the MTD size parameters for
3659 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3660 struct nand_flash_dev
*type
, u8 id_data
[8],
3663 int maf_id
= id_data
[0];
3665 mtd
->erasesize
= type
->erasesize
;
3666 mtd
->writesize
= type
->pagesize
;
3667 mtd
->oobsize
= mtd
->writesize
/ 32;
3668 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3670 /* All legacy ID NAND are small-page, SLC */
3671 chip
->bits_per_cell
= 1;
3674 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3675 * some Spansion chips have erasesize that conflicts with size
3676 * listed in nand_ids table.
3677 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3679 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3680 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3681 && mtd
->writesize
== 512) {
3682 mtd
->erasesize
= 128 * 1024;
3683 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3688 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3689 * heuristic patterns using various detected parameters (e.g., manufacturer,
3690 * page size, cell-type information).
3692 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3693 struct nand_chip
*chip
, u8 id_data
[8])
3695 int maf_id
= id_data
[0];
3697 /* Set the bad block position */
3698 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3699 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3701 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3704 * Bad block marker is stored in the last page of each block on Samsung
3705 * and Hynix MLC devices; stored in first two pages of each block on
3706 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3707 * AMD/Spansion, and Macronix. All others scan only the first page.
3709 if (!nand_is_slc(chip
) &&
3710 (maf_id
== NAND_MFR_SAMSUNG
||
3711 maf_id
== NAND_MFR_HYNIX
))
3712 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3713 else if ((nand_is_slc(chip
) &&
3714 (maf_id
== NAND_MFR_SAMSUNG
||
3715 maf_id
== NAND_MFR_HYNIX
||
3716 maf_id
== NAND_MFR_TOSHIBA
||
3717 maf_id
== NAND_MFR_AMD
||
3718 maf_id
== NAND_MFR_MACRONIX
)) ||
3719 (mtd
->writesize
== 2048 &&
3720 maf_id
== NAND_MFR_MICRON
))
3721 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3724 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3726 return type
->id_len
;
3729 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3730 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3732 if (!strncmp((char *)type
->id
, (char *)id_data
, type
->id_len
)) {
3733 mtd
->writesize
= type
->pagesize
;
3734 mtd
->erasesize
= type
->erasesize
;
3735 mtd
->oobsize
= type
->oobsize
;
3737 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3738 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3739 chip
->options
|= type
->options
;
3740 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3741 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3742 chip
->onfi_timing_mode_default
=
3743 type
->onfi_timing_mode_default
;
3745 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3748 mtd
->name
= type
->name
;
3756 * Get the flash and manufacturer id and lookup if the type is supported.
3758 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3759 struct nand_chip
*chip
,
3760 int *maf_id
, int *dev_id
,
3761 struct nand_flash_dev
*type
)
3768 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3771 nand_reset(chip
, 0);
3773 /* Select the device */
3774 chip
->select_chip(mtd
, 0);
3776 /* Send the command for reading device ID */
3777 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3779 /* Read manufacturer and device IDs */
3780 *maf_id
= chip
->read_byte(mtd
);
3781 *dev_id
= chip
->read_byte(mtd
);
3784 * Try again to make sure, as some systems the bus-hold or other
3785 * interface concerns can cause random data which looks like a
3786 * possibly credible NAND flash to appear. If the two results do
3787 * not match, ignore the device completely.
3790 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3792 /* Read entire ID string */
3793 for (i
= 0; i
< 8; i
++)
3794 id_data
[i
] = chip
->read_byte(mtd
);
3796 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3797 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3798 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3799 return ERR_PTR(-ENODEV
);
3803 type
= nand_flash_ids
;
3805 for (; type
->name
!= NULL
; type
++) {
3806 if (is_full_id_nand(type
)) {
3807 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3809 } else if (*dev_id
== type
->dev_id
) {
3814 chip
->onfi_version
= 0;
3815 if (!type
->name
|| !type
->pagesize
) {
3816 /* Check if the chip is ONFI compliant */
3817 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3820 /* Check if the chip is JEDEC compliant */
3821 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3826 return ERR_PTR(-ENODEV
);
3829 mtd
->name
= type
->name
;
3831 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3833 if (!type
->pagesize
) {
3834 /* Decode parameters from extended ID */
3835 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3837 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3839 /* Get chip options */
3840 chip
->options
|= type
->options
;
3843 * Check if chip is not a Samsung device. Do not clear the
3844 * options for chips which do not have an extended id.
3846 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3847 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3850 /* Try to identify manufacturer */
3851 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3852 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3856 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3857 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3858 chip
->options
|= busw
;
3859 nand_set_defaults(chip
, busw
);
3860 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3862 * Check, if buswidth is correct. Hardware drivers should set
3865 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3867 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3868 pr_warn("bus width %d instead %d bit\n",
3869 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3871 return ERR_PTR(-EINVAL
);
3874 nand_decode_bbm_options(mtd
, chip
, id_data
);
3876 /* Calculate the address shift from the page size */
3877 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3878 /* Convert chipsize to number of pages per chip -1 */
3879 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3881 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3882 ffs(mtd
->erasesize
) - 1;
3883 if (chip
->chipsize
& 0xffffffff)
3884 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3886 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3887 chip
->chip_shift
+= 32 - 1;
3890 if (chip
->chip_shift
- chip
->page_shift
> 16)
3891 chip
->options
|= NAND_ROW_ADDR_3
;
3893 chip
->badblockbits
= 8;
3894 chip
->erase
= single_erase
;
3896 /* Do not replace user supplied command function! */
3897 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3898 chip
->cmdfunc
= nand_command_lp
;
3900 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3903 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3904 if (chip
->onfi_version
)
3905 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3906 chip
->onfi_params
.model
);
3907 else if (chip
->jedec_version
)
3908 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3909 chip
->jedec_params
.model
);
3911 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3914 if (chip
->jedec_version
)
3915 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3916 chip
->jedec_params
.model
);
3918 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3921 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3925 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3926 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3927 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3931 #if CONFIG_IS_ENABLED(OF_CONTROL)
3932 DECLARE_GLOBAL_DATA_PTR
;
3934 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3936 int ret
, ecc_mode
= -1, ecc_strength
, ecc_step
;
3937 const void *blob
= gd
->fdt_blob
;
3940 ret
= fdtdec_get_int(blob
, node
, "nand-bus-width", -1);
3942 chip
->options
|= NAND_BUSWIDTH_16
;
3944 if (fdtdec_get_bool(blob
, node
, "nand-on-flash-bbt"))
3945 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3947 str
= fdt_getprop(blob
, node
, "nand-ecc-mode", NULL
);
3949 if (!strcmp(str
, "none"))
3950 ecc_mode
= NAND_ECC_NONE
;
3951 else if (!strcmp(str
, "soft"))
3952 ecc_mode
= NAND_ECC_SOFT
;
3953 else if (!strcmp(str
, "hw"))
3954 ecc_mode
= NAND_ECC_HW
;
3955 else if (!strcmp(str
, "hw_syndrome"))
3956 ecc_mode
= NAND_ECC_HW_SYNDROME
;
3957 else if (!strcmp(str
, "hw_oob_first"))
3958 ecc_mode
= NAND_ECC_HW_OOB_FIRST
;
3959 else if (!strcmp(str
, "soft_bch"))
3960 ecc_mode
= NAND_ECC_SOFT_BCH
;
3964 ecc_strength
= fdtdec_get_int(blob
, node
, "nand-ecc-strength", -1);
3965 ecc_step
= fdtdec_get_int(blob
, node
, "nand-ecc-step-size", -1);
3967 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3968 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3969 pr_err("must set both strength and step size in DT\n");
3974 chip
->ecc
.mode
= ecc_mode
;
3976 if (ecc_strength
>= 0)
3977 chip
->ecc
.strength
= ecc_strength
;
3980 chip
->ecc
.size
= ecc_step
;
3982 if (fdt_getprop(blob
, node
, "nand-ecc-maximize", NULL
))
3983 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
3988 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3992 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
3995 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3996 * @mtd: MTD device structure
3997 * @maxchips: number of chips to scan for
3998 * @table: alternative NAND ID table
4000 * This is the first phase of the normal nand_scan() function. It reads the
4001 * flash ID and sets up MTD fields accordingly.
4004 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4005 struct nand_flash_dev
*table
)
4007 int i
, nand_maf_id
, nand_dev_id
;
4008 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4009 struct nand_flash_dev
*type
;
4012 if (chip
->flash_node
) {
4013 ret
= nand_dt_init(mtd
, chip
, chip
->flash_node
);
4018 /* Set the default functions */
4019 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4021 /* Read the flash type */
4022 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4023 &nand_dev_id
, table
);
4026 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4027 pr_warn("No NAND device found\n");
4028 chip
->select_chip(mtd
, -1);
4029 return PTR_ERR(type
);
4032 /* Initialize the ->data_interface field. */
4033 ret
= nand_init_data_interface(chip
);
4038 * Setup the data interface correctly on the chip and controller side.
4039 * This explicit call to nand_setup_data_interface() is only required
4040 * for the first die, because nand_reset() has been called before
4041 * ->data_interface and ->default_onfi_timing_mode were set.
4042 * For the other dies, nand_reset() will automatically switch to the
4045 ret
= nand_setup_data_interface(chip
, 0);
4049 chip
->select_chip(mtd
, -1);
4051 /* Check for a chip array */
4052 for (i
= 1; i
< maxchips
; i
++) {
4053 /* See comment in nand_get_flash_type for reset */
4054 nand_reset(chip
, i
);
4056 chip
->select_chip(mtd
, i
);
4057 /* Send the command for reading device ID */
4058 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4059 /* Read manufacturer and device IDs */
4060 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4061 nand_dev_id
!= chip
->read_byte(mtd
)) {
4062 chip
->select_chip(mtd
, -1);
4065 chip
->select_chip(mtd
, -1);
4070 pr_info("%d chips detected\n", i
);
4073 /* Store the number of chips and calc total size for mtd */
4075 mtd
->size
= i
* chip
->chipsize
;
4079 EXPORT_SYMBOL(nand_scan_ident
);
4082 * nand_check_ecc_caps - check the sanity of preset ECC settings
4083 * @chip: nand chip info structure
4084 * @caps: ECC caps info structure
4085 * @oobavail: OOB size that the ECC engine can use
4087 * When ECC step size and strength are already set, check if they are supported
4088 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4089 * On success, the calculated ECC bytes is set.
4091 int nand_check_ecc_caps(struct nand_chip
*chip
,
4092 const struct nand_ecc_caps
*caps
, int oobavail
)
4094 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4095 const struct nand_ecc_step_info
*stepinfo
;
4096 int preset_step
= chip
->ecc
.size
;
4097 int preset_strength
= chip
->ecc
.strength
;
4098 int nsteps
, ecc_bytes
;
4101 if (WARN_ON(oobavail
< 0))
4104 if (!preset_step
|| !preset_strength
)
4107 nsteps
= mtd
->writesize
/ preset_step
;
4109 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4110 stepinfo
= &caps
->stepinfos
[i
];
4112 if (stepinfo
->stepsize
!= preset_step
)
4115 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4116 if (stepinfo
->strengths
[j
] != preset_strength
)
4119 ecc_bytes
= caps
->calc_ecc_bytes(preset_step
,
4121 if (WARN_ON_ONCE(ecc_bytes
< 0))
4124 if (ecc_bytes
* nsteps
> oobavail
) {
4125 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4126 preset_step
, preset_strength
);
4130 chip
->ecc
.bytes
= ecc_bytes
;
4136 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4137 preset_step
, preset_strength
);
4141 EXPORT_SYMBOL_GPL(nand_check_ecc_caps
);
4144 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4145 * @chip: nand chip info structure
4146 * @caps: ECC engine caps info structure
4147 * @oobavail: OOB size that the ECC engine can use
4149 * If a chip's ECC requirement is provided, try to meet it with the least
4150 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4151 * On success, the chosen ECC settings are set.
4153 int nand_match_ecc_req(struct nand_chip
*chip
,
4154 const struct nand_ecc_caps
*caps
, int oobavail
)
4156 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4157 const struct nand_ecc_step_info
*stepinfo
;
4158 int req_step
= chip
->ecc_step_ds
;
4159 int req_strength
= chip
->ecc_strength_ds
;
4160 int req_corr
, step_size
, strength
, nsteps
, ecc_bytes
, ecc_bytes_total
;
4161 int best_step
, best_strength
, best_ecc_bytes
;
4162 int best_ecc_bytes_total
= INT_MAX
;
4165 if (WARN_ON(oobavail
< 0))
4168 /* No information provided by the NAND chip */
4169 if (!req_step
|| !req_strength
)
4172 /* number of correctable bits the chip requires in a page */
4173 req_corr
= mtd
->writesize
/ req_step
* req_strength
;
4175 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4176 stepinfo
= &caps
->stepinfos
[i
];
4177 step_size
= stepinfo
->stepsize
;
4179 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4180 strength
= stepinfo
->strengths
[j
];
4183 * If both step size and strength are smaller than the
4184 * chip's requirement, it is not easy to compare the
4185 * resulted reliability.
4187 if (step_size
< req_step
&& strength
< req_strength
)
4190 if (mtd
->writesize
% step_size
)
4193 nsteps
= mtd
->writesize
/ step_size
;
4195 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4196 if (WARN_ON_ONCE(ecc_bytes
< 0))
4198 ecc_bytes_total
= ecc_bytes
* nsteps
;
4200 if (ecc_bytes_total
> oobavail
||
4201 strength
* nsteps
< req_corr
)
4205 * We assume the best is to meet the chip's requrement
4206 * with the least number of ECC bytes.
4208 if (ecc_bytes_total
< best_ecc_bytes_total
) {
4209 best_ecc_bytes_total
= ecc_bytes_total
;
4210 best_step
= step_size
;
4211 best_strength
= strength
;
4212 best_ecc_bytes
= ecc_bytes
;
4217 if (best_ecc_bytes_total
== INT_MAX
)
4220 chip
->ecc
.size
= best_step
;
4221 chip
->ecc
.strength
= best_strength
;
4222 chip
->ecc
.bytes
= best_ecc_bytes
;
4226 EXPORT_SYMBOL_GPL(nand_match_ecc_req
);
4229 * nand_maximize_ecc - choose the max ECC strength available
4230 * @chip: nand chip info structure
4231 * @caps: ECC engine caps info structure
4232 * @oobavail: OOB size that the ECC engine can use
4234 * Choose the max ECC strength that is supported on the controller, and can fit
4235 * within the chip's OOB. On success, the chosen ECC settings are set.
4237 int nand_maximize_ecc(struct nand_chip
*chip
,
4238 const struct nand_ecc_caps
*caps
, int oobavail
)
4240 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4241 const struct nand_ecc_step_info
*stepinfo
;
4242 int step_size
, strength
, nsteps
, ecc_bytes
, corr
;
4245 int best_strength
, best_ecc_bytes
;
4248 if (WARN_ON(oobavail
< 0))
4251 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4252 stepinfo
= &caps
->stepinfos
[i
];
4253 step_size
= stepinfo
->stepsize
;
4255 /* If chip->ecc.size is already set, respect it */
4256 if (chip
->ecc
.size
&& step_size
!= chip
->ecc
.size
)
4259 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4260 strength
= stepinfo
->strengths
[j
];
4262 if (mtd
->writesize
% step_size
)
4265 nsteps
= mtd
->writesize
/ step_size
;
4267 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4268 if (WARN_ON_ONCE(ecc_bytes
< 0))
4271 if (ecc_bytes
* nsteps
> oobavail
)
4274 corr
= strength
* nsteps
;
4277 * If the number of correctable bits is the same,
4278 * bigger step_size has more reliability.
4280 if (corr
> best_corr
||
4281 (corr
== best_corr
&& step_size
> best_step
)) {
4283 best_step
= step_size
;
4284 best_strength
= strength
;
4285 best_ecc_bytes
= ecc_bytes
;
4293 chip
->ecc
.size
= best_step
;
4294 chip
->ecc
.strength
= best_strength
;
4295 chip
->ecc
.bytes
= best_ecc_bytes
;
4299 EXPORT_SYMBOL_GPL(nand_maximize_ecc
);
4302 * Check if the chip configuration meet the datasheet requirements.
4304 * If our configuration corrects A bits per B bytes and the minimum
4305 * required correction level is X bits per Y bytes, then we must ensure
4306 * both of the following are true:
4308 * (1) A / B >= X / Y
4311 * Requirement (1) ensures we can correct for the required bitflip density.
4312 * Requirement (2) ensures we can correct even when all bitflips are clumped
4313 * in the same sector.
4315 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4317 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4318 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4321 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4322 /* Not enough information */
4326 * We get the number of corrected bits per page to compare
4327 * the correction density.
4329 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4330 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4332 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4335 static bool invalid_ecc_page_accessors(struct nand_chip
*chip
)
4337 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4339 if (nand_standard_page_accessors(ecc
))
4343 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4344 * controller driver implements all the page accessors because
4345 * default helpers are not suitable when the core does not
4346 * send the READ0/PAGEPROG commands.
4348 return (!ecc
->read_page
|| !ecc
->write_page
||
4349 !ecc
->read_page_raw
|| !ecc
->write_page_raw
||
4350 (NAND_HAS_SUBPAGE_READ(chip
) && !ecc
->read_subpage
) ||
4351 (NAND_HAS_SUBPAGE_WRITE(chip
) && !ecc
->write_subpage
&&
4352 ecc
->hwctl
&& ecc
->calculate
));
4356 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4357 * @mtd: MTD device structure
4359 * This is the second phase of the normal nand_scan() function. It fills out
4360 * all the uninitialized function pointers with the defaults and scans for a
4361 * bad block table if appropriate.
4363 int nand_scan_tail(struct mtd_info
*mtd
)
4366 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4367 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4368 struct nand_buffers
*nbuf
;
4370 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4371 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4372 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
4374 if (invalid_ecc_page_accessors(chip
)) {
4375 pr_err("Invalid ECC page accessors setup\n");
4379 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4380 nbuf
= kzalloc(sizeof(struct nand_buffers
), GFP_KERNEL
);
4381 chip
->buffers
= nbuf
;
4387 /* Set the internal oob buffer location, just after the page data */
4388 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4391 * If no default placement scheme is given, select an appropriate one.
4393 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4394 switch (mtd
->oobsize
) {
4396 ecc
->layout
= &nand_oob_8
;
4399 ecc
->layout
= &nand_oob_16
;
4402 ecc
->layout
= &nand_oob_64
;
4405 ecc
->layout
= &nand_oob_128
;
4408 pr_warn("No oob scheme defined for oobsize %d\n",
4414 if (!chip
->write_page
)
4415 chip
->write_page
= nand_write_page
;
4418 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4419 * selected and we have 256 byte pagesize fallback to software ECC
4422 switch (ecc
->mode
) {
4423 case NAND_ECC_HW_OOB_FIRST
:
4424 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4425 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4426 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4429 if (!ecc
->read_page
)
4430 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4433 /* Use standard hwecc read page function? */
4434 if (!ecc
->read_page
)
4435 ecc
->read_page
= nand_read_page_hwecc
;
4436 if (!ecc
->write_page
)
4437 ecc
->write_page
= nand_write_page_hwecc
;
4438 if (!ecc
->read_page_raw
)
4439 ecc
->read_page_raw
= nand_read_page_raw
;
4440 if (!ecc
->write_page_raw
)
4441 ecc
->write_page_raw
= nand_write_page_raw
;
4443 ecc
->read_oob
= nand_read_oob_std
;
4444 if (!ecc
->write_oob
)
4445 ecc
->write_oob
= nand_write_oob_std
;
4446 if (!ecc
->read_subpage
)
4447 ecc
->read_subpage
= nand_read_subpage
;
4448 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4449 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4451 case NAND_ECC_HW_SYNDROME
:
4452 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4454 ecc
->read_page
== nand_read_page_hwecc
||
4456 ecc
->write_page
== nand_write_page_hwecc
)) {
4457 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4460 /* Use standard syndrome read/write page function? */
4461 if (!ecc
->read_page
)
4462 ecc
->read_page
= nand_read_page_syndrome
;
4463 if (!ecc
->write_page
)
4464 ecc
->write_page
= nand_write_page_syndrome
;
4465 if (!ecc
->read_page_raw
)
4466 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4467 if (!ecc
->write_page_raw
)
4468 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4470 ecc
->read_oob
= nand_read_oob_syndrome
;
4471 if (!ecc
->write_oob
)
4472 ecc
->write_oob
= nand_write_oob_syndrome
;
4474 if (mtd
->writesize
>= ecc
->size
) {
4475 if (!ecc
->strength
) {
4476 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4481 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4482 ecc
->size
, mtd
->writesize
);
4483 ecc
->mode
= NAND_ECC_SOFT
;
4486 ecc
->calculate
= nand_calculate_ecc
;
4487 ecc
->correct
= nand_correct_data
;
4488 ecc
->read_page
= nand_read_page_swecc
;
4489 ecc
->read_subpage
= nand_read_subpage
;
4490 ecc
->write_page
= nand_write_page_swecc
;
4491 ecc
->read_page_raw
= nand_read_page_raw
;
4492 ecc
->write_page_raw
= nand_write_page_raw
;
4493 ecc
->read_oob
= nand_read_oob_std
;
4494 ecc
->write_oob
= nand_write_oob_std
;
4501 case NAND_ECC_SOFT_BCH
:
4502 if (!mtd_nand_has_bch()) {
4503 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4506 ecc
->calculate
= nand_bch_calculate_ecc
;
4507 ecc
->correct
= nand_bch_correct_data
;
4508 ecc
->read_page
= nand_read_page_swecc
;
4509 ecc
->read_subpage
= nand_read_subpage
;
4510 ecc
->write_page
= nand_write_page_swecc
;
4511 ecc
->read_page_raw
= nand_read_page_raw
;
4512 ecc
->write_page_raw
= nand_write_page_raw
;
4513 ecc
->read_oob
= nand_read_oob_std
;
4514 ecc
->write_oob
= nand_write_oob_std
;
4516 * Board driver should supply ecc.size and ecc.strength values
4517 * to select how many bits are correctable. Otherwise, default
4518 * to 4 bits for large page devices.
4520 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4525 /* See nand_bch_init() for details. */
4527 ecc
->priv
= nand_bch_init(mtd
);
4529 pr_warn("BCH ECC initialization failed!\n");
4535 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4536 ecc
->read_page
= nand_read_page_raw
;
4537 ecc
->write_page
= nand_write_page_raw
;
4538 ecc
->read_oob
= nand_read_oob_std
;
4539 ecc
->read_page_raw
= nand_read_page_raw
;
4540 ecc
->write_page_raw
= nand_write_page_raw
;
4541 ecc
->write_oob
= nand_write_oob_std
;
4542 ecc
->size
= mtd
->writesize
;
4548 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4552 /* For many systems, the standard OOB write also works for raw */
4553 if (!ecc
->read_oob_raw
)
4554 ecc
->read_oob_raw
= ecc
->read_oob
;
4555 if (!ecc
->write_oob_raw
)
4556 ecc
->write_oob_raw
= ecc
->write_oob
;
4559 * The number of bytes available for a client to place data into
4560 * the out of band area.
4564 for (i
= 0; ecc
->layout
->oobfree
[i
].length
; i
++)
4565 mtd
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4568 /* ECC sanity check: warn if it's too weak */
4569 if (!nand_ecc_strength_good(mtd
))
4570 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4574 * Set the number of read / write steps for one page depending on ECC
4577 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4578 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4579 pr_warn("Invalid ECC parameters\n");
4582 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4584 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4585 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4586 switch (ecc
->steps
) {
4588 mtd
->subpage_sft
= 1;
4593 mtd
->subpage_sft
= 2;
4597 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4599 /* Initialize state */
4600 chip
->state
= FL_READY
;
4602 /* Invalidate the pagebuffer reference */
4605 /* Large page NAND with SOFT_ECC should support subpage reads */
4606 switch (ecc
->mode
) {
4608 case NAND_ECC_SOFT_BCH
:
4609 if (chip
->page_shift
> 9)
4610 chip
->options
|= NAND_SUBPAGE_READ
;
4617 /* Fill in remaining MTD driver data */
4618 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4619 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4621 mtd
->_erase
= nand_erase
;
4622 mtd
->_read
= nand_read
;
4623 mtd
->_write
= nand_write
;
4624 mtd
->_panic_write
= panic_nand_write
;
4625 mtd
->_read_oob
= nand_read_oob
;
4626 mtd
->_write_oob
= nand_write_oob
;
4627 mtd
->_sync
= nand_sync
;
4629 mtd
->_unlock
= NULL
;
4630 mtd
->_block_isreserved
= nand_block_isreserved
;
4631 mtd
->_block_isbad
= nand_block_isbad
;
4632 mtd
->_block_markbad
= nand_block_markbad
;
4633 mtd
->writebufsize
= mtd
->writesize
;
4635 /* propagate ecc info to mtd_info */
4636 mtd
->ecclayout
= ecc
->layout
;
4637 mtd
->ecc_strength
= ecc
->strength
;
4638 mtd
->ecc_step_size
= ecc
->size
;
4640 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4641 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4644 if (!mtd
->bitflip_threshold
)
4645 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4649 EXPORT_SYMBOL(nand_scan_tail
);
4652 * nand_scan - [NAND Interface] Scan for the NAND device
4653 * @mtd: MTD device structure
4654 * @maxchips: number of chips to scan for
4656 * This fills out all the uninitialized function pointers with the defaults.
4657 * The flash ID is read and the mtd/chip structures are filled with the
4658 * appropriate values.
4660 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4664 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4666 ret
= nand_scan_tail(mtd
);
4669 EXPORT_SYMBOL(nand_scan
);
4671 MODULE_LICENSE("GPL");
4672 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4673 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4674 MODULE_DESCRIPTION("Generic NAND flash driver code");