4 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <spi_flash.h>
14 #include "sf_internal.h"
16 /* Used when the "_ext_id" is two bytes at most */
17 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
19 ((_jedec_id) >> 16) & 0xff, \
20 ((_jedec_id) >> 8) & 0xff, \
22 ((_ext_id) >> 8) & 0xff, \
25 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
26 .sector_size = (_sector_size), \
27 .n_sectors = (_n_sectors), \
31 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
33 ((_jedec_id) >> 16) & 0xff, \
34 ((_jedec_id) >> 8) & 0xff, \
36 ((_ext_id) >> 16) & 0xff, \
37 ((_ext_id) >> 8) & 0xff, \
41 .sector_size = (_sector_size), \
42 .n_sectors = (_n_sectors), \
46 const struct spi_flash_info spi_flash_ids
[] = {
47 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
48 {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K
) },
49 {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K
) },
50 {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K
) },
51 {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K
) },
52 {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K
) },
53 {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K
) },
54 {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K
) },
55 {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K
) },
56 {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K
) },
57 {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K
) },
59 #ifdef CONFIG_SPI_FLASH_EON /* EON */
60 {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) },
61 {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K
) },
62 {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) },
63 {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) },
65 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
66 {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K
) },
67 {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K
) },
69 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
70 {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) },
71 {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) },
72 {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) },
73 {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) },
75 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
76 {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
77 {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
78 {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) },
79 {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) },
80 {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) },
81 {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) },
82 {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
83 {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL
| WR_QPP
) },
84 {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL
| WR_QPP
) },
85 {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL
| WR_QPP
) },
86 {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
87 {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K
) },
88 {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL
| WR_QPP
) },
89 {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL
| WR_QPP
) },
91 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
92 {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) },
93 {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) },
94 {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) },
95 {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) },
96 {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) },
97 {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) },
98 {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL
| WR_QPP
) },
99 {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
100 {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL
| WR_QPP
) },
101 {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL
| WR_QPP
) },
102 {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL
| WR_QPP
) },
103 {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
104 {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL
| WR_QPP
) },
105 {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL
| WR_QPP
| SECT_4K
) },
106 {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL
| WR_QPP
) },
107 {"s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL
| WR_QPP
| SECT_4K
) },
108 {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL
| WR_QPP
) },
109 {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL
| WR_QPP
) },
110 {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL
| WR_QPP
) },
112 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
113 {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) },
114 {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) },
115 {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) },
116 {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) },
117 {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) },
118 {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) },
119 {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD
| RD_DUAL
) },
120 {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) },
121 {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) },
122 {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) },
123 {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K
) },
124 {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K
) },
125 {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL
| WR_QPP
| SECT_4K
) },
126 {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL
| WR_QPP
| SECT_4K
) },
127 {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL
| WR_QPP
| SECT_4K
) },
128 {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL
| WR_QPP
| SECT_4K
) },
129 {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
130 {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
) },
131 {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL
| WR_QPP
| SECT_4K
) },
132 {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL
| WR_QPP
| SECT_4K
) },
133 {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
134 {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
135 {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
136 {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
137 {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
138 {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL
| WR_QPP
| E_FSR
| SECT_4K
) },
139 {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR
| SECT_4K
) },
141 #ifdef CONFIG_SPI_FLASH_SST /* SST */
142 {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K
| SST_WR
) },
143 {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K
| SST_WR
) },
144 {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K
| SST_WR
) },
145 {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K
| SST_WR
) },
146 {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K
) },
147 {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K
| SST_WR
) },
148 {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K
| SST_WR
) },
149 {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K
| SST_WR
) },
150 {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K
| SST_WR
) },
151 {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K
) },
152 {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K
| SST_WR
) },
154 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
155 {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) },
156 {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) },
157 {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) },
158 {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K
) },
159 {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K
) },
160 {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K
) },
161 {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K
) },
162 {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL
| WR_QPP
| SECT_4K
) },
163 {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL
| WR_QPP
| SECT_4K
) },
164 {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL
| WR_QPP
| SECT_4K
) },
165 {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL
| WR_QPP
| SECT_4K
) },
166 {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
| SECT_4K
) },
167 {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL
| WR_QPP
| SECT_4K
) },
168 {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL
| WR_QPP
| SECT_4K
) },
169 {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL
| WR_QPP
| SECT_4K
) },
170 {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL
| WR_QPP
| SECT_4K
) },
171 {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL
| WR_QPP
| SECT_4K
) },
172 {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL
| WR_QPP
| SECT_4K
) },
174 {}, /* Empty entry to terminate the list */
177 * Below paired flash devices has similar spi_flash params.
178 * (s25fl129p_64k, s25fl128s_64k)
179 * (w25q80bl, w25q80bv)
180 * (w25q16cl, w25q16dv)
181 * (w25q32bv, w25q32fv_spi)
182 * (w25q64cv, w25q64fv_spi)
183 * (w25q128bv, w25q128fv_spi)
184 * (w25q32dw, w25q32fv_qpi)
185 * (w25q64dw, w25q64fv_qpi)
186 * (w25q128fw, w25q128fv_qpi)
projects / people / ms / u-boot.git / blob