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Merge git://git.denx.de/u-boot-fsl-qoriq
[people/ms/u-boot.git] / drivers / serial / serial_mxc.c
1 /*
2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <watchdog.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <dm/platform_data/serial_mxc.h>
14 #include <serial.h>
15 #include <linux/compiler.h>
16
17 /* UART Control Register Bit Fields.*/
18 #define URXD_CHARRDY (1<<15)
19 #define URXD_ERR (1<<14)
20 #define URXD_OVRRUN (1<<13)
21 #define URXD_FRMERR (1<<12)
22 #define URXD_BRK (1<<11)
23 #define URXD_PRERR (1<<10)
24 #define URXD_RX_DATA (0xFF)
25 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
26 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
27 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
28 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
30 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
31 #define UCR1_IREN (1<<7) /* Infrared interface enable */
32 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
33 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
34 #define UCR1_SNDBRK (1<<4) /* Send break */
35 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
36 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
37 #define UCR1_DOZE (1<<1) /* Doze */
38 #define UCR1_UARTEN (1<<0) /* UART enabled */
39 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
40 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
41 #define UCR2_CTSC (1<<13) /* CTS pin control */
42 #define UCR2_CTS (1<<12) /* Clear to send */
43 #define UCR2_ESCEN (1<<11) /* Escape enable */
44 #define UCR2_PREN (1<<8) /* Parity enable */
45 #define UCR2_PROE (1<<7) /* Parity odd/even */
46 #define UCR2_STPB (1<<6) /* Stop */
47 #define UCR2_WS (1<<5) /* Word size */
48 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
49 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
50 #define UCR2_RXEN (1<<1) /* Receiver enabled */
51 #define UCR2_SRST (1<<0) /* SW reset */
52 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
53 #define UCR3_PARERREN (1<<12) /* Parity enable */
54 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
55 #define UCR3_DSR (1<<10) /* Data set ready */
56 #define UCR3_DCD (1<<9) /* Data carrier detect */
57 #define UCR3_RI (1<<8) /* Ring indicator */
58 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
59 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
60 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
61 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
62 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
63 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
64 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
65 #define UCR3_BPEN (1<<0) /* Preset registers enable */
66 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
67 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
68 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
69 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
70 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
71 #define UCR4_IRSC (1<<5) /* IR special case */
72 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
73 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
74 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
75 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
76 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
77 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
78 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
79 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
80 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82 #define USR1_RTSS (1<<14) /* RTS pin status */
83 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84 #define USR1_RTSD (1<<12) /* RTS delta */
85 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95 #define USR2_IDLE (1<<12) /* Idle condition */
96 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97 #define USR2_WAKE (1<<7) /* Wake */
98 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99 #define USR2_TXDC (1<<3) /* Transmitter complete */
100 #define USR2_BRCD (1<<2) /* Break condition */
101 #define USR2_ORE (1<<1) /* Overrun error */
102 #define USR2_RDR (1<<0) /* Recv data ready */
103 #define UTS_FRCPERR (1<<13) /* Force parity error */
104 #define UTS_LOOP (1<<12) /* Loop tx and rx */
105 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107 #define UTS_TXFULL (1<<4) /* TxFIFO full */
108 #define UTS_RXFULL (1<<3) /* RxFIFO full */
109 #define UTS_SOFTRST (1<<0) /* Software reset */
110
111 DECLARE_GLOBAL_DATA_PTR;
112
113 #ifndef CONFIG_DM_SERIAL
114
115 #ifndef CONFIG_MXC_UART_BASE
116 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
117 #endif
118
119 #define UART_PHYS CONFIG_MXC_UART_BASE
120
121 #define __REG(x) (*((volatile u32 *)(x)))
122
123 /* Register definitions */
124 #define URXD 0x0 /* Receiver Register */
125 #define UTXD 0x40 /* Transmitter Register */
126 #define UCR1 0x80 /* Control Register 1 */
127 #define UCR2 0x84 /* Control Register 2 */
128 #define UCR3 0x88 /* Control Register 3 */
129 #define UCR4 0x8c /* Control Register 4 */
130 #define UFCR 0x90 /* FIFO Control Register */
131 #define USR1 0x94 /* Status Register 1 */
132 #define USR2 0x98 /* Status Register 2 */
133 #define UESC 0x9c /* Escape Character Register */
134 #define UTIM 0xa0 /* Escape Timer Register */
135 #define UBIR 0xa4 /* BRM Incremental Register */
136 #define UBMR 0xa8 /* BRM Modulator Register */
137 #define UBRC 0xac /* Baud Rate Count Register */
138 #define UTS 0xb4 /* UART Test Register (mx31) */
139
140 #define TXTL 2 /* reset default */
141 #define RXTL 1 /* reset default */
142 #define RFDIV 4 /* divide input clock by 2 */
143
144 static void mxc_serial_setbrg(void)
145 {
146 u32 clk = imx_get_uartclk();
147
148 if (!gd->baudrate)
149 gd->baudrate = CONFIG_BAUDRATE;
150
151 __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
152 | (TXTL << UFCR_TXTL_SHF)
153 | (RXTL << UFCR_RXTL_SHF);
154 __REG(UART_PHYS + UBIR) = 0xf;
155 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
156
157 }
158
159 static int mxc_serial_getc(void)
160 {
161 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
162 WATCHDOG_RESET();
163 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
164 }
165
166 static void mxc_serial_putc(const char c)
167 {
168 /* If \n, also do \r */
169 if (c == '\n')
170 serial_putc('\r');
171
172 __REG(UART_PHYS + UTXD) = c;
173
174 /* wait for transmitter to be ready */
175 while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
176 WATCHDOG_RESET();
177 }
178
179 /*
180 * Test whether a character is in the RX buffer
181 */
182 static int mxc_serial_tstc(void)
183 {
184 /* If receive fifo is empty, return false */
185 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
186 return 0;
187 return 1;
188 }
189
190 /*
191 * Initialise the serial port with the given baudrate. The settings
192 * are always 8 data bits, no parity, 1 stop bit, no start bits.
193 *
194 */
195 static int mxc_serial_init(void)
196 {
197 __REG(UART_PHYS + UCR1) = 0x0;
198 __REG(UART_PHYS + UCR2) = 0x0;
199
200 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
201
202 __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
203 __REG(UART_PHYS + UCR4) = 0x8000;
204 __REG(UART_PHYS + UESC) = 0x002b;
205 __REG(UART_PHYS + UTIM) = 0x0;
206
207 __REG(UART_PHYS + UTS) = 0x0;
208
209 serial_setbrg();
210
211 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
212
213 __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
214
215 return 0;
216 }
217
218 static struct serial_device mxc_serial_drv = {
219 .name = "mxc_serial",
220 .start = mxc_serial_init,
221 .stop = NULL,
222 .setbrg = mxc_serial_setbrg,
223 .putc = mxc_serial_putc,
224 .puts = default_serial_puts,
225 .getc = mxc_serial_getc,
226 .tstc = mxc_serial_tstc,
227 };
228
229 void mxc_serial_initialize(void)
230 {
231 serial_register(&mxc_serial_drv);
232 }
233
234 __weak struct serial_device *default_serial_console(void)
235 {
236 return &mxc_serial_drv;
237 }
238 #endif
239
240 #ifdef CONFIG_DM_SERIAL
241
242 struct mxc_uart {
243 u32 rxd;
244 u32 spare0[15];
245
246 u32 txd;
247 u32 spare1[15];
248
249 u32 cr1;
250 u32 cr2;
251 u32 cr3;
252 u32 cr4;
253
254 u32 fcr;
255 u32 sr1;
256 u32 sr2;
257 u32 esc;
258
259 u32 tim;
260 u32 bir;
261 u32 bmr;
262 u32 brc;
263
264 u32 onems;
265 u32 ts;
266 };
267
268 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
269 {
270 struct mxc_serial_platdata *plat = dev->platdata;
271 struct mxc_uart *const uart = plat->reg;
272 u32 clk = imx_get_uartclk();
273 u32 tmp;
274
275 tmp = 4 << UFCR_RFDIV_SHF;
276 if (plat->use_dte)
277 tmp |= UFCR_DCEDTE;
278 writel(tmp, &uart->fcr);
279
280 writel(0xf, &uart->bir);
281 writel(clk / (2 * baudrate), &uart->bmr);
282
283 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
284 &uart->cr2);
285 writel(UCR1_UARTEN, &uart->cr1);
286
287 return 0;
288 }
289
290 static int mxc_serial_probe(struct udevice *dev)
291 {
292 struct mxc_serial_platdata *plat = dev->platdata;
293 struct mxc_uart *const uart = plat->reg;
294
295 writel(0, &uart->cr1);
296 writel(0, &uart->cr2);
297 while (!(readl(&uart->cr2) & UCR2_SRST));
298 writel(0x704 | UCR3_ADNIMP, &uart->cr3);
299 writel(0x8000, &uart->cr4);
300 writel(0x2b, &uart->esc);
301 writel(0, &uart->tim);
302 writel(0, &uart->ts);
303
304 return 0;
305 }
306
307 static int mxc_serial_getc(struct udevice *dev)
308 {
309 struct mxc_serial_platdata *plat = dev->platdata;
310 struct mxc_uart *const uart = plat->reg;
311
312 if (readl(&uart->ts) & UTS_RXEMPTY)
313 return -EAGAIN;
314
315 return readl(&uart->rxd) & URXD_RX_DATA;
316 }
317
318 static int mxc_serial_putc(struct udevice *dev, const char ch)
319 {
320 struct mxc_serial_platdata *plat = dev->platdata;
321 struct mxc_uart *const uart = plat->reg;
322
323 if (!(readl(&uart->ts) & UTS_TXEMPTY))
324 return -EAGAIN;
325
326 writel(ch, &uart->txd);
327
328 return 0;
329 }
330
331 static int mxc_serial_pending(struct udevice *dev, bool input)
332 {
333 struct mxc_serial_platdata *plat = dev->platdata;
334 struct mxc_uart *const uart = plat->reg;
335 uint32_t sr2 = readl(&uart->sr2);
336
337 if (input)
338 return sr2 & USR2_RDR ? 1 : 0;
339 else
340 return sr2 & USR2_TXDC ? 0 : 1;
341 }
342
343 static const struct dm_serial_ops mxc_serial_ops = {
344 .putc = mxc_serial_putc,
345 .pending = mxc_serial_pending,
346 .getc = mxc_serial_getc,
347 .setbrg = mxc_serial_setbrg,
348 };
349
350 #if CONFIG_IS_ENABLED(OF_CONTROL)
351 static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
352 {
353 struct mxc_serial_platdata *plat = dev->platdata;
354 fdt_addr_t addr;
355
356 addr = devfdt_get_addr(dev);
357 if (addr == FDT_ADDR_T_NONE)
358 return -EINVAL;
359
360 plat->reg = (struct mxc_uart *)addr;
361
362 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
363 "fsl,dte-mode");
364 return 0;
365 }
366
367 static const struct udevice_id mxc_serial_ids[] = {
368 { .compatible = "fsl,imx6ul-uart" },
369 { .compatible = "fsl,imx7d-uart" },
370 { }
371 };
372 #endif
373
374 U_BOOT_DRIVER(serial_mxc) = {
375 .name = "serial_mxc",
376 .id = UCLASS_SERIAL,
377 #if CONFIG_IS_ENABLED(OF_CONTROL)
378 .of_match = mxc_serial_ids,
379 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
380 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
381 #endif
382 .probe = mxc_serial_probe,
383 .ops = &mxc_serial_ops,
384 .flags = DM_FLAG_PRE_RELOC,
385 };
386 #endif
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