drivers/serial/serial_mxc.c

   1 /*
   2  * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/clock.h>
  11 #include <serial.h>
  12 #include <linux/compiler.h>
  13
  14 #define __REG(x)     (*((volatile u32 *)(x)))
  15
  16 #ifndef CONFIG_MXC_UART_BASE
  17 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
  18 #endif
  19
  20 #define UART_PHYS       CONFIG_MXC_UART_BASE
  21
  22 /* Register definitions */
  23 #define URXD  0x0  /* Receiver Register */
  24 #define UTXD  0x40 /* Transmitter Register */
  25 #define UCR1  0x80 /* Control Register 1 */
  26 #define UCR2  0x84 /* Control Register 2 */
  27 #define UCR3  0x88 /* Control Register 3 */
  28 #define UCR4  0x8c /* Control Register 4 */
  29 #define UFCR  0x90 /* FIFO Control Register */
  30 #define USR1  0x94 /* Status Register 1 */
  31 #define USR2  0x98 /* Status Register 2 */
  32 #define UESC  0x9c /* Escape Character Register */
  33 #define UTIM  0xa0 /* Escape Timer Register */
  34 #define UBIR  0xa4 /* BRM Incremental Register */
  35 #define UBMR  0xa8 /* BRM Modulator Register */
  36 #define UBRC  0xac /* Baud Rate Count Register */
  37 #define UTS   0xb4 /* UART Test Register (mx31) */
  38
  39 /* UART Control Register Bit Fields.*/
  40 #define  URXD_CHARRDY    (1<<15)
  41 #define  URXD_ERR        (1<<14)
  42 #define  URXD_OVRRUN     (1<<13)
  43 #define  URXD_FRMERR     (1<<12)
  44 #define  URXD_BRK        (1<<11)
  45 #define  URXD_PRERR      (1<<10)
  46 #define  URXD_RX_DATA    (0xFF)
  47 #define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
  48 #define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  49 #define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  50 #define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  51 #define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  52 #define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  53 #define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
  54 #define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  55 #define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  56 #define  UCR1_SNDBRK     (1<<4)  /* Send break */
  57 #define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  58 #define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
  59 #define  UCR1_DOZE       (1<<1)  /* Doze */
  60 #define  UCR1_UARTEN     (1<<0)  /* UART enabled */
  61 #define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  62 #define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  63 #define  UCR2_CTSC       (1<<13) /* CTS pin control */
  64 #define  UCR2_CTS        (1<<12) /* Clear to send */
  65 #define  UCR2_ESCEN      (1<<11) /* Escape enable */
  66 #define  UCR2_PREN       (1<<8)  /* Parity enable */
  67 #define  UCR2_PROE       (1<<7)  /* Parity odd/even */
  68 #define  UCR2_STPB       (1<<6)  /* Stop */
  69 #define  UCR2_WS         (1<<5)  /* Word size */
  70 #define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  71 #define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  72 #define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
  73 #define  UCR2_SRST       (1<<0)  /* SW reset */
  74 #define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
  75 #define  UCR3_PARERREN   (1<<12) /* Parity enable */
  76 #define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
  77 #define  UCR3_DSR        (1<<10) /* Data set ready */
  78 #define  UCR3_DCD        (1<<9)  /* Data carrier detect */
  79 #define  UCR3_RI         (1<<8)  /* Ring indicator */
  80 #define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
  81 #define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
  82 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
  83 #define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
  84 #define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
  85 #define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
  86 #define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
  87 #define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
  88 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
  89 #define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
  90 #define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
  91 #define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
  92 #define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
  93 #define  UCR4_IRSC       (1<<5)  /* IR special case */
  94 #define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
  95 #define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
  96 #define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
  97 #define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
  98 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
  99 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 100 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 101 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 102 #define  USR1_RTSS       (1<<14) /* RTS pin status */
 103 #define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 104 #define  USR1_RTSD       (1<<12) /* RTS delta */
 105 #define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 106 #define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 107 #define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
 108 #define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
 109 #define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
 110 #define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
 111 #define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
 112 #define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
 113 #define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
 114 #define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
 115 #define  USR2_IDLE       (1<<12) /* Idle condition */
 116 #define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
 117 #define  USR2_WAKE       (1<<7)  /* Wake */
 118 #define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
 119 #define  USR2_TXDC       (1<<3)  /* Transmitter complete */
 120 #define  USR2_BRCD       (1<<2)  /* Break condition */
 121 #define  USR2_ORE        (1<<1)  /* Overrun error */
 122 #define  USR2_RDR        (1<<0)  /* Recv data ready */
 123 #define  UTS_FRCPERR     (1<<13) /* Force parity error */
 124 #define  UTS_LOOP        (1<<12) /* Loop tx and rx */
 125 #define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
 126 #define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
 127 #define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
 128 #define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
 129 #define  UTS_SOFTRST     (1<<0)  /* Software reset */
 130
 131 DECLARE_GLOBAL_DATA_PTR;
 132
 133 static void mxc_serial_setbrg(void)
 134 {
 135         u32 clk = imx_get_uartclk();
 136
 137         if (!gd->baudrate)
 138                 gd->baudrate = CONFIG_BAUDRATE;
 139
 140         __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
 141         __REG(UART_PHYS + UBIR) = 0xf;
 142         __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
 143
 144 }
 145
 146 static int mxc_serial_getc(void)
 147 {
 148         while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
 149                 WATCHDOG_RESET();
 150         return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
 151 }
 152
 153 static void mxc_serial_putc(const char c)
 154 {
 155         __REG(UART_PHYS + UTXD) = c;
 156
 157         /* wait for transmitter to be ready */
 158         while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
 159                 WATCHDOG_RESET();
 160
 161         /* If \n, also do \r */
 162         if (c == '\n')
 163                 serial_putc ('\r');
 164 }
 165
 166 /*
 167  * Test whether a character is in the RX buffer
 168  */
 169 static int mxc_serial_tstc(void)
 170 {
 171         /* If receive fifo is empty, return false */
 172         if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
 173                 return 0;
 174         return 1;
 175 }
 176
 177 /*
 178  * Initialise the serial port with the given baudrate. The settings
 179  * are always 8 data bits, no parity, 1 stop bit, no start bits.
 180  *
 181  */
 182 static int mxc_serial_init(void)
 183 {
 184         __REG(UART_PHYS + UCR1) = 0x0;
 185         __REG(UART_PHYS + UCR2) = 0x0;
 186
 187         while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
 188
 189         __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
 190         __REG(UART_PHYS + UCR4) = 0x8000;
 191         __REG(UART_PHYS + UESC) = 0x002b;
 192         __REG(UART_PHYS + UTIM) = 0x0;
 193
 194         __REG(UART_PHYS + UTS) = 0x0;
 195
 196         serial_setbrg();
 197
 198         __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
 199
 200         __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
 201
 202         return 0;
 203 }
 204
 205 static struct serial_device mxc_serial_drv = {
 206         .name   = "mxc_serial",
 207         .start  = mxc_serial_init,
 208         .stop   = NULL,
 209         .setbrg = mxc_serial_setbrg,
 210         .putc   = mxc_serial_putc,
 211         .puts   = default_serial_puts,
 212         .getc   = mxc_serial_getc,
 213         .tstc   = mxc_serial_tstc,
 214 };
 215
 216 void mxc_serial_initialize(void)
 217 {
 218         serial_register(&mxc_serial_drv);
 219 }
 220
 221 __weak struct serial_device *default_serial_console(void)
 222 {
 223         return &mxc_serial_drv;
 224 }