drivers/video/rockchip/rk_vop.c

   1 /*
   2  * Copyright (c) 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <edid.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <video.h>
  16 #include <asm/gpio.h>
  17 #include <asm/hardware.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/edp_rk3288.h>
  21 #include <asm/arch/vop_rk3288.h>
  22 #include <dm/device-internal.h>
  23 #include <dm/uclass-internal.h>
  24 #include <power/regulator.h>
  25 #include "rk_vop.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 enum vop_pol {
  30         HSYNC_POSITIVE = 0,
  31         VSYNC_POSITIVE = 1,
  32         DEN_NEGATIVE   = 2,
  33         DCLK_INVERT    = 3
  34 };
  35
  36 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
  37                          int fb_bits_per_pixel,
  38                          const struct display_timing *edid)
  39 {
  40         u32 lb_mode;
  41         u32 rgb_mode;
  42         u32 hactive = edid->hactive.typ;
  43         u32 vactive = edid->vactive.typ;
  44
  45         writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
  46                &regs->win0_act_info);
  47
  48         writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
  49                V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
  50                &regs->win0_dsp_st);
  51
  52         writel(V_DSP_WIDTH(hactive - 1) |
  53                 V_DSP_HEIGHT(vactive - 1),
  54                 &regs->win0_dsp_info);
  55
  56         clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  57                         V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
  58
  59         switch (fb_bits_per_pixel) {
  60         case 16:
  61                 rgb_mode = RGB565;
  62                 writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
  63                 break;
  64         case 24:
  65                 rgb_mode = RGB888;
  66                 writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
  67                 break;
  68         case 32:
  69         default:
  70                 rgb_mode = ARGB8888;
  71                 writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
  72                 break;
  73         }
  74
  75         if (hactive > 2560)
  76                 lb_mode = LB_RGB_3840X2;
  77         else if (hactive > 1920)
  78                 lb_mode = LB_RGB_2560X4;
  79         else if (hactive > 1280)
  80                 lb_mode = LB_RGB_1920X5;
  81         else
  82                 lb_mode = LB_RGB_1280X8;
  83
  84         clrsetbits_le32(&regs->win0_ctrl0,
  85                         M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  86                         V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
  87                         V_WIN0_EN(1));
  88
  89         writel(fbbase, &regs->win0_yrgb_mst);
  90         writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  91 }
  92
  93 static void rkvop_set_pin_polarity(struct udevice *dev,
  94                                    enum vop_modes mode, u32 polarity)
  95 {
  96         struct rkvop_driverdata *ops =
  97                 (struct rkvop_driverdata *)dev_get_driver_data(dev);
  98
  99         if (ops->set_pin_polarity)
 100                 ops->set_pin_polarity(dev, mode, polarity);
 101 }
 102
 103 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
 104 {
 105         struct rk_vop_priv *priv = dev_get_priv(dev);
 106         struct rk3288_vop *regs = priv->regs;
 107
 108         /* remove from standby */
 109         clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
 110
 111         switch (mode) {
 112         case VOP_MODE_HDMI:
 113                 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 114                                 V_HDMI_OUT_EN(1));
 115                 break;
 116
 117         case VOP_MODE_EDP:
 118                 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 119                                 V_EDP_OUT_EN(1));
 120                 break;
 121
 122         case VOP_MODE_LVDS:
 123                 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 124                                 V_RGB_OUT_EN(1));
 125                 break;
 126
 127         case VOP_MODE_MIPI:
 128                 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 129                                 V_MIPI_OUT_EN(1));
 130                 break;
 131
 132         default:
 133                 debug("%s: unsupported output mode %x\n", __func__, mode);
 134         }
 135 }
 136
 137 static void rkvop_mode_set(struct udevice *dev,
 138                            const struct display_timing *edid,
 139                            enum vop_modes mode)
 140 {
 141         struct rk_vop_priv *priv = dev_get_priv(dev);
 142         struct rk3288_vop *regs = priv->regs;
 143         struct rkvop_driverdata *data =
 144                 (struct rkvop_driverdata *)dev_get_driver_data(dev);
 145
 146         u32 hactive = edid->hactive.typ;
 147         u32 vactive = edid->vactive.typ;
 148         u32 hsync_len = edid->hsync_len.typ;
 149         u32 hback_porch = edid->hback_porch.typ;
 150         u32 vsync_len = edid->vsync_len.typ;
 151         u32 vback_porch = edid->vback_porch.typ;
 152         u32 hfront_porch = edid->hfront_porch.typ;
 153         u32 vfront_porch = edid->vfront_porch.typ;
 154         int mode_flags;
 155         u32 pin_polarity;
 156
 157         pin_polarity = BIT(DCLK_INVERT);
 158         if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
 159                 pin_polarity |= BIT(HSYNC_POSITIVE);
 160         if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
 161                 pin_polarity |= BIT(VSYNC_POSITIVE);
 162
 163         rkvop_set_pin_polarity(dev, mode, pin_polarity);
 164         rkvop_enable_output(dev, mode);
 165
 166         mode_flags = 0;  /* RGB888 */
 167         if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
 168             (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
 169                 mode_flags = 15;  /* RGBaaa */
 170
 171         clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
 172                         V_DSP_OUT_MODE(mode_flags));
 173
 174         writel(V_HSYNC(hsync_len) |
 175                V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
 176                         &regs->dsp_htotal_hs_end);
 177
 178         writel(V_HEAP(hsync_len + hback_porch + hactive) |
 179                V_HASP(hsync_len + hback_porch),
 180                &regs->dsp_hact_st_end);
 181
 182         writel(V_VSYNC(vsync_len) |
 183                V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
 184                &regs->dsp_vtotal_vs_end);
 185
 186         writel(V_VAEP(vsync_len + vback_porch + vactive)|
 187                V_VASP(vsync_len + vback_porch),
 188                &regs->dsp_vact_st_end);
 189
 190         writel(V_HEAP(hsync_len + hback_porch + hactive) |
 191                V_HASP(hsync_len + hback_porch),
 192                &regs->post_dsp_hact_info);
 193
 194         writel(V_VAEP(vsync_len + vback_porch + vactive)|
 195                V_VASP(vsync_len + vback_porch),
 196                &regs->post_dsp_vact_info);
 197
 198         writel(0x01, &regs->reg_cfg_done); /* enable reg config */
 199 }
 200
 201 /**
 202  * rk_display_init() - Try to enable the given display device
 203  *
 204  * This function performs many steps:
 205  * - Finds the display device being referenced by @ep_node
 206  * - Puts the VOP's ID into its uclass platform data
 207  * - Probes the device to set it up
 208  * - Reads the EDID timing information
 209  * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 210  * - Enables the display (the display device handles this and will do different
 211  *     things depending on the display type)
 212  * - Tells the uclass about the display resolution so that the console will
 213  *     appear correctly
 214  *
 215  * @dev:        VOP device that we want to connect to the display
 216  * @fbbase:     Frame buffer address
 217  * @ep_node:    Device tree node to process - this is the offset of an endpoint
 218  *              node within the VOP's 'port' list.
 219  * @return 0 if OK, -ve if something went wrong
 220  */
 221 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
 222 {
 223         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 224         struct rk_vop_priv *priv = dev_get_priv(dev);
 225         int vop_id, remote_vop_id;
 226         struct rk3288_vop *regs = priv->regs;
 227         struct display_timing timing;
 228         struct udevice *disp;
 229         int ret;
 230         u32 remote_phandle;
 231         struct display_plat *disp_uc_plat;
 232         struct clk clk;
 233         enum video_log2_bpp l2bpp;
 234         ofnode remote;
 235
 236         debug("%s(%s, %lu, %s)\n", __func__,
 237               dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
 238
 239         vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
 240         debug("vop_id=%d\n", vop_id);
 241         ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
 242         if (ret)
 243                 return ret;
 244
 245         remote = ofnode_get_by_phandle(remote_phandle);
 246         if (!ofnode_valid(remote))
 247                 return -EINVAL;
 248         remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
 249         debug("remote vop_id=%d\n", remote_vop_id);
 250
 251         /*
 252          * The remote-endpoint references into a subnode of the encoder
 253          * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
 254          * the following (assume 'hdmi_in_vopl' to be referenced):
 255          *
 256          * hdmi: hdmi@ff940000 {
 257          *   ports {
 258          *     hdmi_in: port {
 259          *       hdmi_in_vopb: endpoint@0 { ... };
 260          *       hdmi_in_vopl: endpoint@1 { ... };
 261          *     }
 262          *   }
 263          * }
 264          *
 265          * The original code had 3 steps of "walking the parent", but
 266          * a much better (as in: less likely to break if the DTS
 267          * changes) way of doing this is to "find the enclosing device
 268          * of UCLASS_DISPLAY".
 269          */
 270         while (ofnode_valid(remote)) {
 271                 remote = ofnode_get_parent(remote);
 272                 if (!ofnode_valid(remote)) {
 273                         debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
 274                               __func__, dev_read_name(dev));
 275                         return -EINVAL;
 276                 }
 277
 278                 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
 279                 if (disp)
 280                         break;
 281         };
 282
 283         disp_uc_plat = dev_get_uclass_platdata(disp);
 284         debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
 285         if (display_in_use(disp)) {
 286                 debug("   - device in use\n");
 287                 return -EBUSY;
 288         }
 289
 290         disp_uc_plat->source_id = remote_vop_id;
 291         disp_uc_plat->src_dev = dev;
 292
 293         ret = device_probe(disp);
 294         if (ret) {
 295                 debug("%s: device '%s' display won't probe (ret=%d)\n",
 296                       __func__, dev->name, ret);
 297                 return ret;
 298         }
 299
 300         ret = display_read_timing(disp, &timing);
 301         if (ret) {
 302                 debug("%s: Failed to read timings\n", __func__);
 303                 return ret;
 304         }
 305
 306         ret = clk_get_by_index(dev, 1, &clk);
 307         if (!ret)
 308                 ret = clk_set_rate(&clk, timing.pixelclock.typ);
 309         if (IS_ERR_VALUE(ret)) {
 310                 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 311                 return ret;
 312         }
 313
 314         /* Set bitwidth for vop display according to vop mode */
 315         switch (vop_id) {
 316         case VOP_MODE_EDP:
 317         case VOP_MODE_LVDS:
 318                 l2bpp = VIDEO_BPP16;
 319                 break;
 320         case VOP_MODE_HDMI:
 321         case VOP_MODE_MIPI:
 322                 l2bpp = VIDEO_BPP32;
 323                 break;
 324         default:
 325                 l2bpp = VIDEO_BPP16;
 326         }
 327
 328         rkvop_mode_set(dev, &timing, vop_id);
 329         rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
 330
 331         ret = display_enable(disp, 1 << l2bpp, &timing);
 332         if (ret)
 333                 return ret;
 334
 335         uc_priv->xsize = timing.hactive.typ;
 336         uc_priv->ysize = timing.vactive.typ;
 337         uc_priv->bpix = l2bpp;
 338         debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
 339
 340         return 0;
 341 }
 342
 343 void rk_vop_probe_regulators(struct udevice *dev,
 344                              const char * const *names, int cnt)
 345 {
 346         int i, ret;
 347         const char *name;
 348         struct udevice *reg;
 349
 350         for (i = 0; i < cnt; ++i) {
 351                 name = names[i];
 352                 debug("%s: probing regulator '%s'\n", dev->name, name);
 353
 354                 ret = regulator_autoset_by_name(name, &reg);
 355                 if (!ret)
 356                         ret = regulator_set_enable(reg, true);
 357         }
 358 }
 359
 360 int rk_vop_probe(struct udevice *dev)
 361 {
 362         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 363         struct rk_vop_priv *priv = dev_get_priv(dev);
 364         int ret = 0;
 365         ofnode port, node;
 366
 367         /* Before relocation we don't need to do anything */
 368         if (!(gd->flags & GD_FLG_RELOC))
 369                 return 0;
 370
 371         priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
 372
 373         /*
 374          * Try all the ports until we find one that works. In practice this
 375          * tries EDP first if available, then HDMI.
 376          *
 377          * Note that rockchip_vop_set_clk() always uses NPLL as the source
 378          * clock so it is currently not possible to use more than one display
 379          * device simultaneously.
 380          */
 381         port = dev_read_subnode(dev, "port");
 382         if (!ofnode_valid(port)) {
 383                 debug("%s(%s): 'port' subnode not found\n",
 384                       __func__, dev_read_name(dev));
 385                 return -EINVAL;
 386         }
 387
 388         for (node = ofnode_first_subnode(port);
 389              ofnode_valid(node);
 390              node = dev_read_next_subnode(node)) {
 391                 ret = rk_display_init(dev, plat->base, node);
 392                 if (ret)
 393                         debug("Device failed: ret=%d\n", ret);
 394                 if (!ret)
 395                         break;
 396         }
 397         video_set_flush_dcache(dev, 1);
 398
 399         return ret;
 400 }
 401
 402 int rk_vop_bind(struct udevice *dev)
 403 {
 404         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 405
 406         plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
 407                           CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
 408
 409         return 0;
 410 }