include/configs/C29XPCIE.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * C29XPCIE board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_C29XPCIE
  15 #define CONFIG_PPC_C29X
  16 #endif
  17
  18 #ifdef CONFIG_SPIFLASH
  19 #define CONFIG_RAMBOOT_SPIFLASH
  20 #define CONFIG_SYS_TEXT_BASE            0x11000000
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  22 #endif
  23
  24 #ifdef CONFIG_NAND
  25 #ifdef CONFIG_TPL_BUILD
  26 #define CONFIG_SPL_NAND_BOOT
  27 #define CONFIG_SPL_FLUSH_IMAGE
  28 #define CONFIG_SPL_NAND_INIT
  29 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
  30 #define CONFIG_SPL_COMMON_INIT_DDR
  31 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  32 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  33 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  34 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  35 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  36 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  37 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  38 #elif defined(CONFIG_SPL_BUILD)
  39 #define CONFIG_SPL_INIT_MINIMAL
  40 #define CONFIG_SPL_NAND_MINIMAL
  41 #define CONFIG_SPL_FLUSH_IMAGE
  42 #define CONFIG_SPL_TEXT_BASE            0xff800000
  43 #define CONFIG_SPL_MAX_SIZE             8192
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  48 #endif
  49 #define CONFIG_SPL_PAD_TO               0x20000
  50 #define CONFIG_TPL_PAD_TO               0x20000
  51 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  52 #define CONFIG_SYS_TEXT_BASE            0x11001000
  53 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  54 #endif
  55
  56 #ifndef CONFIG_SYS_TEXT_BASE
  57 #define CONFIG_SYS_TEXT_BASE            0xeff40000
  58 #endif
  59
  60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  62 #endif
  63
  64 #ifdef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  66 #else
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  68 #endif
  69
  70 #ifdef CONFIG_SPL_BUILD
  71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  72 #endif
  73
  74 /* High Level Configuration Options */
  75 #define CONFIG_BOOKE                    /* BOOKE */
  76 #define CONFIG_E500                     /* BOOKE e500 family */
  77 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  78 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  79 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  80
  81 #ifdef CONFIG_PCI
  82 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  83 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  84 #define CONFIG_PCI_INDIRECT_BRIDGE
  85 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  86 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  87
  88 #define CONFIG_CMD_PCI
  89
  90 /*
  91  * PCI Windows
  92  * Memory space is mapped 1-1, but I/O space must start from 0.
  93  */
  94 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  95 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
  96 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  97 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
  98 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  99 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 100 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 101 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 102 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 103 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 104
 105 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 106
 107 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 108 #define CONFIG_DOS_PARTITION
 109 #endif
 110
 111 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 112 #define CONFIG_TSEC_ENET
 113 #define CONFIG_ENV_OVERWRITE
 114
 115 #define CONFIG_DDR_CLK_FREQ     100000000
 116 #define CONFIG_SYS_CLK_FREQ     66666666
 117
 118 #define CONFIG_HWCONFIG
 119
 120 /*
 121  * These can be toggled for performance analysis, otherwise use default.
 122  */
 123 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 124 #define CONFIG_BTB                      /* toggle branch predition */
 125
 126 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 127
 128 #define CONFIG_ENABLE_36BIT_PHYS
 129
 130 #define CONFIG_ADDR_MAP                 1
 131 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x00200000
 134 #define CONFIG_SYS_MEMTEST_END          0x00400000
 135 #define CONFIG_PANIC_HANG
 136
 137 /* DDR Setup */
 138 #define CONFIG_SYS_FSL_DDR3
 139 #define CONFIG_DDR_SPD
 140 #define CONFIG_SYS_SPD_BUS_NUM          0
 141 #define SPD_EEPROM_ADDRESS              0x50
 142 #define CONFIG_SYS_DDR_RAW_TIMING
 143
 144 /* DDR ECC Setup*/
 145 #define CONFIG_DDR_ECC
 146 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 148
 149 #define CONFIG_SYS_SDRAM_SIZE           512
 150 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 152
 153 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 154 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 155
 156 #define CONFIG_SYS_CCSRBAR              0xffe00000
 157 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 158
 159 /* Platform SRAM setting  */
 160 #define CONFIG_SYS_PLATFORM_SRAM_BASE   0xffb00000
 161 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
 162                         (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 163 #define CONFIG_SYS_PLATFORM_SRAM_SIZE   (512 << 10)
 164
 165 #ifdef CONFIG_SPL_BUILD
 166 #define CONFIG_SYS_NO_FLASH
 167 #endif
 168
 169 /*
 170  * IFC Definitions
 171  */
 172 /* NOR Flash on IFC */
 173 #define CONFIG_SYS_FLASH_BASE           0xec000000
 174 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 175
 176 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 177
 178 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 180
 181 #define CONFIG_SYS_FLASH_QUIET_TEST
 182 #define CONFIG_FLASH_SHOW_PROGRESS      45
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* in ms */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* in ms */
 185
 186 /* 16Bit NOR Flash - S29GL512S10TFI01 */
 187 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 188                                 CSPR_PORT_SIZE_16 | \
 189                                 CSPR_MSEL_NOR | \
 190                                 CSPR_V)
 191 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64*1024*1024)
 192 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 193
 194 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 195                                 FTIM0_NOR_TEADC(0x5) | \
 196                                 FTIM0_NOR_TEAHC(0x5))
 197 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 198                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 199                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 200 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 201                                 FTIM2_NOR_TCH(0x4) | \
 202                                 FTIM2_NOR_TWPH(0x0E) | \
 203                                 FTIM2_NOR_TWP(0x1c))
 204 #define CONFIG_SYS_NOR_FTIM3    0x0
 205
 206 /* CFI for NOR Flash */
 207 #define CONFIG_FLASH_CFI_DRIVER
 208 #define CONFIG_SYS_FLASH_CFI
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
 210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 211
 212 /* NAND Flash on IFC */
 213 #define CONFIG_NAND_FSL_IFC
 214 #define CONFIG_SYS_NAND_BASE            0xff800000
 215 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 216
 217 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 218
 219 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 220 #define CONFIG_CMD_NAND
 221 #define CONFIG_SYS_NAND_BLOCK_SIZE      (1024 * 1024)
 222
 223 /* 8Bit NAND Flash - K9F1G08U0B */
 224 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 225                                 | CSPR_PORT_SIZE_8 \
 226                                 | CSPR_MSEL_NAND \
 227                                 | CSPR_V)
 228 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 229 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280      /* 640b */
 230 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 231                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 232                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 233                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 234                                 | CSOR_NAND_PGS_8K      /* Page Size = 8K */ \
 235                                 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
 236                                 | CSOR_NAND_PB(128))    /*128 Pages Per Block*/
 237 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x01) | \
 238                                 FTIM0_NAND_TWP(0x0c)   | \
 239                                 FTIM0_NAND_TWCHT(0x08) | \
 240                                 FTIM0_NAND_TWH(0x06))
 241 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x28) | \
 242                                 FTIM1_NAND_TWBE(0x1d)  | \
 243                                 FTIM1_NAND_TRR(0x08)   | \
 244                                 FTIM1_NAND_TRP(0x0c))
 245 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x0c) | \
 246                                 FTIM2_NAND_TREH(0x0a) | \
 247                                 FTIM2_NAND_TWHRE(0x18))
 248 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x04))
 249
 250 #define CONFIG_SYS_NAND_DDR_LAW         11
 251
 252 /* Set up IFC registers for boot location NOR/NAND */
 253 #ifdef CONFIG_NAND
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 255 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 256 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 257 #define CONFIG_SYS_CSOR0_EXT            CONFIG_SYS_NAND_OOBSIZE
 258 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 259 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 260 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 261 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 262 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 263 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 264 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 265 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 266 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 267 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 268 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 269 #else
 270 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 278 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 279 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 280 #define CONFIG_SYS_CSOR1_EXT            CONFIG_SYS_NAND_OOBSIZE
 281 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 282 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 283 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 284 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 285 #endif
 286
 287 /* CPLD on IFC, selected by CS2 */
 288 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 289 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull \
 290                                         | CONFIG_SYS_CPLD_BASE)
 291
 292 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 293                                 | CSPR_PORT_SIZE_8 \
 294                                 | CSPR_MSEL_GPCM \
 295                                 | CSPR_V)
 296 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 297 #define CONFIG_SYS_CSOR2        0x0
 298 /* CPLD Timing parameters for IFC CS2 */
 299 #define CONFIG_SYS_CS2_FTIM0    (FTIM0_GPCM_TACSE(0x0e) | \
 300                                 FTIM0_GPCM_TEADC(0x0e) | \
 301                                 FTIM0_GPCM_TEAHC(0x0e))
 302 #define CONFIG_SYS_CS2_FTIM1    (FTIM1_GPCM_TACO(0x0e) | \
 303                                 FTIM1_GPCM_TRAD(0x1f))
 304 #define CONFIG_SYS_CS2_FTIM2    (FTIM2_GPCM_TCS(0x0e) | \
 305                                 FTIM2_GPCM_TCH(0x8) | \
 306                                 FTIM2_GPCM_TWP(0x1f))
 307 #define CONFIG_SYS_CS2_FTIM3    0x0
 308
 309 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 310 #define CONFIG_SYS_RAMBOOT
 311 #define CONFIG_SYS_EXTRA_ENV_RELOC
 312 #endif
 313
 314 #define CONFIG_BOARD_EARLY_INIT_R
 315
 316 #define CONFIG_SYS_INIT_RAM_LOCK
 317 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 318 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 319
 320 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 321                                                 - GENERATED_GBL_DATA_SIZE)
 322 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 323
 324 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 325 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024 * 1024)
 326
 327 /*
 328  * Config the L2 Cache as L2 SRAM
 329  */
 330 #if defined(CONFIG_SPL_BUILD)
 331 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 332 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 333 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 334 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 335 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 336 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 337 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 338 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 339 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 340 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 341 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 342 #elif defined(CONFIG_NAND)
 343 #ifdef CONFIG_TPL_BUILD
 344 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 345 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 346 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 347 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 348 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 349 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 350 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 351 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 352 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 353 #else
 354 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 355 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 356 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 357 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 358 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 359 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 360 #endif
 361 #endif
 362 #endif
 363
 364 /* Serial Port */
 365 #define CONFIG_CONS_INDEX       1
 366 #define CONFIG_SYS_NS16550_SERIAL
 367 #define CONFIG_SYS_NS16550_REG_SIZE     1
 368 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 369
 370 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 371 #define CONFIG_NS16550_MIN_FUNCTIONS
 372 #endif
 373
 374 #define CONFIG_SYS_BAUDRATE_TABLE       \
 375         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 376
 377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 379
 380 #define CONFIG_SYS_I2C
 381 #define CONFIG_SYS_I2C_FSL
 382 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 383 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 384 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 385 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 386 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 387 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 388
 389 /* I2C EEPROM */
 390 /* enable read and write access to EEPROM */
 391 #define CONFIG_CMD_EEPROM
 392 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 393 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 394 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 395
 396 /* eSPI - Enhanced SPI */
 397 #define CONFIG_SF_DEFAULT_SPEED         10000000
 398 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 399
 400 #ifdef CONFIG_TSEC_ENET
 401 #define CONFIG_MII                      /* MII PHY management */
 402 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 403 #define CONFIG_TSEC1            1
 404 #define CONFIG_TSEC1_NAME       "eTSEC1"
 405 #define CONFIG_TSEC2            1
 406 #define CONFIG_TSEC2_NAME       "eTSEC2"
 407
 408 /* Default mode is RGMII mode */
 409 #define TSEC1_PHY_ADDR          0
 410 #define TSEC2_PHY_ADDR          2
 411
 412 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 413 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 414
 415 #define CONFIG_ETHPRIME         "eTSEC1"
 416
 417 #define CONFIG_PHY_GIGE
 418 #endif  /* CONFIG_TSEC_ENET */
 419
 420 /*
 421  * Environment
 422  */
 423 #if defined(CONFIG_SYS_RAMBOOT)
 424 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 425 #define CONFIG_ENV_IS_IN_SPI_FLASH
 426 #define CONFIG_ENV_SPI_BUS      0
 427 #define CONFIG_ENV_SPI_CS       0
 428 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 429 #define CONFIG_ENV_SPI_MODE     0
 430 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 431 #define CONFIG_ENV_SECT_SIZE    0x10000
 432 #define CONFIG_ENV_SIZE         0x2000
 433 #endif
 434 #elif defined(CONFIG_NAND)
 435 #define CONFIG_ENV_IS_IN_NAND
 436 #ifdef CONFIG_TPL_BUILD
 437 #define CONFIG_ENV_SIZE         0x2000
 438 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 439 #else
 440 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 441 #define CONFIG_ENV_RANGE        CONFIG_ENV_SIZE
 442 #endif
 443 #define CONFIG_ENV_OFFSET       CONFIG_SYS_NAND_BLOCK_SIZE
 444 #else
 445 #define CONFIG_ENV_IS_IN_FLASH
 446 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 447 #define CONFIG_ENV_SIZE         0x2000
 448 #define CONFIG_ENV_SECT_SIZE    0x20000
 449 #endif
 450
 451 #define CONFIG_LOADS_ECHO
 452 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 453
 454 /*
 455  * Command line configuration.
 456  */
 457 #define CONFIG_CMD_ERRATA
 458 #define CONFIG_CMD_IRQ
 459 #define CONFIG_CMD_REGINFO
 460
 461 /* Hash command with SHA acceleration supported in hardware */
 462 #ifdef CONFIG_FSL_CAAM
 463 #define CONFIG_CMD_HASH
 464 #define CONFIG_SHA_HW_ACCEL
 465 #endif
 466
 467 /*
 468  * Miscellaneous configurable options
 469  */
 470 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 471 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 472 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 473 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 474
 475 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 476 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 477                                                 /* Print Buffer Size */
 478 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 479 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 480
 481 /*
 482  * For booting Linux, the board info and command line data
 483  * have to be in the first 64 MB of memory, since this is
 484  * the maximum mapped by the Linux kernel during initialization.
 485  */
 486 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 487 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 488
 489 /*
 490  * Environment Configuration
 491  */
 492
 493 #ifdef CONFIG_TSEC_ENET
 494 #define CONFIG_HAS_ETH0
 495 #define CONFIG_HAS_ETH1
 496 #endif
 497
 498 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 499 #define CONFIG_BOOTFILE         "uImage"
 500 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 501
 502 /* default location for tftp and bootm */
 503 #define CONFIG_LOADADDR         1000000
 504
 505
 506 #define CONFIG_BAUDRATE         115200
 507
 508 #define CONFIG_DEF_HWCONFIG     fsl_ddr:ecc=on
 509
 510 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 511         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 512         "netdev=eth0\0"                                         \
 513         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 514         "loadaddr=1000000\0"                            \
 515         "consoledev=ttyS0\0"                            \
 516         "ramdiskaddr=2000000\0"                         \
 517         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 518         "fdtaddr=1e00000\0"                             \
 519         "fdtfile=name/of/device-tree.dtb\0"                     \
 520         "othbootargs=ramdisk_size=600000\0"             \
 521
 522 #define CONFIG_RAMBOOTCOMMAND                   \
 523         "setenv bootargs root=/dev/ram rw "     \
 524         "console=$consoledev,$baudrate $othbootargs; "  \
 525         "tftp $ramdiskaddr $ramdiskfile;"       \
 526         "tftp $loadaddr $bootfile;"             \
 527         "tftp $fdtaddr $fdtfile;"               \
 528         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 529
 530 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 531
 532 #include <asm/fsl_secure_boot.h>
 533
 534 #endif  /* __CONFIG_H */