include/configs/CPCI2DP.h

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26
  27 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  28
  29 #define CONFIG_BAUDRATE         9600
  30
  31 #undef  CONFIG_BOOTARGS
  32 #undef  CONFIG_BOOTCOMMAND
  33
  34 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  35
  36 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  37 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  38
  39 #define CONFIG_MII              1       /* MII PHY management           */
  40 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  41
  42 /*
  43  * BOOTP options
  44  */
  45 #define CONFIG_BOOTP_BOOTFILESIZE
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49
  50 /*
  51  * Command line configuration.
  52  */
  53 #define CONFIG_CMD_PCI
  54 #define CONFIG_CMD_IRQ
  55 #define CONFIG_CMD_BSP
  56 #define CONFIG_CMD_EEPROM
  57
  58 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  59
  60 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  61
  62 /*
  63  * Miscellaneous configurable options
  64  */
  65 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  66
  67 #if defined(CONFIG_CMD_KGDB)
  68 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  69 #else
  70 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  71 #endif
  72 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  73 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  74 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  75
  76 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  77
  78 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  79
  80 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  81
  82 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  83 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  84
  85 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  86 #define CONFIG_SYS_NS16550_SERIAL
  87 #define CONFIG_SYS_NS16550_REG_SIZE     1
  88 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  89
  90 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
  91 #define CONFIG_SYS_BASE_BAUD        691200
  92
  93 /* The following table includes the supported baudrates */
  94 #define CONFIG_SYS_BAUDRATE_TABLE       \
  95         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  96          57600, 115200, 230400, 460800, 921600 }
  97
  98 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  99 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 100
 101 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 102
 103 /*-----------------------------------------------------------------------
 104  * PCI stuff
 105  *-----------------------------------------------------------------------
 106  */
 107 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 108 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 109 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 110
 111 #define CONFIG_PCI                      /* include pci support          */
 112 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 113 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 114 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 115                                         /* resource configuration       */
 116
 117 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 118
 119 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 120
 121 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 122
 123 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 124 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
 125 #define CONFIG_SYS_PCI_CLASSCODE       0x0280   /* PCI Class Code: Network/Other*/
 126
 127 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 128 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 129 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 130 #define CONFIG_SYS_PCI_PTM2LA   0xef000000      /* point to internal regs + PB0/1 */
 131 #define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
 132 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 133
 134 /*-----------------------------------------------------------------------
 135  * Start addresses for the final memory configuration
 136  * (Set up by the startup code)
 137  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 138  */
 139 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 140 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 142 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 143 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 144
 145 /*
 146  * For booting Linux, the board info and command line data
 147  * have to be in the first 8 MB of memory, since this is
 148  * the maximum mapped by the Linux kernel during initialization.
 149  */
 150 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 151 /*-----------------------------------------------------------------------
 152  * FLASH organization
 153  */
 154 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 156
 157 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 158 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 159
 160 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 161 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 162 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 163
 164 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 165 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 166 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 167
 168 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 169
 170 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 171 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 172 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 173
 174 /*-----------------------------------------------------------------------
 175  * I2C EEPROM (CAT24WC16) for environment
 176  */
 177 #define CONFIG_SYS_I2C
 178 #define CONFIG_SYS_I2C_PPC4XX
 179 #define CONFIG_SYS_I2C_PPC4XX_CH0
 180 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 181 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 182
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 185 /* mask of address bits that overflow into the "EEPROM chip address"    */
 186 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 187 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 188                                         /* 16 byte page write mode using*/
 189                                         /* last 4 bits of the address   */
 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 191
 192 #define CONFIG_SYS_EEPROM_WREN         1
 193
 194 /*
 195  * Init Memory Controller:
 196  *
 197  * BR0/1 and OR0/1 (FLASH)
 198  */
 199 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 200 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 201
 202 /*-----------------------------------------------------------------------
 203  * External Bus Controller (EBC) Setup
 204  */
 205
 206 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 207 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 208 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 209
 210 /* Memory Bank 2 (PB0) initialization                                   */
 211 #define CONFIG_SYS_EBC_PB2AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 212 #define CONFIG_SYS_EBC_PB2CR            0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 213
 214 /* Memory Bank 3 (PB1) initialization                           */
 215 #define CONFIG_SYS_EBC_PB3AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 216 #define CONFIG_SYS_EBC_PB3CR            0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
 217
 218 /*-----------------------------------------------------------------------
 219  * Definitions for initial stack pointer and data area (in data cache)
 220  */
 221 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 222
 223 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 224 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 225 #define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 226 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 227
 228 /*-----------------------------------------------------------------------
 229  * GPIO definitions
 230  */
 231 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 13)   /* GPIO13 */
 232 #define CONFIG_SYS_SELF_RST             (0x80000000 >> 14)   /* GPIO14 */
 233 #define CONFIG_SYS_PB_LED               (0x80000000 >> 16)   /* GPIO16 */
 234 #define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 23)   /* GPIO23 */
 235
 236 #endif  /* __CONFIG_H */