include/configs/CPCI4052.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  22 #define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
  23 #undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
  24
  25 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  26 #define CONFIG_DISPLAY_BOARDINFO
  27
  28 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  29 #define CONFIG_MISC_INIT_R       1      /* call misc_init_r()           */
  30
  31 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  32
  33 #define CONFIG_BAUDRATE         9600
  34
  35 #undef  CONFIG_BOOTARGS
  36 #undef  CONFIG_BOOTCOMMAND
  37
  38 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  39
  40 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  41 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  42
  43 #define CONFIG_PPC4xx_EMAC
  44 #define CONFIG_MII              1       /* MII PHY management           */
  45 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  46 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  47 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  48
  49 #undef  CONFIG_HAS_ETH1
  50
  51 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  52
  53 /*
  54  * BOOTP options
  55  */
  56 #define CONFIG_BOOTP_SUBNETMASK
  57 #define CONFIG_BOOTP_GATEWAY
  58 #define CONFIG_BOOTP_HOSTNAME
  59 #define CONFIG_BOOTP_BOOTPATH
  60 #define CONFIG_BOOTP_DNS
  61 #define CONFIG_BOOTP_DNS2
  62 #define CONFIG_BOOTP_SEND_HOSTNAME
  63
  64 /*
  65  * Command line configuration.
  66  */
  67 #define CONFIG_CMD_PCI
  68 #define CONFIG_CMD_IRQ
  69 #define CONFIG_CMD_IDE
  70 #define CONFIG_CMD_DATE
  71 #define CONFIG_CMD_BSP
  72 #define CONFIG_CMD_EEPROM
  73
  74 #define CONFIG_MAC_PARTITION
  75 #define CONFIG_DOS_PARTITION
  76
  77 #define CONFIG_SUPPORT_VFAT
  78
  79 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  80
  81 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #undef CONFIG_SYS_LONGHELP                      /* undef to save memory         */
  87
  88 #if defined(CONFIG_CMD_KGDB)
  89 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  90 #else
  91 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  92 #endif
  93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  94 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  95 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  96
  97 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  98
  99 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 100
 101 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 102
 103 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 104 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 105
 106 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 107 #define CONFIG_SYS_NS16550_SERIAL
 108 #define CONFIG_SYS_NS16550_REG_SIZE     1
 109 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 110
 111 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 112 #define CONFIG_SYS_BASE_BAUD        691200
 113
 114 /* The following table includes the supported baudrates */
 115 #define CONFIG_SYS_BAUDRATE_TABLE       \
 116         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 117          57600, 115200, 230400, 460800, 921600 }
 118
 119 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 120 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 121
 122 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 123
 124 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 125
 126 /*-----------------------------------------------------------------------
 127  * PCI stuff
 128  *-----------------------------------------------------------------------
 129  */
 130 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 131 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 132 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 133
 134 #define CONFIG_PCI                      /* include pci support          */
 135 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 136 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 137 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 138                                         /* resource configuration       */
 139
 140 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 141
 142 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 143
 144 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 145
 146 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 147 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 148 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 149 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 150 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 151 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 152 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 153 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 154 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 155 #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
 156
 157 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 158
 159 /*-----------------------------------------------------------------------
 160  * IDE/ATA stuff
 161  *-----------------------------------------------------------------------
 162  */
 163 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 164 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 165 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 166
 167 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 168 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 169
 170 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 171 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 172
 173 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 174 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 175 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 176
 177 /*-----------------------------------------------------------------------
 178  * Start addresses for the final memory configuration
 179  * (Set up by the startup code)
 180  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 181  */
 182 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 183 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 185 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 186 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 187
 188 #define CONFIG_PRAM             0       /* use pram variable to overwrite */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 202
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 205
 206 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 207 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 208 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 209 /*
 210  * The following defines are added for buggy IOP480 byte interface.
 211  * All other boards should use the standard values (CPCI405 etc.)
 212  */
 213 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 214 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 215 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 216
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 218
 219 #if 0 /* Use NVRAM for environment variables */
 220 /*-----------------------------------------------------------------------
 221  * NVRAM organization
 222  */
 223 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
 224 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars     */
 225 #define CONFIG_ENV_ADDR         \
 226         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))  /* Env  */
 227
 228 #else /* Use EEPROM for environment variables */
 229
 230 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 231 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 232 #define CONFIG_ENV_SIZE         0x800   /* 2048 bytes may be used for env vars*/
 233                                    /* total size of a CAT24WC16 is 2048 bytes */
 234 #endif
 235
 236 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 237 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 238 #define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 239
 240 /*-----------------------------------------------------------------------
 241  * I2C EEPROM (CAT24WC16) for environment
 242  */
 243 #define CONFIG_SYS_I2C
 244 #define CONFIG_SYS_I2C_PPC4XX
 245 #define CONFIG_SYS_I2C_PPC4XX_CH0
 246 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 247 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 248
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 251 /* mask of address bits that overflow into the "EEPROM chip address"    */
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 254                                         /* 16 byte page write mode using*/
 255                                         /* last 4 bits of the address   */
 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 257
 258 /*
 259  * Init Memory Controller:
 260  *
 261  * BR0/1 and OR0/1 (FLASH)
 262  */
 263
 264 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 265 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 266
 267 /*-----------------------------------------------------------------------
 268  * External Bus Controller (EBC) Setup
 269  */
 270
 271 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 272 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 273 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 274
 275 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 276 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 277 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 278
 279 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 280 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 281 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 282 #define CONFIG_SYS_LED_ADDR             0xF0000380
 283
 284 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 285 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 286 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 287
 288 /* Memory Bank 4 (NVRAM/RTC) initialization                                     */
 289 /*#define CONFIG_SYS_EBC_PB4AP            0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
 290 #define CONFIG_SYS_EBC_PB4AP            0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
 291 #define CONFIG_SYS_EBC_PB4CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 292
 293 /* Memory Bank 5 (optional Quart) initialization                                */
 294 #define CONFIG_SYS_EBC_PB5AP            0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 295 #define CONFIG_SYS_EBC_PB5CR            0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 296
 297 /* Memory Bank 6 (FPGA internal) initialization                                 */
 298 #define CONFIG_SYS_EBC_PB6AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 299 #define CONFIG_SYS_EBC_PB6CR            0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 300 #define CONFIG_SYS_FPGA_BASE_ADDR       0xF0400000
 301
 302 /*-----------------------------------------------------------------------
 303  * FPGA stuff
 304  */
 305 /* FPGA internal regs */
 306 #define CONFIG_SYS_FPGA_MODE            0x00
 307 #define CONFIG_SYS_FPGA_STATUS          0x02
 308 #define CONFIG_SYS_FPGA_TS              0x04
 309 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 310 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 311 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 312 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 313 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 314 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 315 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 316 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 317 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 318
 319 /* FPGA Mode Reg */
 320 #define CONFIG_SYS_FPGA_MODE_CF_RESET       0x0001
 321 #define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
 322 #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 323 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 324 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 325 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR       0x2000
 326
 327 /* FPGA Status Reg */
 328 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 329 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 330 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 331 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 332 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 333
 334 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 335 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024     /* 32kByte is enough for XC2S15  */
 336
 337 /* FPGA program pin configuration */
 338 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 339 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 340 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 341 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 342 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 343
 344 /*-----------------------------------------------------------------------
 345  * Definitions for initial stack pointer and data area (in data cache)
 346  */
 347 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 348
 349 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 350 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 351 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 352 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 353
 354 #endif  /* __CONFIG_H */