include/configs/IPHASE4539.h

   1 /*
   2  * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * This file is based on similar values for other boards found in
   5  * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #undef DEBUG                            /* General debug */
  34
  35 /*-----------------------------------------------------------------------
  36  * High Level Configuration Options
  37  * (easy to change)
  38  */
  39
  40 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  41 #define CONFIG_IPHASE4539       1       /* ...on a Interphase 4539 PMC */
  42
  43 /*-----------------------------------------------------------------------
  44  * select serial console configuration
  45  *
  46  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  47  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  48  * for SCC).
  49  *
  50  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  51  * defined elsewhere (for example, on the cogent platform, there are serial
  52  * ports on the motherboard which are used for the serial console - see
  53  * cogent/cma101/serial.[ch]).
  54  */
  55 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  56 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  57 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  58 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  59
  60 /*-----------------------------------------------------------------------
  61  * select ethernet configuration
  62  *
  63  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  64  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  65  * for FCC)
  66  *
  67  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  68  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  69  * from CONFIG_COMMANDS to remove support for networking.
  70  */
  71 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  72 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  73 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  74 #define CONFIG_ETHER_INDEX      3       /* which channel for ether  */
  75
  76 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
  77
  78 /*-----------------------------------------------------------------------
  79  * - Rx-CLK is CLK14
  80  * - Tx-CLK is CLK16
  81  * - Select bus for bd/buffers (see 28-13)
  82  * - Half duplex
  83  */
  84 # define CFG_CMXFCR_MASK        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  85 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  86 # define CFG_CPMFCR_RAMTYPE     0
  87 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  88
  89 #endif  /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  90
  91 /* other options */
  92
  93 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
  94 #define CONFIG_BAUDRATE         19200
  95
  96 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
  97
  98 /*
  99  * select i2c support configuration
 100  *
 101  * Supported configurations are {none, software, hardware} drivers.
 102  * If the software driver is chosen, there are some additional
 103  * configuration items that the driver uses to drive the port pins.
 104  */
 105 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 106 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 107 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 108 #define CFG_I2C_SLAVE           0x7F
 109
 110 /*
 111  * Software (bit-bang) I2C driver configuration
 112  */
 113 #ifdef CONFIG_SOFT_I2C
 114 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 115 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 116 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 117 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 118 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 119                         else    iop->pdat &= ~0x00010000
 120 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 121                         else    iop->pdat &= ~0x00020000
 122 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 123 #endif /* CONFIG_SOFT_I2C */
 124
 125 #define CONFIG_COMMANDS         CONFIG_CMD_DFL
 126
 127 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 128 #include <cmd_confdefs.h>
 129
 130
 131 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 132 #define CONFIG_BOOTCOMMAND      "bootm 100000"  /* autoboot command */
 133 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 134
 135 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 136 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 137 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 138 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 139 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 140 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 141 #endif
 142
 143 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 144
 145 /*-----------------------------------------------------------------------
 146  * Miscellaneous configurable options
 147  */
 148 #define CFG_LONGHELP                    /* undef to save memory         */
 149 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 150 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 151 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 152 #else
 153 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 154 #endif
 155 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
 156 #define CFG_MAXARGS     16              /* max number of command args   */
 157 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 158
 159 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 160 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15 MB in DRAM  */
 161
 162 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passed to Linux in MHz */
 163                                         /* for versions < 2.4.5-pre5     */
 164
 165 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 166
 167 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 168
 169 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 170
 171 #define CFG_RESET_ADDRESS       0x04400000
 172
 173 #define CONFIG_MISC_INIT_R      1       /* We need misc_init_r()        */
 174
 175 /*-----------------------------------------------------------------------
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 181
 182 /*-----------------------------------------------------------------------
 183  * Start addresses for the final memory configuration (Setup by the
 184  * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
 185  */
 186 #define CFG_SDRAM_BASE          0x00000000
 187 #define CFG_FLASH_BASE          0xFF800000
 188
 189 #define CFG_MONITOR_BASE        TEXT_BASE
 190 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor  */
 191 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc() */
 192
 193 /*-----------------------------------------------------------------------
 194  * FLASH organization
 195  */
 196 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 197 #define CFG_MAX_FLASH_SECT      64      /* max num of sects on one chip */
 198 #define CFG_MAX_FLASH_SIZE      (CFG_MAX_FLASH_SECT * 0x10000)  /* 4 MB */
 199
 200 #define CFG_FLASH_ERASE_TOUT    2400000 /* Flash Erase Timeout (in ms)  */
 201 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 202
 203 /* Environment in FLASH, there is little space left in Serial EEPROM */
 204 #define CFG_ENV_IS_IN_FLASH     1
 205 #define CFG_ENV_SECT_SIZE       0x10000 /* We use one complete sector   */
 206 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x10000) /* 2. sector */
 207
 208
 209 /*-----------------------------------------------------------------------
 210  * Hard Reset Configuration Words
 211  *
 212  * if you change bits in the HRCW, you must also change the CFG_*
 213  * defines for the various registers affected by the HRCW e.g. changing
 214  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 215  */
 216 #define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )             |\
 217                           ( HRCW_L2CPC10 | HRCW_ISB110 )        |\
 218                           ( HRCW_MMR11 | HRCW_APPC10 )          |\
 219                           ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )   \
 220                         ) /* 0x14863245 */
 221
 222 /* no slaves */
 223 #define CFG_HRCW_SLAVE1 0
 224 #define CFG_HRCW_SLAVE2 0
 225 #define CFG_HRCW_SLAVE3 0
 226 #define CFG_HRCW_SLAVE4 0
 227 #define CFG_HRCW_SLAVE5 0
 228 #define CFG_HRCW_SLAVE6 0
 229 #define CFG_HRCW_SLAVE7 0
 230
 231 /*-----------------------------------------------------------------------
 232  * Internal Memory Mapped Register
 233  */
 234 #define CFG_IMMR                0xFF000000 /* We keep original value */
 235
 236 /*-----------------------------------------------------------------------
 237  * Definitions for initial stack pointer and data area (in DPRAM)
 238  */
 239 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 240 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 241 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 242 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 243 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 244
 245 /*-----------------------------------------------------------------------
 246  * Internal Definitions
 247  *
 248  * Boot Flags
 249  */
 250 #define BOOTFLAG_COLD   0x01      /* Normal Power-On: Boot from FLASH   */
 251 #define BOOTFLAG_WARM   0x02      /* Software reboot                    */
 252
 253
 254 /*-----------------------------------------------------------------------
 255  * Cache Configuration
 256  */
 257 #define CFG_CACHELINE_SIZE      32     /* For MPC8260 CPU               */
 258 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 259 # define CFG_CACHELINE_SHIFT    5      /* log base 2 of the above value */
 260 #endif
 261
 262 /*-----------------------------------------------------------------------
 263  * HIDx - Hardware Implementation-dependent Registers           2-11
 264  *-----------------------------------------------------------------------
 265  * HID0 also contains cache control.
 266  *
 267  * HID1 has only read-only information - nothing to set.
 268  */
 269 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 270                          HID0_IFEM|HID0_ABE)
 271 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 272 #define CFG_HID2        0
 273
 274 /*-----------------------------------------------------------------------
 275  * RMR - Reset Mode Register                                     5-5
 276  *-----------------------------------------------------------------------
 277  * turn on Checkstop Reset Enable
 278  */
 279 #define CFG_RMR         RMR_CSRE
 280
 281 /*-----------------------------------------------------------------------
 282  * BCR - Bus Configuration                                       4-25
 283  *-----------------------------------------------------------------------
 284  */
 285 #define CFG_BCR         0xA01C0000
 286
 287 /*-----------------------------------------------------------------------
 288  * SIUMCR - SIU Module Configuration                             4-31
 289  *-----------------------------------------------------------------------
 290  */
 291 #define CFG_SIUMCR      0X4205C000
 292
 293 /*-----------------------------------------------------------------------
 294  * SYPCR - System Protection Control                             4-35
 295  * SYPCR can only be written once after reset!
 296  *-----------------------------------------------------------------------
 297  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 298  */
 299 #if defined (CONFIG_WATCHDOG)
 300 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 301                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 302 #else
 303 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 304                          SYPCR_SWRI|SYPCR_SWP)
 305 #endif /* CONFIG_WATCHDOG */
 306
 307 /*-----------------------------------------------------------------------
 308  * TMCNTSC - Time Counter Status and Control                     4-40
 309  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 310  * and enable Time Counter
 311  *-----------------------------------------------------------------------
 312  */
 313 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 314
 315 /*-----------------------------------------------------------------------
 316  * PISCR - Periodic Interrupt Status and Control                 4-42
 317  *-----------------------------------------------------------------------
 318  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 319  * Periodic timer
 320  */
 321 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 322
 323 /*-----------------------------------------------------------------------
 324  * SCCR - System Clock Control                                   9-8
 325  *-----------------------------------------------------------------------
 326  * Ensure DFBRG is Divide by 16
 327  */
 328 #define CFG_SCCR        0
 329
 330 /*-----------------------------------------------------------------------
 331  * RCCR - RISC Controller Configuration                         13-7
 332  *-----------------------------------------------------------------------
 333  */
 334 #define CFG_RCCR        0
 335
 336 /*-----------------------------------------------------------------------
 337  * Init Memory Controller:
 338  *
 339  * Bank Bus     Machine PortSz  Device
 340  * ---- ---     ------- ------  ------
 341  *  0   60x     GPCM    64 bit  FLASH
 342  *  1   60x     SDRAM   64 bit  SDRAM
 343  */
 344
 345 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
 346 #define CFG_OR0_PRELIM  0xFF800882
 347 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
 348 #define CFG_OR1_PRELIM  0xF8002CD0
 349
 350 #define CFG_PSDMR       0x404A241A
 351 #define CFG_MPTPR       0x00007400
 352 #define CFG_PSRT        0x00000007
 353
 354 #endif /* __CONFIG_H */