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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/M54418TWR.h
2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54418TWR /* M54418TWR board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_BAUDRATE 115200
26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
28 #undef CONFIG_WATCHDOG
30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 #define CONFIG_BOOTP_BOOTFILESIZE
36 #define CONFIG_BOOTP_BOOTPATH
37 #define CONFIG_BOOTP_GATEWAY
38 #define CONFIG_BOOTP_HOSTNAME
40 /* Command line configuration */
41 #define CONFIG_CMD_CACHE
42 #undef CONFIG_CMD_DATE
43 #define CONFIG_CMD_DHCP
45 #undef CONFIG_CMD_JFFS2
47 #define CONFIG_CMD_MII
48 #undef CONFIG_CMD_NAND
49 #define CONFIG_CMD_PING
50 #define CONFIG_CMD_REGINFO
51 #define CONFIG_CMD_SPI
58 #ifdef CONFIG_CMD_NAND
59 #define CONFIG_JFFS2_NAND
60 #define CONFIG_NAND_FSL_NFC
61 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
62 #define CONFIG_SYS_MAX_NAND_DEVICE 1
63 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
64 #define CONFIG_SYS_NAND_SELECT_DEVICE
67 /* Network configuration */
71 #define CONFIG_MII_INIT 1
72 #define CONFIG_SYS_DISCOVER_PHY
73 #define CONFIG_SYS_RX_ETH_BUFFER 2
74 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
75 #define CONFIG_SYS_TX_ETH_BUFFER 2
76 #define CONFIG_HAS_ETH1
78 #define CONFIG_SYS_FEC0_PINMUX 0
79 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
80 #define CONFIG_SYS_FEC1_PINMUX 0
81 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
82 #define MCFFEC_TOUT_LOOP 50000
83 #define CONFIG_SYS_FEC0_PHYADDR 0
84 #define CONFIG_SYS_FEC1_PHYADDR 1
86 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
88 #ifdef CONFIG_SYS_NAND_BOOT
89 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
90 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
91 "-(jffs2) console=ttyS0,115200"
93 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
94 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
95 __stringify(CONFIG_IPADDR) " ip=" \
96 __stringify(CONFIG_IPADDR) ":" \
97 __stringify(CONFIG_SERVERIP)":" \
98 __stringify(CONFIG_GATEWAYIP)": " \
99 __stringify(CONFIG_NETMASK) \
100 "::eth0:off:rw console=ttyS0,115200"
103 #define CONFIG_ETHPRIME "FEC0"
104 #define CONFIG_IPADDR 192.168.1.2
105 #define CONFIG_NETMASK 255.255.255.0
106 #define CONFIG_SERVERIP 192.168.1.1
107 #define CONFIG_GATEWAYIP 192.168.1.1
109 #define CONFIG_SYS_FEC_BUF_USE_SRAM
110 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
111 #ifndef CONFIG_SYS_DISCOVER_PHY
112 #define FECDUPLEX FULL
113 #define FECSPEED _100BASET
117 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
118 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
120 #endif /* CONFIG_SYS_DISCOVER_PHY */
123 #define CONFIG_HOSTNAME M54418TWR
125 #if defined(CONFIG_CF_SBF)
126 /* ST Micro serial flash */
127 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
128 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
131 "loadaddr=0x40010000\0" \
132 "sbfhdr=sbfhdr.bin\0" \
133 "uboot=u-boot.bin\0" \
134 "load=tftp ${loadaddr} ${sbfhdr};" \
135 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
136 "upd=run load; run prog\0" \
137 "prog=sf probe 0:1 1000000 3;" \
138 "sf erase 0 40000;" \
139 "sf write ${loadaddr} 0 40000;" \
142 #elif defined(CONFIG_SYS_NAND_BOOT)
143 #define CONFIG_EXTRA_ENV_SETTINGS \
145 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
146 "loadaddr=0x40010000\0" \
147 "u-boot=u-boot.bin\0" \
148 "load=tftp ${loadaddr} ${u-boot};\0" \
149 "upd=run load; run prog\0" \
150 "prog=nand device 0;" \
151 "nand erase 0 40000;" \
152 "nb_update ${loadaddr} ${filesize};" \
156 #define CONFIG_SYS_UBOOT_END 0x3FFFF
157 #define CONFIG_EXTRA_ENV_SETTINGS \
159 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
160 "loadaddr=40010000\0" \
161 "u-boot=u-boot.bin\0" \
162 "load=tftp ${loadaddr) ${u-boot}\0" \
163 "upd=run load; run prog\0" \
164 "prog=prot off mram" " ;" \
165 "cp.b ${loadaddr} 0 ${filesize};" \
172 #define CONFIG_RTC_MCFRRTC
173 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
176 #define CONFIG_MCFTMR
180 #undef CONFIG_SYS_FSL_I2C
181 #undef CONFIG_HARD_I2C /* I2C with hardware support */
182 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
183 /* I2C speed and slave address */
184 #define CONFIG_SYS_I2C_SPEED 80000
185 #define CONFIG_SYS_I2C_SLAVE 0x7F
186 #define CONFIG_SYS_I2C_OFFSET 0x58000
187 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
189 /* DSPI and Serial Flash */
190 #define CONFIG_CF_SPI
191 #define CONFIG_CF_DSPI
192 #define CONFIG_SERIAL_FLASH
193 #define CONFIG_HARD_SPI
194 #define CONFIG_SYS_SBFHDR_SIZE 0x7
195 #ifdef CONFIG_CMD_SPI
197 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
198 DSPI_CTAR_PCSSCK_1CLK | \
199 DSPI_CTAR_PASC(0) | \
201 DSPI_CTAR_CSSCK(0) | \
204 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
205 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
208 /* Input, PCI, Flexbus, and VCO */
209 #define CONFIG_EXTRA_CLOCK
211 #define CONFIG_PRAM 2048 /* 2048 KB */
213 #define CONFIG_SYS_LONGHELP /* undef to save memory */
215 #if defined(CONFIG_CMD_KGDB)
216 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
218 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
220 /* Print Buffer Size */
221 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
222 sizeof(CONFIG_SYS_PROMPT) + 16)
223 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
224 /* Boot Argument Buffer Size */
225 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
227 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
229 #define CONFIG_SYS_MBAR 0xFC000000
232 * Low Level Configuration Settings
233 * (address mappings, register initial values, etc.)
234 * You should know what you are doing if you make changes here.
237 /*-----------------------------------------------------------------------
238 * Definitions for initial stack pointer and data area (in DPRAM)
240 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
241 /* End of used area in internal SRAM */
242 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
243 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
244 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
245 GENERATED_GBL_DATA_SIZE) - 32)
246 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
247 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
249 /*-----------------------------------------------------------------------
250 * Start addresses for the final memory configuration
251 * (Set up by the startup code)
252 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
254 #define CONFIG_SYS_SDRAM_BASE 0x40000000
255 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
257 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
258 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
259 #define CONFIG_SYS_DRAM_TEST
261 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
262 #define CONFIG_SERIAL_BOOT
265 #if defined(CONFIG_SERIAL_BOOT)
266 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
268 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
271 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
272 /* Reserve 256 kB for Monitor */
273 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
274 /* Reserve 256 kB for malloc() */
275 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
278 * For booting Linux, the board info and command line data
279 * have to be in the first 8 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization ??
282 /* Initial Memory map for Linux */
283 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
284 (CONFIG_SYS_SDRAM_SIZE << 20))
286 /* Configuration for environment
287 * Environment is embedded in u-boot in the second sector of the flash
289 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
290 #define CONFIG_SYS_NO_FLASH
291 #define CONFIG_ENV_IS_IN_MRAM 1
292 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
293 #define CONFIG_ENV_SIZE 0x1000
296 #if defined(CONFIG_CF_SBF)
297 #define CONFIG_SYS_NO_FLASH
298 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
299 #define CONFIG_ENV_SPI_CS 1
300 #define CONFIG_ENV_OFFSET 0x40000
301 #define CONFIG_ENV_SIZE 0x2000
302 #define CONFIG_ENV_SECT_SIZE 0x10000
304 #if defined(CONFIG_SYS_NAND_BOOT)
305 #define CONFIG_SYS_NO_FLASH
306 #define CONFIG_ENV_IS_NOWHERE
307 #define CONFIG_ENV_OFFSET 0x80000
308 #define CONFIG_ENV_SIZE 0x20000
309 #define CONFIG_ENV_SECT_SIZE 0x20000
311 #undef CONFIG_ENV_OVERWRITE
313 /* FLASH organization */
314 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
316 #undef CONFIG_SYS_FLASH_CFI
317 #ifdef CONFIG_SYS_FLASH_CFI
319 #define CONFIG_FLASH_CFI_DRIVER 1
320 /* Max size that the board might have */
321 #define CONFIG_SYS_FLASH_SIZE 0x1000000
322 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
323 /* max number of memory banks */
324 #define CONFIG_SYS_MAX_FLASH_BANKS 1
325 /* max number of sectors on one chip */
326 #define CONFIG_SYS_MAX_FLASH_SECT 270
327 /* "Real" (hardware) sectors protection */
328 #define CONFIG_SYS_FLASH_PROTECTION
329 #define CONFIG_SYS_FLASH_CHECKSUM
330 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
332 /* max number of sectors on one chip */
333 #define CONFIG_SYS_MAX_FLASH_SECT 270
334 /* max number of sectors on one chip */
335 #define CONFIG_SYS_MAX_FLASH_BANKS 0
339 * This is setting for JFFS2 support in u-boot.
340 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
342 #ifdef CONFIG_CMD_JFFS2
343 #define CONFIG_JFFS2_DEV "nand0"
344 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
345 #define CONFIG_CMD_MTDPARTS
346 #define CONFIG_MTD_DEVICE
347 #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
349 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
355 #ifdef CONFIG_CMD_UBI
356 #define CONFIG_CMD_MTDPARTS
357 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
358 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
359 #define CONFIG_RBTREE
360 #define MTDIDS_DEFAULT "nand0=NAND"
361 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
364 /* Cache Configuration */
365 #define CONFIG_SYS_CACHELINE_SIZE 16
366 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
367 CONFIG_SYS_INIT_RAM_SIZE - 8)
368 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
369 CONFIG_SYS_INIT_RAM_SIZE - 4)
370 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
371 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
372 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
373 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
374 CF_ACR_EN | CF_ACR_SM_ALL)
375 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
376 CF_CACR_ICINVA | CF_CACR_EUSP)
377 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
378 CF_CACR_DEC | CF_CACR_DDCM_P | \
379 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
381 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
382 CONFIG_SYS_INIT_RAM_SIZE - 12)
384 /*-----------------------------------------------------------------------
385 * Memory bank definitions
388 * CS0 - NOR Flash 16MB
397 #define CONFIG_SYS_CS0_BASE 0x00000000
398 #define CONFIG_SYS_CS0_MASK 0x000F0101
399 #define CONFIG_SYS_CS0_CTRL 0x00001D60
401 #endif /* _M54418TWR_H */