include/configs/M54418TWR.h

   1 /*
   2  * Configuation settings for the Freescale MCF54418 TWR board.
   3  *
   4  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54418TWR_H
  15 #define _M54418TWR_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  25
  26 #define LDS_BOARD_TEXT                  board/freescale/m54418twr/sbf_dram_init.o (.text*)
  27
  28 #undef CONFIG_WATCHDOG
  29
  30 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  31
  32 /*
  33  * BOOTP options
  34  */
  35 #define CONFIG_BOOTP_BOOTFILESIZE
  36
  37 /*
  38  * NAND FLASH
  39  */
  40 #ifdef CONFIG_CMD_NAND
  41 #define CONFIG_JFFS2_NAND
  42 #define CONFIG_NAND_FSL_NFC
  43 #define CONFIG_SYS_NAND_BASE            0xFC0FC000
  44 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  45 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
  46 #define CONFIG_SYS_NAND_SELECT_DEVICE
  47 #endif
  48
  49 /* Network configuration */
  50 #define CONFIG_MCFFEC
  51 #ifdef CONFIG_MCFFEC
  52 #define CONFIG_MII                      1
  53 #define CONFIG_MII_INIT         1
  54 #define CONFIG_SYS_DISCOVER_PHY
  55 #define CONFIG_SYS_RX_ETH_BUFFER        2
  56 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  57 #define CONFIG_SYS_TX_ETH_BUFFER        2
  58 #define CONFIG_HAS_ETH1
  59
  60 #define CONFIG_SYS_FEC0_PINMUX          0
  61 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  62 #define CONFIG_SYS_FEC1_PINMUX          0
  63 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  64 #define MCFFEC_TOUT_LOOP                50000
  65 #define CONFIG_SYS_FEC0_PHYADDR 0
  66 #define CONFIG_SYS_FEC1_PHYADDR 1
  67
  68 #define CONFIG_ETHPRIME "FEC0"
  69 #define CONFIG_IPADDR           192.168.1.2
  70 #define CONFIG_NETMASK          255.255.255.0
  71 #define CONFIG_SERVERIP 192.168.1.1
  72 #define CONFIG_GATEWAYIP        192.168.1.1
  73
  74 #define CONFIG_SYS_FEC_BUF_USE_SRAM
  75 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  76 #ifndef CONFIG_SYS_DISCOVER_PHY
  77 #define FECDUPLEX       FULL
  78 #define FECSPEED        _100BASET
  79 #define LINKSTATUS      1
  80 #else
  81 #define LINKSTATUS      0
  82 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  83 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  84 #endif
  85 #endif                  /* CONFIG_SYS_DISCOVER_PHY */
  86 #endif
  87
  88 #define CONFIG_HOSTNAME         M54418TWR
  89
  90 #if defined(CONFIG_CF_SBF)
  91 /* ST Micro serial flash */
  92 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  93 #define CONFIG_EXTRA_ENV_SETTINGS               \
  94         "netdev=eth0\0"                         \
  95         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  96         "loadaddr=0x40010000\0"                 \
  97         "sbfhdr=sbfhdr.bin\0"                   \
  98         "uboot=u-boot.bin\0"                    \
  99         "load=tftp ${loadaddr} ${sbfhdr};"      \
 100         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 101         "upd=run load; run prog\0"              \
 102         "prog=sf probe 0:1 1000000 3;"          \
 103         "sf erase 0 40000;"                     \
 104         "sf write ${loadaddr} 0 40000;"         \
 105         "save\0"                                \
 106         ""
 107 #elif defined(CONFIG_SYS_NAND_BOOT)
 108 #define CONFIG_EXTRA_ENV_SETTINGS               \
 109         "netdev=eth0\0"                         \
 110         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 111         "loadaddr=0x40010000\0"                 \
 112         "u-boot=u-boot.bin\0"                   \
 113         "load=tftp ${loadaddr} ${u-boot};\0"    \
 114         "upd=run load; run prog\0"              \
 115         "prog=nand device 0;"                   \
 116         "nand erase 0 40000;"                   \
 117         "nb_update ${loadaddr} ${filesize};"    \
 118         "save\0"                                \
 119         ""
 120 #else
 121 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 122 #define CONFIG_EXTRA_ENV_SETTINGS               \
 123         "netdev=eth0\0"                         \
 124         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 125         "loadaddr=40010000\0"                   \
 126         "u-boot=u-boot.bin\0"                   \
 127         "load=tftp ${loadaddr) ${u-boot}\0"     \
 128         "upd=run load; run prog\0"              \
 129         "prog=prot off mram" " ;"       \
 130         "cp.b ${loadaddr} 0 ${filesize};"       \
 131         "save\0"                                \
 132         ""
 133 #endif
 134
 135 /* Realtime clock */
 136 #undef CONFIG_MCFRTC
 137 #define CONFIG_RTC_MCFRRTC
 138 #define CONFIG_SYS_MCFRRTC_BASE         0xFC0A8000
 139
 140 /* Timer */
 141 #define CONFIG_MCFTMR
 142 #undef CONFIG_MCFPIT
 143
 144 /* I2c */
 145 #undef CONFIG_SYS_FSL_I2C
 146 #undef  CONFIG_SYS_I2C_SOFT     /* I2C bit-banged */
 147 /* I2C speed and slave address  */
 148 #define CONFIG_SYS_I2C_SPEED            80000
 149 #define CONFIG_SYS_I2C_SLAVE            0x7F
 150 #define CONFIG_SYS_I2C_OFFSET           0x58000
 151 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 152
 153 /* DSPI and Serial Flash */
 154 #define CONFIG_CF_DSPI
 155 #define CONFIG_SERIAL_FLASH
 156 #define CONFIG_HARD_SPI
 157 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 158 #ifdef CONFIG_CMD_SPI
 159
 160 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 161                                          DSPI_CTAR_PCSSCK_1CLK | \
 162                                          DSPI_CTAR_PASC(0) | \
 163                                          DSPI_CTAR_PDT(0) | \
 164                                          DSPI_CTAR_CSSCK(0) | \
 165                                          DSPI_CTAR_ASC(0) | \
 166                                          DSPI_CTAR_DT(1))
 167 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 168 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 169 #endif
 170
 171 /* Input, PCI, Flexbus, and VCO */
 172 #define CONFIG_EXTRA_CLOCK
 173
 174 #define CONFIG_PRAM                     2048    /* 2048 KB */
 175
 176 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 177
 178 #define CONFIG_SYS_MBAR         0xFC000000
 179
 180 /*
 181  * Low Level Configuration Settings
 182  * (address mappings, register initial values, etc.)
 183  * You should know what you are doing if you make changes here.
 184  */
 185
 186 /*-----------------------------------------------------------------------
 187  * Definitions for initial stack pointer and data area (in DPRAM)
 188  */
 189 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 190 /* End of used area in internal SRAM */
 191 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 192 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 193 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - \
 194                                         GENERATED_GBL_DATA_SIZE) - 32)
 195 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 196 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 197
 198 /*-----------------------------------------------------------------------
 199  * Start addresses for the final memory configuration
 200  * (Set up by the startup code)
 201  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 202  */
 203 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 204 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 205
 206 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x400)
 207 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 208 #define CONFIG_SYS_DRAM_TEST
 209
 210 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
 211 #define CONFIG_SERIAL_BOOT
 212 #endif
 213
 214 #if defined(CONFIG_SERIAL_BOOT)
 215 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
 216 #else
 217 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 218 #endif
 219
 220 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
 221 /* Reserve 256 kB for Monitor */
 222 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 223 /* Reserve 256 kB for malloc() */
 224 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 225
 226 /*
 227  * For booting Linux, the board info and command line data
 228  * have to be in the first 8 MB of memory, since this is
 229  * the maximum mapped by the Linux kernel during initialization ??
 230  */
 231 /* Initial Memory map for Linux */
 232 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
 233                                 (CONFIG_SYS_SDRAM_SIZE << 20))
 234
 235 /* Configuration for environment
 236  * Environment is embedded in u-boot in the second sector of the flash
 237  */
 238 #if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
 239 #define CONFIG_ENV_ADDR         (0x40000 - 0x1000) /*MRAM size 40000*/
 240 #define CONFIG_ENV_SIZE         0x1000
 241 #endif
 242
 243 #if defined(CONFIG_CF_SBF)
 244 #define CONFIG_ENV_SPI_CS               1
 245 #define CONFIG_ENV_OFFSET               0x40000
 246 #define CONFIG_ENV_SIZE         0x2000
 247 #define CONFIG_ENV_SECT_SIZE            0x10000
 248 #endif
 249 #if defined(CONFIG_SYS_NAND_BOOT)
 250 #define CONFIG_ENV_OFFSET       0x80000
 251 #define CONFIG_ENV_SIZE 0x20000
 252 #define CONFIG_ENV_SECT_SIZE    0x20000
 253 #endif
 254 #undef CONFIG_ENV_OVERWRITE
 255
 256 /* FLASH organization */
 257 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 258
 259 #undef CONFIG_SYS_FLASH_CFI
 260 #ifdef CONFIG_SYS_FLASH_CFI
 261
 262 #define CONFIG_FLASH_CFI_DRIVER 1
 263 /* Max size that the board might have */
 264 #define CONFIG_SYS_FLASH_SIZE           0x1000000
 265 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 266 /* max number of memory banks */
 267 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 268 /* max number of sectors on one chip */
 269 #define CONFIG_SYS_MAX_FLASH_SECT       270
 270 /* "Real" (hardware) sectors protection */
 271 #define CONFIG_SYS_FLASH_PROTECTION
 272 #define CONFIG_SYS_FLASH_CHECKSUM
 273 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_CS0_BASE }
 274 #else
 275 /* max number of sectors on one chip */
 276 #define CONFIG_SYS_MAX_FLASH_SECT       270
 277 /* max number of sectors on one chip */
 278 #define CONFIG_SYS_MAX_FLASH_BANKS      0
 279 #endif
 280
 281 /*
 282  * This is setting for JFFS2 support in u-boot.
 283  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 284  */
 285 #ifdef CONFIG_CMD_JFFS2
 286 #define CONFIG_JFFS2_DEV                "nand0"
 287 #define CONFIG_JFFS2_PART_OFFSET        (0x800000)
 288 #define CONFIG_MTD_DEVICE
 289
 290 #endif
 291
 292 #ifdef CONFIG_CMD_UBI
 293 #define CONFIG_MTD_DEVICE       /* needed for mtdparts command */
 294 #define CONFIG_MTD_PARTITIONS   /* mtdparts and UBI support */
 295 #endif
 296 /* Cache Configuration */
 297 #define CONFIG_SYS_CACHELINE_SIZE       16
 298 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 299                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 300 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 301                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 302 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 303 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 304 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 305                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 306                                          CF_ACR_EN | CF_ACR_SM_ALL)
 307 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 308                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 309 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 310                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 311                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 312
 313 #define CACR_STATUS     (CONFIG_SYS_INIT_RAM_ADDR + \
 314                         CONFIG_SYS_INIT_RAM_SIZE - 12)
 315
 316 /*-----------------------------------------------------------------------
 317  * Memory bank definitions
 318  */
 319 /*
 320  * CS0 - NOR Flash 16MB
 321  * CS1 - Available
 322  * CS2 - Available
 323  * CS3 - Available
 324  * CS4 - Available
 325  * CS5 - Available
 326  */
 327
 328  /* Flash */
 329 #define CONFIG_SYS_CS0_BASE             0x00000000
 330 #define CONFIG_SYS_CS0_MASK             0x000F0101
 331 #define CONFIG_SYS_CS0_CTRL             0x00001D60
 332
 333 #endif                          /* _M54418TWR_H */