include/configs/M54418TWR.h

   1 /*
   2  * Configuation settings for the Freescale MCF54418 TWR board.
   3  *
   4  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54418TWR_H
  15 #define _M54418TWR_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54418TWR        /* M54418TWR board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  26
  27 #undef CONFIG_WATCHDOG
  28
  29 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  30
  31 /*
  32  * BOOTP options
  33  */
  34 #define CONFIG_BOOTP_BOOTFILESIZE
  35 #define CONFIG_BOOTP_BOOTPATH
  36 #define CONFIG_BOOTP_GATEWAY
  37 #define CONFIG_BOOTP_HOSTNAME
  38
  39 /* Command line configuration */
  40 #undef CONFIG_CMD_NAND
  41 #define CONFIG_CMD_REGINFO
  42
  43 /*
  44  * NAND FLASH
  45  */
  46 #ifdef CONFIG_CMD_NAND
  47 #define CONFIG_JFFS2_NAND
  48 #define CONFIG_NAND_FSL_NFC
  49 #define CONFIG_SYS_NAND_BASE            0xFC0FC000
  50 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  51 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
  52 #define CONFIG_SYS_NAND_SELECT_DEVICE
  53 #endif
  54
  55 /* Network configuration */
  56 #define CONFIG_MCFFEC
  57 #ifdef CONFIG_MCFFEC
  58 #define CONFIG_MII                      1
  59 #define CONFIG_MII_INIT         1
  60 #define CONFIG_SYS_DISCOVER_PHY
  61 #define CONFIG_SYS_RX_ETH_BUFFER        2
  62 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
  63 #define CONFIG_SYS_TX_ETH_BUFFER        2
  64 #define CONFIG_HAS_ETH1
  65
  66 #define CONFIG_SYS_FEC0_PINMUX          0
  67 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  68 #define CONFIG_SYS_FEC1_PINMUX          0
  69 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  70 #define MCFFEC_TOUT_LOOP                50000
  71 #define CONFIG_SYS_FEC0_PHYADDR 0
  72 #define CONFIG_SYS_FEC1_PHYADDR 1
  73
  74
  75 #ifdef  CONFIG_SYS_NAND_BOOT
  76 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
  77                                 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
  78                                 "-(jffs2) console=ttyS0,115200"
  79 #else
  80 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot="     \
  81                                 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
  82                                 __stringify(CONFIG_IPADDR) "  ip="      \
  83                                 __stringify(CONFIG_IPADDR) ":"  \
  84                                 __stringify(CONFIG_SERVERIP)":" \
  85                                 __stringify(CONFIG_GATEWAYIP)": "       \
  86                                 __stringify(CONFIG_NETMASK)             \
  87                                 "::eth0:off:rw console=ttyS0,115200"
  88 #endif
  89
  90 #define CONFIG_ETHPRIME "FEC0"
  91 #define CONFIG_IPADDR           192.168.1.2
  92 #define CONFIG_NETMASK          255.255.255.0
  93 #define CONFIG_SERVERIP 192.168.1.1
  94 #define CONFIG_GATEWAYIP        192.168.1.1
  95
  96 #define CONFIG_SYS_FEC_BUF_USE_SRAM
  97 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  98 #ifndef CONFIG_SYS_DISCOVER_PHY
  99 #define FECDUPLEX       FULL
 100 #define FECSPEED        _100BASET
 101 #define LINKSTATUS      1
 102 #else
 103 #define LINKSTATUS      0
 104 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 105 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 106 #endif
 107 #endif                  /* CONFIG_SYS_DISCOVER_PHY */
 108 #endif
 109
 110 #define CONFIG_HOSTNAME         M54418TWR
 111
 112 #if defined(CONFIG_CF_SBF)
 113 /* ST Micro serial flash */
 114 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 115 #define CONFIG_EXTRA_ENV_SETTINGS               \
 116         "netdev=eth0\0"                         \
 117         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 118         "loadaddr=0x40010000\0"                 \
 119         "sbfhdr=sbfhdr.bin\0"                   \
 120         "uboot=u-boot.bin\0"                    \
 121         "load=tftp ${loadaddr} ${sbfhdr};"      \
 122         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 123         "upd=run load; run prog\0"              \
 124         "prog=sf probe 0:1 1000000 3;"          \
 125         "sf erase 0 40000;"                     \
 126         "sf write ${loadaddr} 0 40000;"         \
 127         "save\0"                                \
 128         ""
 129 #elif defined(CONFIG_SYS_NAND_BOOT)
 130 #define CONFIG_EXTRA_ENV_SETTINGS               \
 131         "netdev=eth0\0"                         \
 132         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 133         "loadaddr=0x40010000\0"                 \
 134         "u-boot=u-boot.bin\0"                   \
 135         "load=tftp ${loadaddr} ${u-boot};\0"    \
 136         "upd=run load; run prog\0"              \
 137         "prog=nand device 0;"                   \
 138         "nand erase 0 40000;"                   \
 139         "nb_update ${loadaddr} ${filesize};"    \
 140         "save\0"                                \
 141         ""
 142 #else
 143 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 144 #define CONFIG_EXTRA_ENV_SETTINGS               \
 145         "netdev=eth0\0"                         \
 146         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 147         "loadaddr=40010000\0"                   \
 148         "u-boot=u-boot.bin\0"                   \
 149         "load=tftp ${loadaddr) ${u-boot}\0"     \
 150         "upd=run load; run prog\0"              \
 151         "prog=prot off mram" " ;"       \
 152         "cp.b ${loadaddr} 0 ${filesize};"       \
 153         "save\0"                                \
 154         ""
 155 #endif
 156
 157 /* Realtime clock */
 158 #undef CONFIG_MCFRTC
 159 #define CONFIG_RTC_MCFRRTC
 160 #define CONFIG_SYS_MCFRRTC_BASE         0xFC0A8000
 161
 162 /* Timer */
 163 #define CONFIG_MCFTMR
 164 #undef CONFIG_MCFPIT
 165
 166 /* I2c */
 167 #undef CONFIG_SYS_FSL_I2C
 168 #undef  CONFIG_SYS_I2C_SOFT     /* I2C bit-banged */
 169 /* I2C speed and slave address  */
 170 #define CONFIG_SYS_I2C_SPEED            80000
 171 #define CONFIG_SYS_I2C_SLAVE            0x7F
 172 #define CONFIG_SYS_I2C_OFFSET           0x58000
 173 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 174
 175 /* DSPI and Serial Flash */
 176 #define CONFIG_CF_SPI
 177 #define CONFIG_CF_DSPI
 178 #define CONFIG_SERIAL_FLASH
 179 #define CONFIG_HARD_SPI
 180 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 181 #ifdef CONFIG_CMD_SPI
 182
 183 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 184                                          DSPI_CTAR_PCSSCK_1CLK | \
 185                                          DSPI_CTAR_PASC(0) | \
 186                                          DSPI_CTAR_PDT(0) | \
 187                                          DSPI_CTAR_CSSCK(0) | \
 188                                          DSPI_CTAR_ASC(0) | \
 189                                          DSPI_CTAR_DT(1))
 190 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 191 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 192 #endif
 193
 194 /* Input, PCI, Flexbus, and VCO */
 195 #define CONFIG_EXTRA_CLOCK
 196
 197 #define CONFIG_PRAM                     2048    /* 2048 KB */
 198
 199 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 200
 201 #if defined(CONFIG_CMD_KGDB)
 202 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 203 #else
 204 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 205 #endif
 206 /* Print Buffer Size */
 207 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 208                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 209 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 210 /* Boot Argument Buffer Size    */
 211 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 212
 213 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 214
 215 #define CONFIG_SYS_MBAR         0xFC000000
 216
 217 /*
 218  * Low Level Configuration Settings
 219  * (address mappings, register initial values, etc.)
 220  * You should know what you are doing if you make changes here.
 221  */
 222
 223 /*-----------------------------------------------------------------------
 224  * Definitions for initial stack pointer and data area (in DPRAM)
 225  */
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 227 /* End of used area in internal SRAM */
 228 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 229 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 230 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - \
 231                                         GENERATED_GBL_DATA_SIZE) - 32)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 234
 235 /*-----------------------------------------------------------------------
 236  * Start addresses for the final memory configuration
 237  * (Set up by the startup code)
 238  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 239  */
 240 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 241 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 242
 243 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x400)
 244 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 245 #define CONFIG_SYS_DRAM_TEST
 246
 247 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
 248 #define CONFIG_SERIAL_BOOT
 249 #endif
 250
 251 #if defined(CONFIG_SERIAL_BOOT)
 252 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
 253 #else
 254 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 255 #endif
 256
 257 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
 258 /* Reserve 256 kB for Monitor */
 259 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 260 /* Reserve 256 kB for malloc() */
 261 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 262
 263 /*
 264  * For booting Linux, the board info and command line data
 265  * have to be in the first 8 MB of memory, since this is
 266  * the maximum mapped by the Linux kernel during initialization ??
 267  */
 268 /* Initial Memory map for Linux */
 269 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
 270                                 (CONFIG_SYS_SDRAM_SIZE << 20))
 271
 272 /* Configuration for environment
 273  * Environment is embedded in u-boot in the second sector of the flash
 274  */
 275 #if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
 276 #define CONFIG_ENV_IS_IN_MRAM   1
 277 #define CONFIG_ENV_ADDR         (0x40000 - 0x1000) /*MRAM size 40000*/
 278 #define CONFIG_ENV_SIZE         0x1000
 279 #endif
 280
 281 #if defined(CONFIG_CF_SBF)
 282 #define CONFIG_ENV_IS_IN_SPI_FLASH      1
 283 #define CONFIG_ENV_SPI_CS               1
 284 #define CONFIG_ENV_OFFSET               0x40000
 285 #define CONFIG_ENV_SIZE         0x2000
 286 #define CONFIG_ENV_SECT_SIZE            0x10000
 287 #endif
 288 #if defined(CONFIG_SYS_NAND_BOOT)
 289 #define CONFIG_ENV_IS_NOWHERE
 290 #define CONFIG_ENV_OFFSET       0x80000
 291 #define CONFIG_ENV_SIZE 0x20000
 292 #define CONFIG_ENV_SECT_SIZE    0x20000
 293 #endif
 294 #undef CONFIG_ENV_OVERWRITE
 295
 296 /* FLASH organization */
 297 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 298
 299 #undef CONFIG_SYS_FLASH_CFI
 300 #ifdef CONFIG_SYS_FLASH_CFI
 301
 302 #define CONFIG_FLASH_CFI_DRIVER 1
 303 /* Max size that the board might have */
 304 #define CONFIG_SYS_FLASH_SIZE           0x1000000
 305 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 306 /* max number of memory banks */
 307 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 308 /* max number of sectors on one chip */
 309 #define CONFIG_SYS_MAX_FLASH_SECT       270
 310 /* "Real" (hardware) sectors protection */
 311 #define CONFIG_SYS_FLASH_PROTECTION
 312 #define CONFIG_SYS_FLASH_CHECKSUM
 313 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_CS0_BASE }
 314 #else
 315 /* max number of sectors on one chip */
 316 #define CONFIG_SYS_MAX_FLASH_SECT       270
 317 /* max number of sectors on one chip */
 318 #define CONFIG_SYS_MAX_FLASH_BANKS      0
 319 #endif
 320
 321 /*
 322  * This is setting for JFFS2 support in u-boot.
 323  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 324  */
 325 #ifdef CONFIG_CMD_JFFS2
 326 #define CONFIG_JFFS2_DEV                "nand0"
 327 #define CONFIG_JFFS2_PART_OFFSET        (0x800000)
 328 #define CONFIG_CMD_MTDPARTS
 329 #define CONFIG_MTD_DEVICE
 330 #define MTDIDS_DEFAULT          "nand0=m54418twr.nand"
 331
 332 #define MTDPARTS_DEFAULT        "mtdparts=m54418twr.nand:1m(data),"     \
 333                                                 "7m(kernel),"           \
 334                                                 "-(rootfs)"
 335
 336 #endif
 337
 338 #ifdef CONFIG_CMD_UBI
 339 #define CONFIG_CMD_MTDPARTS
 340 #define CONFIG_MTD_DEVICE       /* needed for mtdparts command */
 341 #define CONFIG_MTD_PARTITIONS   /* mtdparts and UBI support */
 342 #define CONFIG_RBTREE
 343 #define MTDIDS_DEFAULT          "nand0=NAND"
 344 #define MTDPARTS_DEFAULT        "mtdparts=NAND:1m(u-boot),"     \
 345                                         "-(ubi)"
 346 #endif
 347 /* Cache Configuration */
 348 #define CONFIG_SYS_CACHELINE_SIZE       16
 349 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 350                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 351 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 352                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 353 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 354 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 355 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 356                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 357                                          CF_ACR_EN | CF_ACR_SM_ALL)
 358 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 359                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 360 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 361                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 362                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 363
 364 #define CACR_STATUS     (CONFIG_SYS_INIT_RAM_ADDR + \
 365                         CONFIG_SYS_INIT_RAM_SIZE - 12)
 366
 367 /*-----------------------------------------------------------------------
 368  * Memory bank definitions
 369  */
 370 /*
 371  * CS0 - NOR Flash 16MB
 372  * CS1 - Available
 373  * CS2 - Available
 374  * CS3 - Available
 375  * CS4 - Available
 376  * CS5 - Available
 377  */
 378
 379  /* Flash */
 380 #define CONFIG_SYS_CS0_BASE             0x00000000
 381 #define CONFIG_SYS_CS0_MASK             0x000F0101
 382 #define CONFIG_SYS_CS0_CTRL             0x00001D60
 383
 384 #endif                          /* _M54418TWR_H */