include/configs/MHPC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
   4  *
   5  * (C) Copyright 2001
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * Configuation settings for the miniHiPerCam.
   9  *
  10  * -----------------------------------------------------------------
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  42 #define CONFIG_MHPC             1       /* on a miniHiPerCam            */
  43 #define CONFIG_BOARD_PRE_INIT   1       /* do special hardware init.    */
  44 #define CONFIG_MISC_INIT_R      1
  45
  46 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_SPEED
  47 #undef  CONFIG_8xx_CONS_SMC1
  48 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  49 #undef  CONFIG_8xx_CONS_NONE
  50 #define CONFIG_BAUDRATE         9600
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52
  53 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  54
  55 #define CONFIG_ENV_OVERWRITE    1
  56 #define CONFIG_ETHADDR          00:00:5b:ee:de:ad
  57
  58 #undef  CONFIG_BOOTARGS
  59 #define CONFIG_BOOTCOMMAND      \
  60         "bootp;"                                                                \
  61         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  62         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
  63         "bootm"
  64
  65 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  66 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  67
  68 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  69 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  70
  71 #undef  CONFIG_UCODE_PATCH
  72
  73 /* enable I2C and select the hardware/software driver */
  74 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  75 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  76 /*
  77  * Software (bit-bang) I2C driver configuration
  78  */
  79 #define PB_SCL          0x00000020      /* PB 26 */
  80 #define PB_SDA          0x00000010      /* PB 27 */
  81
  82 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  83 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  84 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  85 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  86 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
  87                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
  88 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
  89                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
  90 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  91
  92 #define CFG_I2C_SPEED                   50000
  93 #define CFG_I2C_SLAVE                   0xFE
  94 #define CFG_I2C_EEPROM_ADDR             0x50    /* EEPROM X24C04                */
  95 #define CFG_I2C_EEPROM_ADDR_LEN         1       /* bytes of address             */
  96 /* mask of address bits that overflow into the "EEPROM chip address"    */
  97 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
  98 #define CFG_EEPROM_PAGE_WRITE_BITS      3
  99 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 100
 101 #define LCD_VIDEO_ADDR          (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
 102 #define LCD_VIDEO_SIZE          SDRAM_RES_SIZE  /* 2MB */
 103 #define LCD_VIDEO_COLS          640
 104 #define LCD_VIDEO_ROWS          480
 105 #define LCD_VIDEO_FG            255
 106 #define LCD_VIDEO_BG            0
 107
 108 #undef  CONFIG_VIDEO                            /* test only ! s.a devices.c and 8xx */
 109 #define CONFIG_CFB_CONSOLE                      /* framebuffer console with std input */
 110 #define CONFIG_VIDEO_LOGO
 111
 112 #define VIDEO_KBD_INIT_FCT      0               /* no KBD dev on MHPC - use serial */
 113 #define VIDEO_TSTC_FCT          serial_tstc
 114 #define VIDEO_GETC_FCT          serial_getc
 115
 116 #define CONFIG_BR0_WORKAROUND   1
 117
 118 #define CONFIG_COMMANDS      ( CONFIG_CMD_DFL  | \
 119                                CFG_CMD_DATE    | \
 120                                CFG_CMD_EEPROM  | \
 121                                CFG_CMD_ELF     | \
 122                                CFG_CMD_I2C     | \
 123                                CFG_CMD_JFFS2   | \
 124                                CFG_CMD_REGINFO )
 125
 126 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 127
 128 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 129 #include <cmd_confdefs.h>
 130
 131 /*
 132  * Miscellaneous configurable options
 133  */
 134 #define CFG_LONGHELP                    /* undef to save memory         */
 135 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 136 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 137 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 138 #else
 139 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 140 #endif
 141 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 142 #define CFG_MAXARGS     16              /* max number of command args   */
 143 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 144
 145 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 146 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 147
 148 #define CFG_LOAD_ADDR           0x300000        /* default load address */
 149
 150 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 151
 152 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 153
 154 /*
 155  * Low Level Configuration Settings
 156  * (address mappings, register initial values, etc.)
 157  * You should know what you are doing if you make changes here.
 158  */
 159
 160 /*-----------------------------------------------------------------------
 161  * Physical memory map
 162  */
 163 #define CFG_IMMR                0xFFF00000 /* Internal Memory Mapped Register*/
 164
 165 /*-----------------------------------------------------------------------
 166  * Definitions for initial stack pointer and data area (in DPRAM)
 167  */
 168 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 169 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 170 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 171 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 172 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CFG_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CFG_SDRAM_BASE          0x00000000
 180 #define CFG_FLASH_BASE          0xfe000000
 181
 182 #define CFG_MONITOR_LEN         0x40000         /* Reserve 256 kB for Monitor   */
 183 #undef  CFG_MONITOR_BASE                    /* to run U-Boot from RAM */
 184 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 185 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 186
 187 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 188 #define CFG_JFFS2_NUM_BANKS     1           /* one flash only */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map- for Linux        */
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 201 #define CFG_MAX_FLASH_SECT      64      /* max number of sectors on one chip    */
 202
 203 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 204 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 205 #define CFG_ENV_IS_IN_FLASH     1
 206 #define CFG_ENV_OFFSET          CFG_MONITOR_LEN /* Offset of Environment */
 207 #define CFG_ENV_SIZE            0x20000 /* Total Size of Environment    */
 208
 209 /*-----------------------------------------------------------------------
 210  * Cache Configuration
 211  */
 212 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 214 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * SYPCR - System Protection Control                            11-9
 219  * SYPCR can only be written once after reset!
 220  *-----------------------------------------------------------------------
 221  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 222  */
 223 #if defined(CONFIG_WATCHDOG)
 224 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 225                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 226 #else
 227 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 228                          SYPCR_SWP)
 229 #endif
 230
 231 /*-----------------------------------------------------------------------
 232  * SIUMCR - SIU Module Configuration                            11-6
 233  *-----------------------------------------------------------------------
 234  * PCMCIA config., multi-function pin tri-state
 235  */
 236 #define CFG_SIUMCR      (SIUMCR_SEME)
 237
 238 /*-----------------------------------------------------------------------
 239  * TBSCR - Time Base Status and Control                         11-26
 240  *-----------------------------------------------------------------------
 241  * Clear Reference Interrupt Status, Timebase freezing enabled
 242  */
 243 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 244
 245 /*-----------------------------------------------------------------------
 246  * PISCR - Periodic Interrupt Status and Control                11-31
 247  *-----------------------------------------------------------------------
 248  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 249  */
 250 #define CFG_PISCR       (PISCR_PS | PISCR_PITF | PISCR_PTE)
 251
 252 /*-----------------------------------------------------------------------
 253  * RTCSC - Real-Time Clock Status and Control Register          12-18
 254  *-----------------------------------------------------------------------
 255  */
 256 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 257
 258 /*-----------------------------------------------------------------------
 259  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 260  *-----------------------------------------------------------------------
 261  * Reset PLL lock status sticky bit, timer expired status bit and timer
 262  * interrupt status bit - leave PLL multiplication factor unchanged !
 263  */
 264 #define MPC8XX_SPEED    50000000L
 265 #define MPC8XX_XIN      5000000L      /* ref clk */
 266 #define MPC8XX_FACT     (MPC8XX_SPEED/MPC8XX_XIN)
 267 #define CFG_PLPRCR      (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 268                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 269
 270 /*-----------------------------------------------------------------------
 271  * SCCR - System Clock and reset Control Register               15-27
 272  *-----------------------------------------------------------------------
 273  * Set clock output, timebase and RTC source and divider,
 274  * power management and some other internal clocks
 275  */
 276
 277 #define SCCR_MASK       (SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
 278 #define CFG_SCCR        (SCCR_TBS | SCCR_DFLCD001)
 279
 280
 281 /*-----------------------------------------------------------------------
 282  * MAMR settings for SDRAM      - 16-14
 283  * => 0xC080200F
 284  *-----------------------------------------------------------------------
 285  * periodic timer for refresh
 286  */
 287 #define CFG_MAMR_PTA    0xC0
 288 #define CFG_MAMR        ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
 289
 290 /*
 291  * BR0 and OR0 (FLASH) used to re-map FLASH
 292  */
 293
 294 /* allow for max 8 MB of Flash */
 295 #define FLASH_BASE              0xFE000000      /* FLASH bank #0*/
 296 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0*/
 297 #define CFG_REMAP_OR_AM         0xFF800000      /* OR addr mask */
 298 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 299
 300 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
 301
 302 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 303 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 304 #define CFG_BR0_PRELIM  ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
 305
 306 /*
 307  * BR1 and OR1 (SDRAM)
 308  */
 309 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 310 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB            */
 311 #define SDRAM_RES_SIZE          0x00200000      /* 2 MB for framebuffer */
 312
 313 /* SDRAM timing: drive GPL5 high on first cycle */
 314 #define CFG_OR_TIMING_SDRAM     (OR_G5LS)
 315
 316 #define CFG_OR1_PRELIM  ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
 317 #define CFG_BR1_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 318
 319 /*
 320  * BR2/OR2 - DIMM
 321  */
 322 #define CFG_OR2         (OR_ACS_DIV4)
 323 #define CFG_BR2         (BR_MS_UPMA)
 324
 325 /*
 326  * BR3/OR3 - DIMM
 327  */
 328 #define CFG_OR3         (OR_ACS_DIV4)
 329 #define CFG_BR3         (BR_MS_UPMA)
 330
 331 /*
 332  * BR4/OR4
 333  */
 334 #define CFG_OR4         0
 335 #define CFG_BR4         0
 336
 337 /*
 338  * BR5/OR5
 339  */
 340 #define CFG_OR5         0
 341 #define CFG_BR5         0
 342
 343 /*
 344  * BR6/OR6
 345  */
 346 #define CFG_OR6         0
 347 #define CFG_BR6         0
 348
 349 /*
 350  * BR7/OR7
 351  */
 352 #define CFG_OR7         0
 353 #define CFG_BR7         0
 354
 355
 356 /*-----------------------------------------------------------------------
 357  * Debug Entry Mode
 358  *-----------------------------------------------------------------------
 359  *
 360  */
 361 #define CFG_DER 0
 362
 363 /*
 364  * Internal Definitions
 365  *
 366  * Boot Flags
 367  */
 368 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 369 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 370
 371 #endif  /* __CONFIG_H */