include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23
  24
  25 /***********************************************************
  26  * Note that it may also be a MIP405T board which is a subset of the
  27  * MIP405
  28  ***********************************************************/
  29 /***********************************************************
  30  * WARNING:
  31  * CONFIG_BOOT_PCI is only used for first boot-up and should
  32  * NOT be enabled for production bootloader
  33  ***********************************************************/
  34 /*#define        CONFIG_BOOT_PCI         1*/
  35 /***********************************************************
  36  * Clock
  37  ***********************************************************/
  38 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  39
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_BOOTFILESIZE
  45 #define CONFIG_BOOTP_BOOTPATH
  46 #define CONFIG_BOOTP_GATEWAY
  47 #define CONFIG_BOOTP_HOSTNAME
  48
  49
  50 /*
  51  * Command line configuration.
  52  */
  53 #define CONFIG_CMD_CACHE
  54 #define CONFIG_CMD_DATE
  55 #define CONFIG_CMD_DHCP
  56 #define CONFIG_CMD_EEPROM
  57 #define CONFIG_CMD_FAT
  58 #define CONFIG_CMD_I2C
  59 #define CONFIG_CMD_IDE
  60 #define CONFIG_CMD_IRQ
  61 #define CONFIG_CMD_JFFS2
  62 #define CONFIG_CMD_MII
  63 #define CONFIG_CMD_PCI
  64 #define CONFIG_CMD_PING
  65 #define CONFIG_CMD_REGINFO
  66 #define CONFIG_CMD_SAVES
  67 #define CONFIG_CMD_BSP
  68
  69 #if !defined(CONFIG_MIP405T)
  70     #define CONFIG_CMD_USB
  71 #endif
  72
  73
  74 #define  CONFIG_SYS_HUSH_PARSER
  75 /**************************************************************
  76  * I2C Stuff:
  77  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  78  * 0x53.
  79  * The Atmel EEPROM uses 16Bit addressing.
  80  ***************************************************************/
  81
  82 #define CONFIG_SYS_I2C
  83 #define CONFIG_SYS_I2C_PPC4XX
  84 #define CONFIG_SYS_I2C_PPC4XX_CH0
  85 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  86 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  87
  88 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  89 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  90 /* mask of address bits that overflow into the "EEPROM chip address"    */
  91 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  92 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  93                                         /* 64 byte page write mode using*/
  94                                         /* last 6 bits of the address   */
  95 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  96
  97
  98 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
  99 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 100 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 101
 102 /***************************************************************
 103  * Definitions for Serial Presence Detect EEPROM address
 104  * (to get SDRAM settings)
 105  ***************************************************************/
 106 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 107 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 108 */
 109 /**************************************************************
 110  * Environment definitions
 111  **************************************************************/
 112 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 113 #define CONFIG_BOOTDELAY        5
 114 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 115 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 116 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 117
 118 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 119 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 120
 121 #define CONFIG_IPADDR           10.0.0.100
 122 #define CONFIG_SERVERIP         10.0.0.1
 123 #define CONFIG_PREBOOT
 124 /***************************************************************
 125  * defines if the console is stored in the environment
 126  ***************************************************************/
 127 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 128 /***************************************************************
 129  * defines if an overwrite_console function exists
 130  *************************************************************/
 131 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 132 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 133 /***************************************************************
 134  * defines if the overwrite_console should be stored in the
 135  * environment
 136  **************************************************************/
 137 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 138
 139 /**************************************************************
 140  * loads config
 141  *************************************************************/
 142 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 143 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 144
 145 #define CONFIG_MISC_INIT_R
 146 /***********************************************************
 147  * Miscellaneous configurable options
 148  **********************************************************/
 149 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 150 #if defined(CONFIG_CMD_KGDB)
 151 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 152 #else
 153 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 154 #endif
 155 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 156 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 157 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 158
 159 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 160 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 161
 162 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 163 #define CONFIG_SYS_NS16550_SERIAL
 164 #define CONFIG_SYS_NS16550_REG_SIZE     1
 165 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 166
 167 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 168 #define CONFIG_SYS_BASE_BAUD       916667
 169
 170 /* The following table includes the supported baudrates */
 171 #define CONFIG_SYS_BAUDRATE_TABLE       \
 172         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 173          57600, 115200, 230400, 460800, 921600 }
 174
 175 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 176 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 177
 178 /*-----------------------------------------------------------------------
 179  * PCI stuff
 180  *-----------------------------------------------------------------------
 181  */
 182 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 183 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 184 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 185
 186 #define CONFIG_PCI                      /* include pci support          */
 187 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 188 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 189 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 190                                         /* resource configuration       */
 191 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 192 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 193 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 194 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 195 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 196 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 197 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 198 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 199
 200 /*-----------------------------------------------------------------------
 201  * Start addresses for the final memory configuration
 202  * (Set up by the startup code)
 203  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 204  */
 205 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 206 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 208 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 209 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 210
 211 /*
 212  * For booting Linux, the board info and command line data
 213  * have to be in the first 8 MB of memory, since this is
 214  * the maximum mapped by the Linux kernel during initialization.
 215  */
 216 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 217 /*-----------------------------------------------------------------------
 218  * FLASH organization
 219  */
 220 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 221 #define CONFIG_SYS_FLASH_PROTECTION
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO
 223
 224 #define CONFIG_SYS_FLASH_CFI
 225 #define CONFIG_FLASH_CFI_DRIVER
 226
 227 #define CONFIG_FLASH_SHOW_PROGRESS      45
 228
 229 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 230 #define CONFIG_SYS_MAX_FLASH_SECT       256
 231
 232 /*
 233  * JFFS2 partitions
 234  *
 235  */
 236 /* No command line, one static partition, whole device */
 237 #undef CONFIG_CMD_MTDPARTS
 238 #define CONFIG_JFFS2_DEV                "nor0"
 239 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 240 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 241
 242 /* mtdparts command line support */
 243 /* Note: fake mtd_id used, no linux mtd map file */
 244 /*
 245 #define CONFIG_CMD_MTDPARTS
 246 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 247 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 248 */
 249
 250 /*-----------------------------------------------------------------------
 251  * Logbuffer Configuration
 252  */
 253 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 254 /*-----------------------------------------------------------------------
 255  * Bootcountlimit Configuration
 256  */
 257 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 258
 259 /*-----------------------------------------------------------------------
 260  * POST Configuration
 261  */
 262 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 263 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 264                                  CONFIG_SYS_POST_CPU            | \
 265                                  CONFIG_SYS_POST_RTC            | \
 266                                  CONFIG_SYS_POST_I2C)
 267
 268 #endif
 269 /*
 270  * Init Memory Controller:
 271  */
 272 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 273 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 274 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 275 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 276
 277 #define CONFIG_BOARD_EARLY_INIT_F 1
 278 #define CONFIG_BOARD_EARLY_INIT_R
 279
 280 /* Peripheral Bus Mapping */
 281 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 282 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 283 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 284
 285 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 286 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 287
 288
 289 /*-----------------------------------------------------------------------
 290  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 291  */
 292 #define CONFIG_SYS_TEMP_STACK_OCM      1
 293 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 294 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 295 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 296 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 297 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 298 /* reserve some memory for POST and BOOT limit info */
 299 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 300
 301 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 302 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 303 #endif
 304
 305 /***********************************************************************
 306  * External peripheral base address
 307  ***********************************************************************/
 308 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 309
 310 /***********************************************************************
 311  * Last Stage Init
 312  ***********************************************************************/
 313 #define CONFIG_LAST_STAGE_INIT
 314 /************************************************************
 315  * Ethernet Stuff
 316  ***********************************************************/
 317 #define CONFIG_PPC4xx_EMAC
 318 #define CONFIG_MII              1       /* MII PHY management           */
 319 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 320 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 321 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 322 /************************************************************
 323  * RTC
 324  ***********************************************************/
 325 #define CONFIG_RTC_MC146818
 326 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 327
 328 /************************************************************
 329  * IDE/ATA stuff
 330  ************************************************************/
 331 #if defined(CONFIG_MIP405T)
 332 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 333 #else
 334 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 335 #endif
 336
 337 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 338
 339 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 340 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 341 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 342 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 343 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 344 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 345
 346 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 347 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 348 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 349 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 350 #define CONFIG_SUPPORT_VFAT
 351 /************************************************************
 352  * ATAPI support (experimental)
 353  ************************************************************/
 354 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 355
 356 /************************************************************
 357  * DISK Partition support
 358  ************************************************************/
 359 #define CONFIG_DOS_PARTITION
 360 #define CONFIG_MAC_PARTITION
 361 #define CONFIG_ISO_PARTITION /* Experimental */
 362
 363 /************************************************************
 364  * Video support
 365  ************************************************************/
 366 #define CONFIG_VIDEO                    /*To enable video controller support */
 367 #define CONFIG_VIDEO_CT69000
 368 #define CONFIG_CFB_CONSOLE
 369 #define CONFIG_VIDEO_LOGO
 370 #define CONFIG_CONSOLE_EXTRA_INFO
 371 #define CONFIG_VGA_AS_SINGLE_DEVICE
 372 #define CONFIG_VIDEO_SW_CURSOR
 373 #undef CONFIG_VIDEO_ONBOARD
 374 /************************************************************
 375  * USB support EXPERIMENTAL
 376  ************************************************************/
 377 #if !defined(CONFIG_MIP405T)
 378 #define CONFIG_USB_UHCI
 379 #define CONFIG_USB_KEYBOARD
 380 #define CONFIG_USB_STORAGE
 381
 382 /* Enable needed helper functions */
 383 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 384 #endif
 385 /************************************************************
 386  * Debug support
 387  ************************************************************/
 388 #if defined(CONFIG_CMD_KGDB)
 389 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 390 #endif
 391
 392 /************************************************************
 393  * support BZIP2 compression
 394  ************************************************************/
 395 #define CONFIG_BZIP2            1
 396
 397 /************************************************************
 398  * Ident
 399  ************************************************************/
 400
 401 #define VERSION_TAG "released"
 402 #if !defined(CONFIG_MIP405T)
 403 #define CONFIG_ISO_STRING "MEV-10072-001"
 404 #else
 405 #define CONFIG_ISO_STRING "MEV-10082-001"
 406 #endif
 407
 408 #if !defined(CONFIG_BOOT_PCI)
 409 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 410 #else
 411 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 412 #endif
 413
 414
 415 #endif  /* __CONFIG_H */