include/configs/MPC832XEMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * High Level Configuration Options
  12  */
  13 #define CONFIG_E300             1       /* E300 family */
  14 #define CONFIG_QE               1       /* Has QE */
  15 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  16 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  17
  18 /*
  19  * System Clock Setup
  20  */
  21 #ifdef CONFIG_PCISLAVE
  22 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  23 #else
  24 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  25 #endif
  26
  27 #ifndef CONFIG_SYS_CLK_FREQ
  28 #define CONFIG_SYS_CLK_FREQ     66000000
  29 #endif
  30
  31 /*
  32  * Hardware Reset Configuration Word
  33  */
  34 #define CONFIG_SYS_HRCW_LOW (\
  35         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  36         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  37         HRCWL_VCO_1X2 |\
  38         HRCWL_CSB_TO_CLKIN_2X1 |\
  39         HRCWL_CORE_TO_CSB_2X1 |\
  40         HRCWL_CE_PLL_VCO_DIV_2 |\
  41         HRCWL_CE_PLL_DIV_1X1 |\
  42         HRCWL_CE_TO_PLL_1X3)
  43
  44 #ifdef CONFIG_PCISLAVE
  45 #define CONFIG_SYS_HRCW_HIGH (\
  46         HRCWH_PCI_AGENT |\
  47         HRCWH_PCI1_ARBITER_DISABLE |\
  48         HRCWH_CORE_ENABLE |\
  49         HRCWH_FROM_0XFFF00100 |\
  50         HRCWH_BOOTSEQ_DISABLE |\
  51         HRCWH_SW_WATCHDOG_DISABLE |\
  52         HRCWH_ROM_LOC_LOCAL_16BIT |\
  53         HRCWH_BIG_ENDIAN |\
  54         HRCWH_LALE_NORMAL)
  55 #else
  56 #define CONFIG_SYS_HRCW_HIGH (\
  57         HRCWH_PCI_HOST |\
  58         HRCWH_PCI1_ARBITER_ENABLE |\
  59         HRCWH_CORE_ENABLE |\
  60         HRCWH_FROM_0X00000100 |\
  61         HRCWH_BOOTSEQ_DISABLE |\
  62         HRCWH_SW_WATCHDOG_DISABLE |\
  63         HRCWH_ROM_LOC_LOCAL_16BIT |\
  64         HRCWH_BIG_ENDIAN |\
  65         HRCWH_LALE_NORMAL)
  66 #endif
  67
  68 /*
  69  * System IO Config
  70  */
  71 #define CONFIG_SYS_SICRL                0x00000000
  72
  73 #define CONFIG_BOARD_EARLY_INIT_R
  74
  75 /*
  76  * IMMR new address
  77  */
  78 #define CONFIG_SYS_IMMR         0xE0000000
  79
  80 /*
  81  * DDR Setup
  82  */
  83 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  84 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  86 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  87
  88 #undef CONFIG_SPD_EEPROM
  89 #if defined(CONFIG_SPD_EEPROM)
  90 /* Determine DDR configuration from I2C interface
  91  */
  92 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  93 #else
  94 /* Manually set up DDR parameters
  95  */
  96 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  97 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  98                                         | CSCONFIG_AP \
  99                                         | CSCONFIG_ODT_WR_CFG \
 100                                         | CSCONFIG_ROW_BIT_13 \
 101                                         | CSCONFIG_COL_BIT_10)
 102                                         /* 0x80840102 */
 103 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
 104                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
 105                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
 106                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
 107                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 108                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 109                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 110                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 111                                         /* 0x00220802 */
 112 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 113                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 114                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 115                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 116                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
 117                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 118                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 119                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 120                                         /* 0x3935D322 */
 121 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 122                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 123                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 124                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 125                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 126                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 127                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 128                                 /* 0x0F9048CA */
 129 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 130 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 131                                         /* 0x02000000 */
 132 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 133                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 134                                         /* 0x44400232 */
 135 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 136 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 137                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 138                                         /* 0x03200064 */
 139 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 140 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 141                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 142                                         | SDRAM_CFG_32_BE)
 143                                         /* 0x43080000 */
 144 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 145 #endif
 146
 147 /*
 148  * Memory test
 149  */
 150 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 151 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 152 #define CONFIG_SYS_MEMTEST_END          0x00100000
 153
 154 /*
 155  * The reserved memory
 156  */
 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 158
 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 160 #define CONFIG_SYS_RAMBOOT
 161 #else
 162 #undef  CONFIG_SYS_RAMBOOT
 163 #endif
 164
 165 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 166 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 167 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 168
 169 /*
 170  * Initial RAM Base Address Setup
 171  */
 172 #define CONFIG_SYS_INIT_RAM_LOCK        1
 173 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 174 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 176                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 177
 178 /*
 179  * Local Bus Configuration & Clock Setup
 180  */
 181 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 182 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 183 #define CONFIG_SYS_LBC_LBCR             0x00000000
 184
 185 /*
 186  * FLASH on the Local Bus
 187  */
 188 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 189 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 190 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 191 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 192 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 193
 194                                         /* Window base at flash base */
 195 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 196 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 197
 198 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 199                                 | BR_PS_16      /* 16 bit port */ \
 200                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 201                                 | BR_V)         /* valid */
 202 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 203                                 | OR_GPCM_XAM \
 204                                 | OR_GPCM_CSNT \
 205                                 | OR_GPCM_ACS_DIV2 \
 206                                 | OR_GPCM_XACS \
 207                                 | OR_GPCM_SCY_15 \
 208                                 | OR_GPCM_TRLX_SET \
 209                                 | OR_GPCM_EHTR_SET \
 210                                 | OR_GPCM_EAD)
 211                                 /* 0xfe006ff7 */
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 215
 216 #undef CONFIG_SYS_FLASH_CHECKSUM
 217
 218 /*
 219  * BCSR on the Local Bus
 220  */
 221 #define CONFIG_SYS_BCSR                 0xF8000000
 222                                         /* Access window base at BCSR base */
 223 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 224 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 225
 226 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 227                                         | BR_PS_8 \
 228                                         | BR_MS_GPCM \
 229                                         | BR_V)
 230 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 231                                         | OR_GPCM_XAM \
 232                                         | OR_GPCM_CSNT \
 233                                         | OR_GPCM_XACS \
 234                                         | OR_GPCM_SCY_15 \
 235                                         | OR_GPCM_TRLX_SET \
 236                                         | OR_GPCM_EHTR_SET \
 237                                         | OR_GPCM_EAD)
 238                                         /* 0xFFFFE9F7 */
 239
 240 /*
 241  * Windows to access PIB via local bus
 242  */
 243                                         /* PIB window base 0xF8008000 */
 244 #define CONFIG_SYS_PIB_BASE             0xF8008000
 245 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 246 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 247 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 248
 249 /*
 250  * CS2 on Local Bus, to PIB
 251  */
 252 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 253                                 | BR_PS_8 \
 254                                 | BR_MS_GPCM \
 255                                 | BR_V)
 256                                 /* 0xF8008801 */
 257 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 258                                 | OR_GPCM_XAM \
 259                                 | OR_GPCM_CSNT \
 260                                 | OR_GPCM_XACS \
 261                                 | OR_GPCM_SCY_15 \
 262                                 | OR_GPCM_TRLX_SET \
 263                                 | OR_GPCM_EHTR_SET \
 264                                 | OR_GPCM_EAD)
 265                                 /* 0xffffe9f7 */
 266
 267 /*
 268  * CS3 on Local Bus, to PIB
 269  */
 270 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 271                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 272                                 | BR_PS_8 \
 273                                 | BR_MS_GPCM \
 274                                 | BR_V)
 275                                 /* 0xF8010801 */
 276 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 277                                 | OR_GPCM_XAM \
 278                                 | OR_GPCM_CSNT \
 279                                 | OR_GPCM_XACS \
 280                                 | OR_GPCM_SCY_15 \
 281                                 | OR_GPCM_TRLX_SET \
 282                                 | OR_GPCM_EHTR_SET \
 283                                 | OR_GPCM_EAD)
 284                                 /* 0xffffe9f7 */
 285
 286 /*
 287  * Serial Port
 288  */
 289 #define CONFIG_CONS_INDEX       1
 290 #define CONFIG_SYS_NS16550_SERIAL
 291 #define CONFIG_SYS_NS16550_REG_SIZE     1
 292 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 293
 294 #define CONFIG_SYS_BAUDRATE_TABLE  \
 295                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 296
 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 299
 300 /* I2C */
 301 #define CONFIG_SYS_I2C
 302 #define CONFIG_SYS_I2C_FSL
 303 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 304 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 305 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 306 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 307
 308 /*
 309  * Config on-board RTC
 310  */
 311 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 312 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 313
 314 /*
 315  * General PCI
 316  * Addresses are mapped 1-1.
 317  */
 318 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 319 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 320 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 321 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 322 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 323 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 324 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 325 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 326 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 327
 328 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 329 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 330 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 331
 332 #ifdef CONFIG_PCI
 333 #define CONFIG_PCI_INDIRECT_BRIDGE
 334
 335 #define CONFIG_83XX_PCI_STREAMING
 336
 337 #undef CONFIG_EEPRO100
 338 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 339 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 340
 341 #endif  /* CONFIG_PCI */
 342
 343 /*
 344  * QE UEC ethernet configuration
 345  */
 346 #define CONFIG_UEC_ETH
 347 #define CONFIG_ETHPRIME         "UEC0"
 348
 349 #define CONFIG_UEC_ETH1         /* ETH3 */
 350
 351 #ifdef CONFIG_UEC_ETH1
 352 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 353 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 354 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 355 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 356 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 357 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 358 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 359 #endif
 360
 361 #define CONFIG_UEC_ETH2         /* ETH4 */
 362
 363 #ifdef CONFIG_UEC_ETH2
 364 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 365 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 366 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 367 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 368 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 369 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 370 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 371 #endif
 372
 373 /*
 374  * Environment
 375  */
 376 #ifndef CONFIG_SYS_RAMBOOT
 377         #define CONFIG_ENV_ADDR         \
 378                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 379         #define CONFIG_ENV_SECT_SIZE    0x20000
 380         #define CONFIG_ENV_SIZE         0x2000
 381 #else
 382         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 383         #define CONFIG_ENV_SIZE         0x2000
 384 #endif
 385
 386 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 387 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 388
 389 /*
 390  * BOOTP options
 391  */
 392 #define CONFIG_BOOTP_BOOTFILESIZE
 393
 394 /*
 395  * Command line configuration.
 396  */
 397
 398 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 399
 400 /*
 401  * Miscellaneous configurable options
 402  */
 403 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 404
 405 /*
 406  * For booting Linux, the board info and command line data
 407  * have to be in the first 256 MB of memory, since this is
 408  * the maximum mapped by the Linux kernel during initialization.
 409  */
 410                                         /* Initial Memory map for Linux */
 411 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 412 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 413
 414 /*
 415  * Core HID Setup
 416  */
 417 #define CONFIG_SYS_HID0_INIT    0x000000000
 418 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 419                                  HID0_ENABLE_INSTRUCTION_CACHE)
 420 #define CONFIG_SYS_HID2         HID2_HBE
 421
 422 /*
 423  * MMU Setup
 424  */
 425
 426 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 427
 428 /* DDR: cache cacheable */
 429 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 430                                 | BATL_PP_RW \
 431                                 | BATL_MEMCOHERENCE)
 432 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 433                                 | BATU_BL_256M \
 434                                 | BATU_VS \
 435                                 | BATU_VP)
 436 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 437 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 438
 439 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 440 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 441                                 | BATL_PP_RW \
 442                                 | BATL_CACHEINHIBIT \
 443                                 | BATL_GUARDEDSTORAGE)
 444 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 445                                 | BATU_BL_4M \
 446                                 | BATU_VS \
 447                                 | BATU_VP)
 448 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 449 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 450
 451 /* BCSR: cache-inhibit and guarded */
 452 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 453                                 | BATL_PP_RW \
 454                                 | BATL_CACHEINHIBIT \
 455                                 | BATL_GUARDEDSTORAGE)
 456 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 457                                 | BATU_BL_128K \
 458                                 | BATU_VS \
 459                                 | BATU_VP)
 460 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 461 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 462
 463 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 464 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 465                                 | BATL_PP_RW \
 466                                 | BATL_MEMCOHERENCE)
 467 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 468                                 | BATU_BL_32M \
 469                                 | BATU_VS \
 470                                 | BATU_VP)
 471 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 472                                 | BATL_PP_RW \
 473                                 | BATL_CACHEINHIBIT \
 474                                 | BATL_GUARDEDSTORAGE)
 475 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 476
 477 #define CONFIG_SYS_IBAT4L       (0)
 478 #define CONFIG_SYS_IBAT4U       (0)
 479 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 480 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 481
 482 /* Stack in dcache: cacheable, no memory coherence */
 483 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 484 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 485                                 | BATU_BL_128K \
 486                                 | BATU_VS \
 487                                 | BATU_VP)
 488 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 489 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 490
 491 #ifdef CONFIG_PCI
 492 /* PCI MEM space: cacheable */
 493 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 494                                 | BATL_PP_RW \
 495                                 | BATL_MEMCOHERENCE)
 496 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 497                                 | BATU_BL_256M \
 498                                 | BATU_VS \
 499                                 | BATU_VP)
 500 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 501 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 502 /* PCI MMIO space: cache-inhibit and guarded */
 503 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 504                                 | BATL_PP_RW \
 505                                 | BATL_CACHEINHIBIT \
 506                                 | BATL_GUARDEDSTORAGE)
 507 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 508                                 | BATU_BL_256M \
 509                                 | BATU_VS \
 510                                 | BATU_VP)
 511 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 512 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 513 #else
 514 #define CONFIG_SYS_IBAT6L       (0)
 515 #define CONFIG_SYS_IBAT6U       (0)
 516 #define CONFIG_SYS_IBAT7L       (0)
 517 #define CONFIG_SYS_IBAT7U       (0)
 518 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 519 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 520 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 521 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 522 #endif
 523
 524 #if defined(CONFIG_CMD_KGDB)
 525 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 526 #endif
 527
 528 /*
 529  * Environment Configuration
 530  */ #define CONFIG_ENV_OVERWRITE
 531
 532 #if defined(CONFIG_UEC_ETH)
 533 #define CONFIG_HAS_ETH0
 534 #define CONFIG_HAS_ETH1
 535 #endif
 536
 537 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 538
 539 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 540         "netdev=eth0\0"                                                 \
 541         "consoledev=ttyS0\0"                                            \
 542         "ramdiskaddr=1000000\0"                                         \
 543         "ramdiskfile=ramfs.83xx\0"                                      \
 544         "fdtaddr=780000\0"                                              \
 545         "fdtfile=mpc832x_mds.dtb\0"                                     \
 546         ""
 547
 548 #define CONFIG_NFSBOOTCOMMAND                                           \
 549         "setenv bootargs root=/dev/nfs rw "                             \
 550                 "nfsroot=$serverip:$rootpath "                          \
 551                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 552                                                         "$netdev:off "  \
 553                 "console=$consoledev,$baudrate $othbootargs;"           \
 554         "tftp $loadaddr $bootfile;"                                     \
 555         "tftp $fdtaddr $fdtfile;"                                       \
 556         "bootm $loadaddr - $fdtaddr"
 557
 558 #define CONFIG_RAMBOOTCOMMAND                                           \
 559         "setenv bootargs root=/dev/ram rw "                             \
 560                 "console=$consoledev,$baudrate $othbootargs;"           \
 561         "tftp $ramdiskaddr $ramdiskfile;"                               \
 562         "tftp $loadaddr $bootfile;"                                     \
 563         "tftp $fdtaddr $fdtfile;"                                       \
 564         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 565
 566 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 567
 568 #endif  /* __CONFIG_H */