include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8555cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_CPM2             1       /* has CPM2 */
  20 #define CONFIG_MPC8555          1       /* MPC8555 specific */
  21 #define CONFIG_MPC8555CDS       1       /* MPC8555CDS board specific */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  24
  25 #define CONFIG_PCI_INDIRECT_BRIDGE
  26 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  27 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  28 #define CONFIG_ENV_OVERWRITE
  29 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  30
  31 #define CONFIG_FSL_VIA
  32
  33 #ifndef __ASSEMBLY__
  34 extern unsigned long get_clock_freq(void);
  35 #endif
  36 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  37
  38 /*
  39  * These can be toggled for performance analysis, otherwise use default.
  40  */
  41 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  42 #define CONFIG_BTB                          /* toggle branch predition */
  43
  44 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  45 #define CONFIG_SYS_MEMTEST_END          0x00400000
  46
  47 #define CONFIG_SYS_CCSRBAR              0xe0000000
  48 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  49
  50 /* DDR Setup */
  51 #define CONFIG_SYS_FSL_DDR1
  52 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  53 #define CONFIG_DDR_SPD
  54 #undef CONFIG_FSL_DDR_INTERACTIVE
  55
  56 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  57
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  59 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  60
  61 #define CONFIG_NUM_DDR_CONTROLLERS      1
  62 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  63 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  64
  65 /* I2C addresses of SPD EEPROMs */
  66 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  67
  68 /* Make sure required options are set */
  69 #ifndef CONFIG_SPD_EEPROM
  70 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  71 #endif
  72
  73 #undef CONFIG_CLOCKS_IN_MHZ
  74
  75 /*
  76  * Local Bus Definitions
  77  */
  78
  79 /*
  80  * FLASH on the Local Bus
  81  * Two banks, 8M each, using the CFI driver.
  82  * Boot from BR0/OR0 bank at 0xff00_0000
  83  * Alternate BR1/OR1 bank at 0xff80_0000
  84  *
  85  * BR0, BR1:
  86  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  87  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  88  *    Port Size = 16 bits = BRx[19:20] = 10
  89  *    Use GPCM = BRx[24:26] = 000
  90  *    Valid = BRx[31] = 1
  91  *
  92  * 0    4    8    12   16   20   24   28
  93  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  94  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  95  *
  96  * OR0, OR1:
  97  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  98  *    Reserved ORx[17:18] = 11, confusion here?
  99  *    CSNT = ORx[20] = 1
 100  *    ACS = half cycle delay = ORx[21:22] = 11
 101  *    SCY = 6 = ORx[24:27] = 0110
 102  *    TRLX = use relaxed timing = ORx[29] = 1
 103  *    EAD = use external address latch delay = OR[31] = 1
 104  *
 105  * 0    4    8    12   16   20   24   28
 106  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 107  */
 108
 109 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 110
 111 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 112 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 113
 114 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 115 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 116
 117 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 118 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 119 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 120 #undef  CONFIG_SYS_FLASH_CHECKSUM
 121 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 122 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 123
 124 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 125
 126 #define CONFIG_FLASH_CFI_DRIVER
 127 #define CONFIG_SYS_FLASH_CFI
 128 #define CONFIG_SYS_FLASH_EMPTY_INFO
 129
 130 /*
 131  * SDRAM on the Local Bus
 132  */
 133 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 134 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 135
 136 /*
 137  * Base Register 2 and Option Register 2 configure SDRAM.
 138  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 139  *
 140  * For BR2, need:
 141  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 142  *    port-size = 32-bits = BR2[19:20] = 11
 143  *    no parity checking = BR2[21:22] = 00
 144  *    SDRAM for MSEL = BR2[24:26] = 011
 145  *    Valid = BR[31] = 1
 146  *
 147  * 0    4    8    12   16   20   24   28
 148  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 149  *
 150  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 151  * FIXME: the top 17 bits of BR2.
 152  */
 153
 154 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 155
 156 /*
 157  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 158  *
 159  * For OR2, need:
 160  *    64MB mask for AM, OR2[0:7] = 1111 1100
 161  *                 XAM, OR2[17:18] = 11
 162  *    9 columns OR2[19-21] = 010
 163  *    13 rows   OR2[23-25] = 100
 164  *    EAD set for extra time OR[31] = 1
 165  *
 166  * 0    4    8    12   16   20   24   28
 167  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 168  */
 169
 170 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 171
 172 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 173 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 174 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 175 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 176
 177 /*
 178  * Common settings for all Local Bus SDRAM commands.
 179  * At run time, either BSMA1516 (for CPU 1.1)
 180  *                  or BSMA1617 (for CPU 1.0) (old)
 181  * is OR'ed in too.
 182  */
 183 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 184                                 | LSDMR_PRETOACT7       \
 185                                 | LSDMR_ACTTORW7        \
 186                                 | LSDMR_BL8             \
 187                                 | LSDMR_WRC4            \
 188                                 | LSDMR_CL3             \
 189                                 | LSDMR_RFEN            \
 190                                 )
 191
 192 /*
 193  * The CADMUS registers are connected to CS3 on CDS.
 194  * The new memory map places CADMUS at 0xf8000000.
 195  *
 196  * For BR3, need:
 197  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 198  *    port-size = 8-bits  = BR[19:20] = 01
 199  *    no parity checking  = BR[21:22] = 00
 200  *    GPMC for MSEL       = BR[24:26] = 000
 201  *    Valid               = BR[31]    = 1
 202  *
 203  * 0    4    8    12   16   20   24   28
 204  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 205  *
 206  * For OR3, need:
 207  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 208  *    disable buffer ctrl OR[19]    = 0
 209  *    CSNT                OR[20]    = 1
 210  *    ACS                 OR[21:22] = 11
 211  *    XACS                OR[23]    = 1
 212  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 213  *    SETA                OR[28]    = 0
 214  *    TRLX                OR[29]    = 1
 215  *    EHTR                OR[30]    = 1
 216  *    EAD extra time      OR[31]    = 1
 217  *
 218  * 0    4    8    12   16   20   24   28
 219  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 220  */
 221
 222 #define CONFIG_FSL_CADMUS
 223
 224 #define CADMUS_BASE_ADDR 0xf8000000
 225 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 226 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 227
 228 #define CONFIG_SYS_INIT_RAM_LOCK        1
 229 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 230 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 231
 232 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 233 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 234
 235 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 236 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 237
 238 /* Serial Port */
 239 #define CONFIG_CONS_INDEX     2
 240 #define CONFIG_SYS_NS16550_SERIAL
 241 #define CONFIG_SYS_NS16550_REG_SIZE    1
 242 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 243
 244 #define CONFIG_SYS_BAUDRATE_TABLE  \
 245         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 246
 247 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 248 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 249
 250 /*
 251  * I2C
 252  */
 253 #define CONFIG_SYS_I2C
 254 #define CONFIG_SYS_I2C_FSL
 255 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 256 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 257 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 258 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 259
 260 /* EEPROM */
 261 #define CONFIG_ID_EEPROM
 262 #define CONFIG_SYS_I2C_EEPROM_CCID
 263 #define CONFIG_SYS_ID_EEPROM
 264 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 265 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 266
 267 /*
 268  * General PCI
 269  * Addresses are mapped 1-1.
 270  */
 271 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 272 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 273 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 274 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 275 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 276 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 277 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 278 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 279
 280 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 281 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 282 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 283 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 284 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 285 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 286 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 287 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 288
 289 #ifdef CONFIG_LEGACY
 290 #define BRIDGE_ID 17
 291 #define VIA_ID 2
 292 #else
 293 #define BRIDGE_ID 28
 294 #define VIA_ID 4
 295 #endif
 296
 297 #if defined(CONFIG_PCI)
 298
 299 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 300 #define CONFIG_MPC85XX_PCI2
 301
 302 #undef CONFIG_EEPRO100
 303 #undef CONFIG_TULIP
 304
 305 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 306 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 307
 308 #endif  /* CONFIG_PCI */
 309
 310 #if defined(CONFIG_TSEC_ENET)
 311
 312 #define CONFIG_MII              1       /* MII PHY management */
 313 #define CONFIG_TSEC1    1
 314 #define CONFIG_TSEC1_NAME       "TSEC0"
 315 #define CONFIG_TSEC2    1
 316 #define CONFIG_TSEC2_NAME       "TSEC1"
 317 #define TSEC1_PHY_ADDR          0
 318 #define TSEC2_PHY_ADDR          1
 319 #define TSEC1_PHYIDX            0
 320 #define TSEC2_PHYIDX            0
 321 #define TSEC1_FLAGS             TSEC_GIGABIT
 322 #define TSEC2_FLAGS             TSEC_GIGABIT
 323
 324 /* Options are: TSEC[0-1] */
 325 #define CONFIG_ETHPRIME         "TSEC0"
 326
 327 #endif  /* CONFIG_TSEC_ENET */
 328
 329 /*
 330  * Environment
 331  */
 332 #define CONFIG_ENV_IS_IN_FLASH  1
 333 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 334 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 335 #define CONFIG_ENV_SIZE         0x2000
 336
 337 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 338 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 339
 340 /*
 341  * BOOTP options
 342  */
 343 #define CONFIG_BOOTP_BOOTFILESIZE
 344 #define CONFIG_BOOTP_BOOTPATH
 345 #define CONFIG_BOOTP_GATEWAY
 346 #define CONFIG_BOOTP_HOSTNAME
 347
 348 /*
 349  * Command line configuration.
 350  */
 351 #define CONFIG_CMD_IRQ
 352 #define CONFIG_CMD_REGINFO
 353
 354 #if defined(CONFIG_PCI)
 355     #define CONFIG_CMD_PCI
 356 #endif
 357
 358 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 359
 360 /*
 361  * Miscellaneous configurable options
 362  */
 363 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 364 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 365 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 366 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 367 #if defined(CONFIG_CMD_KGDB)
 368 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 369 #else
 370 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 371 #endif
 372 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 373 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 374 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 375
 376 /*
 377  * For booting Linux, the board info and command line data
 378  * have to be in the first 64 MB of memory, since this is
 379  * the maximum mapped by the Linux kernel during initialization.
 380  */
 381 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 382 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 383
 384 #if defined(CONFIG_CMD_KGDB)
 385 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 386 #endif
 387
 388 /*
 389  * Environment Configuration
 390  */
 391 #if defined(CONFIG_TSEC_ENET)
 392 #define CONFIG_HAS_ETH0
 393 #define CONFIG_HAS_ETH1
 394 #define CONFIG_HAS_ETH2
 395 #endif
 396
 397 #define CONFIG_IPADDR    192.168.1.253
 398
 399 #define CONFIG_HOSTNAME  unknown
 400 #define CONFIG_ROOTPATH  "/nfsroot"
 401 #define CONFIG_BOOTFILE  "your.uImage"
 402
 403 #define CONFIG_SERVERIP  192.168.1.1
 404 #define CONFIG_GATEWAYIP 192.168.1.1
 405 #define CONFIG_NETMASK   255.255.255.0
 406
 407 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 408
 409 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 410
 411 #define CONFIG_BAUDRATE 115200
 412
 413 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 414    "netdev=eth0\0"                                                      \
 415    "consoledev=ttyS1\0"                                                 \
 416    "ramdiskaddr=600000\0"                                               \
 417    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 418    "fdtaddr=400000\0"                                                   \
 419    "fdtfile=your.fdt.dtb\0"
 420
 421 #define CONFIG_NFSBOOTCOMMAND                                           \
 422    "setenv bootargs root=/dev/nfs rw "                                  \
 423       "nfsroot=$serverip:$rootpath "                                    \
 424       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 425       "console=$consoledev,$baudrate $othbootargs;"                     \
 426    "tftp $loadaddr $bootfile;"                                          \
 427    "tftp $fdtaddr $fdtfile;"                                            \
 428    "bootm $loadaddr - $fdtaddr"
 429
 430 #define CONFIG_RAMBOOTCOMMAND \
 431    "setenv bootargs root=/dev/ram rw "                                  \
 432       "console=$consoledev,$baudrate $othbootargs;"                     \
 433    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 434    "tftp $loadaddr $bootfile;"                                          \
 435    "bootm $loadaddr $ramdiskaddr"
 436
 437 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 438
 439 #endif  /* __CONFIG_H */