include/configs/MPC8568MDS.h

   1 /*
   2  * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8568mds board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 /* High Level Configuration Options */
  16 #define CONFIG_BOOKE            1       /* BOOKE */
  17 #define CONFIG_E500             1       /* BOOKE e500 family */
  18 #define CONFIG_MPC8568          1       /* MPC8568 specific */
  19 #define CONFIG_MPC8568MDS       1       /* MPC8568MDS board specific */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  22
  23 #define CONFIG_SYS_SRIO
  24 #define CONFIG_SRIO1                    /* SRIO port 1 */
  25
  26 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  27 #define CONFIG_PCI1             1       /* PCI controller */
  28 #define CONFIG_PCIE1            1       /* PCIE controller */
  29 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  30 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  31 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  32 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  33 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  34 #define CONFIG_QE                       /* Enable QE */
  35 #define CONFIG_ENV_OVERWRITE
  36 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  37
  38 #ifndef __ASSEMBLY__
  39 extern unsigned long get_clock_freq(void);
  40 #endif                                            /*Replace a call to get_clock_freq (after it is implemented)*/
  41 #define CONFIG_SYS_CLK_FREQ     66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  42
  43 /*
  44  * These can be toggled for performance analysis, otherwise use default.
  45  */
  46 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  47 #define CONFIG_BTB                              /* toggle branch predition */
  48
  49 /*
  50  * Only possible on E500 Version 2 or newer cores.
  51  */
  52 #define CONFIG_ENABLE_36BIT_PHYS        1
  53
  54
  55 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  56
  57 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  58 #define CONFIG_SYS_MEMTEST_END          0x00400000
  59
  60 #define CONFIG_SYS_CCSRBAR              0xe0000000
  61 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  62
  63 /* DDR Setup */
  64 #define CONFIG_SYS_FSL_DDR2
  65 #undef CONFIG_FSL_DDR_INTERACTIVE
  66 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  67 #define CONFIG_DDR_SPD
  68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  69
  70 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  71
  72 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  73 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  74
  75 #define CONFIG_NUM_DDR_CONTROLLERS      1
  76 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  77 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  78
  79 /* I2C addresses of SPD EEPROMs */
  80 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  81
  82 /* Make sure required options are set */
  83 #ifndef CONFIG_SPD_EEPROM
  84 #error ("CONFIG_SPD_EEPROM is required")
  85 #endif
  86
  87 #undef CONFIG_CLOCKS_IN_MHZ
  88
  89 /*
  90  * Local Bus Definitions
  91  */
  92
  93 /*
  94  * FLASH on the Local Bus
  95  * Two banks, 8M each, using the CFI driver.
  96  * Boot from BR0/OR0 bank at 0xff00_0000
  97  * Alternate BR1/OR1 bank at 0xff80_0000
  98  *
  99  * BR0, BR1:
 100  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 101  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 102  *    Port Size = 16 bits = BRx[19:20] = 10
 103  *    Use GPCM = BRx[24:26] = 000
 104  *    Valid = BRx[31] = 1
 105  *
 106  * 0    4    8    12   16   20   24   28
 107  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 108  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 109  *
 110  * OR0, OR1:
 111  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 112  *    Reserved ORx[17:18] = 11, confusion here?
 113  *    CSNT = ORx[20] = 1
 114  *    ACS = half cycle delay = ORx[21:22] = 11
 115  *    SCY = 6 = ORx[24:27] = 0110
 116  *    TRLX = use relaxed timing = ORx[29] = 1
 117  *    EAD = use external address latch delay = OR[31] = 1
 118  *
 119  * 0    4    8    12   16   20   24   28
 120  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 121  */
 122 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 123
 124 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 125
 126 /*Chip select 0 - Flash*/
 127 #define CONFIG_SYS_BR0_PRELIM           0xfe001001
 128 #define CONFIG_SYS_OR0_PRELIM           0xfe006ff7
 129
 130 /*Chip slelect 1 - BCSR*/
 131 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 132 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 133
 134 /*#define CONFIG_SYS_FLASH_BANKS_LIST   {0xff800000, CONFIG_SYS_FLASH_BASE} */
 135 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* number of banks */
 136 #define CONFIG_SYS_MAX_FLASH_SECT               512             /* sectors per device */
 137 #undef  CONFIG_SYS_FLASH_CHECKSUM
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 140
 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 142
 143 #define CONFIG_FLASH_CFI_DRIVER
 144 #define CONFIG_SYS_FLASH_CFI
 145 #define CONFIG_SYS_FLASH_EMPTY_INFO
 146
 147
 148 /*
 149  * SDRAM on the LocalBus
 150  */
 151 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM        */
 152 #define CONFIG_SYS_LBC_SDRAM_SIZE       64                      /* LBC SDRAM is 64MB */
 153
 154
 155 /*Chip select 2 - SDRAM*/
 156 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
 157 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 158
 159 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 160 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 161 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 162 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 163
 164 /*
 165  * Common settings for all Local Bus SDRAM commands.
 166  * At run time, either BSMA1516 (for CPU 1.1)
 167  *                  or BSMA1617 (for CPU 1.0) (old)
 168  * is OR'ed in too.
 169  */
 170 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 171                                 | LSDMR_PRETOACT7       \
 172                                 | LSDMR_ACTTORW7        \
 173                                 | LSDMR_BL8             \
 174                                 | LSDMR_WRC4            \
 175                                 | LSDMR_CL3             \
 176                                 | LSDMR_RFEN            \
 177                                 )
 178
 179 /*
 180  * The bcsr registers are connected to CS3 on MDS.
 181  * The new memory map places bcsr at 0xf8000000.
 182  *
 183  * For BR3, need:
 184  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 185  *    port-size = 8-bits  = BR[19:20] = 01
 186  *    no parity checking  = BR[21:22] = 00
 187  *    GPMC for MSEL       = BR[24:26] = 000
 188  *    Valid               = BR[31]    = 1
 189  *
 190  * 0    4    8    12   16   20   24   28
 191  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 192  *
 193  * For OR3, need:
 194  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 195  *    disable buffer ctrl OR[19]    = 0
 196  *    CSNT                OR[20]    = 1
 197  *    ACS                 OR[21:22] = 11
 198  *    XACS                OR[23]    = 1
 199  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 200  *    SETA                OR[28]    = 0
 201  *    TRLX                OR[29]    = 1
 202  *    EHTR                OR[30]    = 1
 203  *    EAD extra time      OR[31]    = 1
 204  *
 205  * 0    4    8    12   16   20   24   28
 206  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 207  */
 208 #define CONFIG_SYS_BCSR (0xf8000000)
 209
 210 /*Chip slelect 4 - PIB*/
 211 #define CONFIG_SYS_BR4_PRELIM   0xf8008801
 212 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
 213
 214 /*Chip select 5 - PIB*/
 215 #define CONFIG_SYS_BR5_PRELIM    0xf8010801
 216 #define CONFIG_SYS_OR5_PRELIM    0xffff69f7
 217
 218 #define CONFIG_SYS_INIT_RAM_LOCK        1
 219 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 220 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 221
 222 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 223 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 224
 225 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 226 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 227
 228 /* Serial Port */
 229 #define CONFIG_CONS_INDEX               1
 230 #define CONFIG_SYS_NS16550_SERIAL
 231 #define CONFIG_SYS_NS16550_REG_SIZE    1
 232 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 233
 234 #define CONFIG_SYS_BAUDRATE_TABLE  \
 235         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 236
 237 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 238 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 239
 240 /*
 241  * I2C
 242  */
 243 #define CONFIG_SYS_I2C
 244 #define CONFIG_SYS_I2C_FSL
 245 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 246 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 247 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 248 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 249 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 250 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 251 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 253
 254 /*
 255  * General PCI
 256  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 257  */
 258 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 259 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 260 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 261 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 262 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 263 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 264 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 265 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000      /* 8M */
 266
 267 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 268 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 269 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 270 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 271 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 272 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 273 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 274 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 275 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 276
 277 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 278 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 279 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 280 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 281
 282 #ifdef CONFIG_QE
 283 /*
 284  * QE UEC ethernet configuration
 285  */
 286 #define CONFIG_UEC_ETH
 287 #ifndef CONFIG_TSEC_ENET
 288 #define CONFIG_ETHPRIME         "UEC0"
 289 #endif
 290 #define CONFIG_PHY_MODE_NEED_CHANGE
 291 #define CONFIG_eTSEC_MDIO_BUS
 292
 293 #ifdef CONFIG_eTSEC_MDIO_BUS
 294 #define CONFIG_MIIM_ADDRESS     0xE0024520
 295 #endif
 296
 297 #define CONFIG_UEC_ETH1         /* GETH1 */
 298
 299 #ifdef CONFIG_UEC_ETH1
 300 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 301 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 302 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 303 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 304 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 305 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 306 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 307 #endif
 308
 309 #define CONFIG_UEC_ETH2         /* GETH2 */
 310
 311 #ifdef CONFIG_UEC_ETH2
 312 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 313 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 314 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 315 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 316 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 317 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 318 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 319 #endif
 320 #endif /* CONFIG_QE */
 321
 322 #if defined(CONFIG_PCI)
 323
 324 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 325
 326 #undef CONFIG_EEPRO100
 327 #undef CONFIG_TULIP
 328
 329 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 330 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 331
 332 #endif  /* CONFIG_PCI */
 333
 334 #if defined(CONFIG_TSEC_ENET)
 335
 336 #define CONFIG_MII              1       /* MII PHY management */
 337 #define CONFIG_TSEC1    1
 338 #define CONFIG_TSEC1_NAME       "eTSEC0"
 339 #define CONFIG_TSEC2    1
 340 #define CONFIG_TSEC2_NAME       "eTSEC1"
 341
 342 #define TSEC1_PHY_ADDR          2
 343 #define TSEC2_PHY_ADDR          3
 344
 345 #define TSEC1_PHYIDX            0
 346 #define TSEC2_PHYIDX            0
 347
 348 #define TSEC1_FLAGS             TSEC_GIGABIT
 349 #define TSEC2_FLAGS             TSEC_GIGABIT
 350
 351 /* Options are: eTSEC[0-1] */
 352 #define CONFIG_ETHPRIME         "eTSEC0"
 353
 354 #endif  /* CONFIG_TSEC_ENET */
 355
 356 /*
 357  * Environment
 358  */
 359 #define CONFIG_ENV_IS_IN_FLASH  1
 360 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 361 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 362 #define CONFIG_ENV_SIZE         0x2000
 363
 364 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 365 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 366
 367
 368 /*
 369  * BOOTP options
 370  */
 371 #define CONFIG_BOOTP_BOOTFILESIZE
 372 #define CONFIG_BOOTP_BOOTPATH
 373 #define CONFIG_BOOTP_GATEWAY
 374 #define CONFIG_BOOTP_HOSTNAME
 375
 376
 377 /*
 378  * Command line configuration.
 379  */
 380 #define CONFIG_CMD_PING
 381 #define CONFIG_CMD_I2C
 382 #define CONFIG_CMD_MII
 383 #define CONFIG_CMD_IRQ
 384 #define CONFIG_CMD_REGINFO
 385
 386 #if defined(CONFIG_PCI)
 387     #define CONFIG_CMD_PCI
 388 #endif
 389
 390
 391 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 392
 393 /*
 394  * Miscellaneous configurable options
 395  */
 396 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 397 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 398 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 399 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 400 #if defined(CONFIG_CMD_KGDB)
 401 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 402 #else
 403 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size */
 404 #endif
 405 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 406 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 407 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 408
 409 /*
 410  * For booting Linux, the board info and command line data
 411  * have to be in the first 64 MB of memory, since this is
 412  * the maximum mapped by the Linux kernel during initialization.
 413  */
 414 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 415 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 416
 417 #if defined(CONFIG_CMD_KGDB)
 418 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 419 #endif
 420
 421 /*
 422  * Environment Configuration
 423  */
 424
 425 /* The mac addresses for all ethernet interface */
 426 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
 427 #define CONFIG_HAS_ETH0
 428 #define CONFIG_HAS_ETH1
 429 #define CONFIG_HAS_ETH2
 430 #define CONFIG_HAS_ETH3
 431 #endif
 432
 433 #define CONFIG_IPADDR    192.168.1.253
 434
 435 #define CONFIG_HOSTNAME  unknown
 436 #define CONFIG_ROOTPATH  "/nfsroot"
 437 #define CONFIG_BOOTFILE  "your.uImage"
 438
 439 #define CONFIG_SERVERIP  192.168.1.1
 440 #define CONFIG_GATEWAYIP 192.168.1.1
 441 #define CONFIG_NETMASK   255.255.255.0
 442
 443 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 444
 445 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 446 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 447
 448 #define CONFIG_BAUDRATE 115200
 449
 450 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 451    "netdev=eth0\0"                                                      \
 452    "consoledev=ttyS0\0"                                                 \
 453    "ramdiskaddr=600000\0"                                               \
 454    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 455    "fdtaddr=400000\0"                                                   \
 456    "fdtfile=your.fdt.dtb\0"                                             \
 457    "nfsargs=setenv bootargs root=/dev/nfs rw "                          \
 458       "nfsroot=$serverip:$rootpath "                                    \
 459       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 460       "console=$consoledev,$baudrate $othbootargs\0"                    \
 461    "ramargs=setenv bootargs root=/dev/ram rw "                          \
 462       "console=$consoledev,$baudrate $othbootargs\0"                    \
 463
 464
 465 #define CONFIG_NFSBOOTCOMMAND                                           \
 466    "run nfsargs;"                                                       \
 467    "tftp $loadaddr $bootfile;"                                          \
 468    "tftp $fdtaddr $fdtfile;"                                            \
 469    "bootm $loadaddr - $fdtaddr"
 470
 471
 472 #define CONFIG_RAMBOOTCOMMAND \
 473    "run ramargs;"                                                       \
 474    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 475    "tftp $loadaddr $bootfile;"                                          \
 476    "bootm $loadaddr $ramdiskaddr"
 477
 478 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 479
 480 #endif  /* __CONFIG_H */