include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_P2041RDB
  15 #define CONFIG_PHYS_64BIT
  16 #define CONFIG_DISPLAY_BOARDINFO
  17 #define CONFIG_PPC_P2041
  18
  19 #ifdef CONFIG_RAMBOOT_PBL
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  24 #endif
  25
  26 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  27 /* Set 1M boot space */
  28 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  29 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  30                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  32 #define CONFIG_SYS_NO_FLASH
  33 #endif
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_BOOKE
  37 #define CONFIG_E500                     /* BOOKE e500 family */
  38 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  39 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  40 #define CONFIG_MP                       /* support multiple processors */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  44 #endif
  45
  46 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  47 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  48 #endif
  49
  50 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  51 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  52 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  53 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  54 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  55 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  56 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  57 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  58 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  59 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  60
  61 #define CONFIG_SYS_SRIO
  62 #define CONFIG_SRIO1                    /* SRIO port 1 */
  63 #define CONFIG_SRIO2                    /* SRIO port 2 */
  64 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  65 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  66
  67 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  68
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #ifdef CONFIG_SYS_NO_FLASH
  72 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  73 #define CONFIG_ENV_IS_NOWHERE
  74 #endif
  75 #else
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  79 #endif
  80
  81 #if defined(CONFIG_SPIFLASH)
  82         #define CONFIG_SYS_EXTRA_ENV_RELOC
  83         #define CONFIG_ENV_IS_IN_SPI_FLASH
  84         #define CONFIG_ENV_SPI_BUS              0
  85         #define CONFIG_ENV_SPI_CS               0
  86         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  87         #define CONFIG_ENV_SPI_MODE             0
  88         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  89         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  90         #define CONFIG_ENV_SECT_SIZE            0x10000
  91 #elif defined(CONFIG_SDCARD)
  92         #define CONFIG_SYS_EXTRA_ENV_RELOC
  93         #define CONFIG_ENV_IS_IN_MMC
  94         #define CONFIG_FSL_FIXED_MMC_LOCATION
  95         #define CONFIG_SYS_MMC_ENV_DEV          0
  96         #define CONFIG_ENV_SIZE                 0x2000
  97         #define CONFIG_ENV_OFFSET               (512 * 1658)
  98 #elif defined(CONFIG_NAND)
  99 #define CONFIG_SYS_EXTRA_ENV_RELOC
 100 #define CONFIG_ENV_IS_IN_NAND
 101 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 102 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 104 #define CONFIG_ENV_IS_IN_REMOTE
 105 #define CONFIG_ENV_ADDR         0xffe20000
 106 #define CONFIG_ENV_SIZE         0x2000
 107 #elif defined(CONFIG_ENV_IS_NOWHERE)
 108 #define CONFIG_ENV_SIZE         0x2000
 109 #else
 110         #define CONFIG_ENV_IS_IN_FLASH
 111         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 112                         - CONFIG_ENV_SECT_SIZE)
 113         #define CONFIG_ENV_SIZE         0x2000
 114         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 115 #endif
 116
 117 #ifndef __ASSEMBLY__
 118 unsigned long get_board_sys_clk(unsigned long dummy);
 119 #endif
 120 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 121
 122 /*
 123  * These can be toggled for performance analysis, otherwise use default.
 124  */
 125 #define CONFIG_SYS_CACHE_STASHING
 126 #define CONFIG_BACKSIDE_L2_CACHE
 127 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 128 #define CONFIG_BTB                      /* toggle branch predition */
 129
 130 #define CONFIG_ENABLE_36BIT_PHYS
 131
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_ADDR_MAP
 134 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 135 #endif
 136
 137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 138 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 139 #define CONFIG_SYS_MEMTEST_END          0x00400000
 140 #define CONFIG_SYS_ALT_MEMTEST
 141 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 142
 143 /*
 144  *  Config the L3 Cache as L3 SRAM
 145  */
 146 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 149                 CONFIG_RAMBOOT_TEXT_BASE)
 150 #else
 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 152 #endif
 153 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 155
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_DCSRBAR              0xf0000000
 158 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 159 #endif
 160
 161 /* EEPROM */
 162 #define CONFIG_ID_EEPROM
 163 #define CONFIG_SYS_I2C_EEPROM_NXID
 164 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 167
 168 /*
 169  * DDR Setup
 170  */
 171 #define CONFIG_VERY_BIG_RAM
 172 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 173 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 174
 175 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 176 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 177
 178 #define CONFIG_DDR_SPD
 179 #define CONFIG_SYS_FSL_DDR3
 180
 181 #define CONFIG_SYS_SPD_BUS_NUM  0
 182 #define SPD_EEPROM_ADDRESS      0x52
 183 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 184
 185 /*
 186  * Local Bus Definitions
 187  */
 188
 189 /* Set the local bus clock 1/8 of platform clock */
 190 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 191
 192 /*
 193  * This board doesn't have a promjet connector.
 194  * However, it uses commone corenet board LAW and TLB.
 195  * It is necessary to use the same start address with proper offset.
 196  */
 197 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 198 #ifdef CONFIG_PHYS_64BIT
 199 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 200 #else
 201 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 202 #endif
 203
 204 #define CONFIG_SYS_FLASH_BR_PRELIM \
 205                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 206                 BR_PS_16 | BR_V)
 207 #define CONFIG_SYS_FLASH_OR_PRELIM \
 208                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 209                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 210
 211 #define CONFIG_FSL_CPLD
 212 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 213 #ifdef CONFIG_PHYS_64BIT
 214 #define CPLD_BASE_PHYS          0xfffdf0000ull
 215 #else
 216 #define CPLD_BASE_PHYS          CPLD_BASE
 217 #endif
 218
 219 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 220 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 221
 222 #define PIXIS_LBMAP_SWITCH      7
 223 #define PIXIS_LBMAP_MASK        0xf0
 224 #define PIXIS_LBMAP_SHIFT       4
 225 #define PIXIS_LBMAP_ALTBANK     0x40
 226
 227 #define CONFIG_SYS_FLASH_QUIET_TEST
 228 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 229
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 234
 235 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 236
 237 #if defined(CONFIG_RAMBOOT_PBL)
 238 #define CONFIG_SYS_RAMBOOT
 239 #endif
 240
 241 #define CONFIG_NAND_FSL_ELBC
 242 /* Nand Flash */
 243 #ifdef CONFIG_NAND_FSL_ELBC
 244 #define CONFIG_SYS_NAND_BASE            0xffa00000
 245 #ifdef CONFIG_PHYS_64BIT
 246 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 247 #else
 248 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 249 #endif
 250
 251 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 252 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 253 #define CONFIG_CMD_NAND
 254 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 255
 256 /* NAND flash config */
 257 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 258                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 259                                | BR_PS_8               /* Port Size = 8 bit */ \
 260                                | BR_MS_FCM             /* MSEL = FCM */ \
 261                                | BR_V)                 /* valid */
 262 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 263                                | OR_FCM_PGS            /* Large Page*/ \
 264                                | OR_FCM_CSCT \
 265                                | OR_FCM_CST \
 266                                | OR_FCM_CHT \
 267                                | OR_FCM_SCY_1 \
 268                                | OR_FCM_TRLX \
 269                                | OR_FCM_EHTR)
 270
 271 #ifdef CONFIG_NAND
 272 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 273 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 274 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 275 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 276 #else
 277 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 278 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 279 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 280 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 281 #endif
 282 #else
 283 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 284 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 285 #endif /* CONFIG_NAND_FSL_ELBC */
 286
 287 #define CONFIG_SYS_FLASH_EMPTY_INFO
 288 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 289 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 290
 291 #define CONFIG_BOARD_EARLY_INIT_F
 292 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 293 #define CONFIG_MISC_INIT_R
 294
 295 #define CONFIG_HWCONFIG
 296
 297 /* define to use L1 as initial stack */
 298 #define CONFIG_L1_INIT_RAM
 299 #define CONFIG_SYS_INIT_RAM_LOCK
 300 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 301 #ifdef CONFIG_PHYS_64BIT
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 304 /* The assembler doesn't like typecast */
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 306         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 307           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 308 #else
 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 312 #endif
 313 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 314
 315 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 316                                         GENERATED_GBL_DATA_SIZE)
 317 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 318
 319 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 320 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 321
 322 /* Serial Port - controlled on board with jumper J8
 323  * open - index 2
 324  * shorted - index 1
 325  */
 326 #define CONFIG_CONS_INDEX       1
 327 #define CONFIG_SYS_NS16550_SERIAL
 328 #define CONFIG_SYS_NS16550_REG_SIZE     1
 329 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 330
 331 #define CONFIG_SYS_BAUDRATE_TABLE       \
 332         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 333
 334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 336 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 337 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 338
 339 /* Use the HUSH parser */
 340 #define CONFIG_SYS_HUSH_PARSER
 341
 342 /* pass open firmware flat tree */
 343 #define CONFIG_OF_BOARD_SETUP
 344 #define CONFIG_OF_STDOUT_VIA_ALIAS
 345
 346 /* new uImage format support */
 347 #define CONFIG_FIT
 348 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 349
 350 /* I2C */
 351 #define CONFIG_SYS_I2C
 352 #define CONFIG_SYS_I2C_FSL
 353 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 354 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 355 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 356 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 357 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 358 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 359
 360 /*
 361  * RapidIO
 362  */
 363 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 364 #ifdef CONFIG_PHYS_64BIT
 365 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 366 #else
 367 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 368 #endif
 369 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 370
 371 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 372 #ifdef CONFIG_PHYS_64BIT
 373 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 374 #else
 375 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 376 #endif
 377 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 378
 379 /*
 380  * for slave u-boot IMAGE instored in master memory space,
 381  * PHYS must be aligned based on the SIZE
 382  */
 383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 387 /*
 388  * for slave UCODE and ENV instored in master memory space,
 389  * PHYS must be aligned based on the SIZE
 390  */
 391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 392 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 393 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 394
 395 /* slave core release by master*/
 396 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 397 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 398
 399 /*
 400  * SRIO_PCIE_BOOT - SLAVE
 401  */
 402 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 403 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 404 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 405                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 406 #endif
 407
 408 /*
 409  * eSPI - Enhanced SPI
 410  */
 411 #define CONFIG_CMD_SF
 412 #define CONFIG_SF_DEFAULT_SPEED         10000000
 413 #define CONFIG_SF_DEFAULT_MODE          0
 414
 415 /*
 416  * General PCI
 417  * Memory space is mapped 1-1, but I/O space must start from 0.
 418  */
 419
 420 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 421 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 424 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 425 #else
 426 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 427 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 428 #endif
 429 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 430 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 431 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 432 #ifdef CONFIG_PHYS_64BIT
 433 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 434 #else
 435 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 436 #endif
 437 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 438
 439 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 440 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 441 #ifdef CONFIG_PHYS_64BIT
 442 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 443 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 444 #else
 445 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 446 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 447 #endif
 448 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 449 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 450 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 451 #ifdef CONFIG_PHYS_64BIT
 452 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 453 #else
 454 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 455 #endif
 456 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 457
 458 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 459 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 460 #ifdef CONFIG_PHYS_64BIT
 461 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 462 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 463 #else
 464 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 465 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 466 #endif
 467 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 468 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 469 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 470 #ifdef CONFIG_PHYS_64BIT
 471 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 472 #else
 473 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 474 #endif
 475 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 476
 477 /* Qman/Bman */
 478 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 479 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 480 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 481 #ifdef CONFIG_PHYS_64BIT
 482 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 483 #else
 484 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 485 #endif
 486 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 487 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 488 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 489 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 490 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 491 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 492                                         CONFIG_SYS_BMAN_CENA_SIZE)
 493 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 494 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 495 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 496 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 497 #ifdef CONFIG_PHYS_64BIT
 498 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 499 #else
 500 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 501 #endif
 502 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 503 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 504 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 505 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 506 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 507 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 508                                         CONFIG_SYS_QMAN_CENA_SIZE)
 509 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 510 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 511
 512 #define CONFIG_SYS_DPAA_FMAN
 513 #define CONFIG_SYS_DPAA_PME
 514 /* Default address of microcode for the Linux Fman driver */
 515 #if defined(CONFIG_SPIFLASH)
 516 /*
 517  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 518  * env, so we got 0x110000.
 519  */
 520 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 521 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 522 #elif defined(CONFIG_SDCARD)
 523 /*
 524  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 525  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 526  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 527  */
 528 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 529 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 530 #elif defined(CONFIG_NAND)
 531 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 532 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 533 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 534 /*
 535  * Slave has no ucode locally, it can fetch this from remote. When implementing
 536  * in two corenet boards, slave's ucode could be stored in master's memory
 537  * space, the address can be mapped from slave TLB->slave LAW->
 538  * slave SRIO or PCIE outbound window->master inbound window->
 539  * master LAW->the ucode address in master's memory space.
 540  */
 541 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 542 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 543 #else
 544 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 545 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 546 #endif
 547 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 548 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 549
 550 #ifdef CONFIG_SYS_DPAA_FMAN
 551 #define CONFIG_FMAN_ENET
 552 #define CONFIG_PHYLIB_10G
 553 #define CONFIG_PHY_VITESSE
 554 #define CONFIG_PHY_TERANETICS
 555 #endif
 556
 557 #ifdef CONFIG_PCI
 558 #define CONFIG_PCI_INDIRECT_BRIDGE
 559 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 560
 561 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 562 #define CONFIG_DOS_PARTITION
 563 #endif  /* CONFIG_PCI */
 564
 565 /* SATA */
 566 #define CONFIG_FSL_SATA_V2
 567
 568 #ifdef CONFIG_FSL_SATA_V2
 569 #define CONFIG_FSL_SATA
 570 #define CONFIG_LIBATA
 571
 572 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 573 #define CONFIG_SATA1
 574 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 575 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 576 #define CONFIG_SATA2
 577 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 578 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 579
 580 #define CONFIG_LBA48
 581 #define CONFIG_CMD_SATA
 582 #define CONFIG_DOS_PARTITION
 583 #define CONFIG_CMD_EXT2
 584 #endif
 585
 586 #ifdef CONFIG_FMAN_ENET
 587 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 588 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 589 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 590 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 591 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 592
 593 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 594 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 595 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 596 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 597
 598 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 599
 600 #define CONFIG_SYS_TBIPA_VALUE  8
 601 #define CONFIG_MII              /* MII PHY management */
 602 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 603 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 604 #endif
 605
 606 /*
 607  * Environment
 608  */
 609 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 610 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 611
 612 /*
 613  * Command line configuration.
 614  */
 615 #define CONFIG_CMD_DHCP
 616 #define CONFIG_CMD_ERRATA
 617 #define CONFIG_CMD_GREPENV
 618 #define CONFIG_CMD_IRQ
 619 #define CONFIG_CMD_I2C
 620 #define CONFIG_CMD_MII
 621 #define CONFIG_CMD_PING
 622
 623 #ifdef CONFIG_PCI
 624 #define CONFIG_CMD_PCI
 625 #endif
 626
 627 /*
 628 * USB
 629 */
 630 #define CONFIG_HAS_FSL_DR_USB
 631 #define CONFIG_HAS_FSL_MPH_USB
 632
 633 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 634 #define CONFIG_CMD_USB
 635 #define CONFIG_USB_STORAGE
 636 #define CONFIG_USB_EHCI
 637 #define CONFIG_USB_EHCI_FSL
 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 639 #endif
 640
 641 #define CONFIG_CMD_EXT2
 642
 643 #define CONFIG_MMC
 644
 645 #ifdef CONFIG_MMC
 646 #define CONFIG_FSL_ESDHC
 647 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 648 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 649 #define CONFIG_CMD_MMC
 650 #define CONFIG_GENERIC_MMC
 651 #define CONFIG_CMD_EXT2
 652 #define CONFIG_CMD_FAT
 653 #define CONFIG_DOS_PARTITION
 654 #endif
 655
 656 /* Hash command with SHA acceleration supported in hardware */
 657 #ifdef CONFIG_FSL_CAAM
 658 #define CONFIG_CMD_HASH
 659 #define CONFIG_SHA_HW_ACCEL
 660 #endif
 661
 662 /*
 663  * Miscellaneous configurable options
 664  */
 665 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 666 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 667 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 668 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 669 #ifdef CONFIG_CMD_KGDB
 670 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 671 #else
 672 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 673 #endif
 674 /* Print Buffer Size */
 675 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 676                                 sizeof(CONFIG_SYS_PROMPT)+16)
 677 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 678 /* Boot Argument Buffer Size */
 679 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 680
 681 /*
 682  * For booting Linux, the board info and command line data
 683  * have to be in the first 64 MB of memory, since this is
 684  * the maximum mapped by the Linux kernel during initialization.
 685  */
 686 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 687 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 688
 689 #ifdef CONFIG_CMD_KGDB
 690 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 691 #endif
 692
 693 /*
 694  * Environment Configuration
 695  */
 696 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 697 #define CONFIG_BOOTFILE         "uImage"
 698 #define CONFIG_UBOOTPATH        u-boot.bin
 699
 700 /* default location for tftp and bootm */
 701 #define CONFIG_LOADADDR         1000000
 702
 703 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 704
 705 #define CONFIG_BAUDRATE 115200
 706
 707 #define __USB_PHY_TYPE  utmi
 708
 709 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 710         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 711         "bank_intlv=cs0_cs1\0"                                  \
 712         "netdev=eth0\0"                                         \
 713         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 714         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 715         "tftpflash=tftpboot $loadaddr $uboot && "               \
 716         "protect off $ubootaddr +$filesize && "                 \
 717         "erase $ubootaddr +$filesize && "                       \
 718         "cp.b $loadaddr $ubootaddr $filesize && "               \
 719         "protect on $ubootaddr +$filesize && "                  \
 720         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 721         "consoledev=ttyS0\0"                                    \
 722         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 723         "usb_dr_mode=host\0"                                    \
 724         "ramdiskaddr=2000000\0"                                 \
 725         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 726         "fdtaddr=c00000\0"                                      \
 727         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 728         "bdev=sda3\0"
 729
 730 #define CONFIG_HDBOOT                                   \
 731         "setenv bootargs root=/dev/$bdev rw "           \
 732         "console=$consoledev,$baudrate $othbootargs;"   \
 733         "tftp $loadaddr $bootfile;"                     \
 734         "tftp $fdtaddr $fdtfile;"                       \
 735         "bootm $loadaddr - $fdtaddr"
 736
 737 #define CONFIG_NFSBOOTCOMMAND                   \
 738         "setenv bootargs root=/dev/nfs rw "     \
 739         "nfsroot=$serverip:$rootpath "          \
 740         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 741         "console=$consoledev,$baudrate $othbootargs;"   \
 742         "tftp $loadaddr $bootfile;"             \
 743         "tftp $fdtaddr $fdtfile;"               \
 744         "bootm $loadaddr - $fdtaddr"
 745
 746 #define CONFIG_RAMBOOTCOMMAND                           \
 747         "setenv bootargs root=/dev/ram rw "             \
 748         "console=$consoledev,$baudrate $othbootargs;"   \
 749         "tftp $ramdiskaddr $ramdiskfile;"               \
 750         "tftp $loadaddr $bootfile;"                     \
 751         "tftp $fdtaddr $fdtfile;"                       \
 752         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 753
 754 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 755
 756 #include <asm/fsl_secure_boot.h>
 757
 758 #endif  /* __CONFIG_H */