include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * File:                PATI.h
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  20 #define CONFIG_PATI             1               /* ...On a PATI board   */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  23
  24 /* Serial Console Configuration */
  25 #define CONFIG_5xx_CONS_SCI1
  26 #undef  CONFIG_5xx_CONS_SCI2
  27
  28 /*
  29  * BOOTP options
  30  */
  31 #define CONFIG_BOOTP_BOOTFILESIZE
  32 #define CONFIG_BOOTP_BOOTPATH
  33 #define CONFIG_BOOTP_GATEWAY
  34 #define CONFIG_BOOTP_HOSTNAME
  35
  36 /*
  37  * Command line configuration.
  38  */
  39 #define CONFIG_CMD_REGINFO
  40 #define CONFIG_CMD_REGINFO
  41 #define CONFIG_CMD_IRQ
  42
  43 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  44
  45 #define CONFIG_BOOTARGS         ""              /* */
  46
  47 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  48
  49 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  50
  51 /*
  52  * Miscellaneous configurable options
  53  */
  54 #define CONFIG_PREBOOT
  55
  56 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  57 #if defined(CONFIG_CMD_KGDB)
  58 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  59 #else
  60 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  61 #endif
  62 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  63 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
  64 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  65
  66 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
  67 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
  68
  69 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
  70
  71 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
  72
  73 /***********************************************************************
  74  * Last Stage Init
  75  ***********************************************************************/
  76 #define CONFIG_LAST_STAGE_INIT
  77
  78 /*
  79  * Low Level Configuration Settings
  80  */
  81
  82 /*
  83  * Internal Memory Mapped (This is not the IMMR content)
  84  */
  85 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
  86
  87 /*
  88  * Definitions for initial stack pointer and data area
  89  */
  90 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
  91 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
  92 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
  93 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
  94 /*
  95  * Start addresses for the final memory configuration
  96  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  97  */
  98 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
  99 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 100 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 101 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 102 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 103
 104 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 105 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 106                                                 /* This adress is given to the linker with -Ttext to    */
 107                                                 /* locate the text section at this adress.              */
 108 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 109 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 110
 111 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 112
 113 /*
 114  * For booting Linux, the board info and command line data
 115  * have to be in the first 8 MB of memory, since this is
 116  * the maximum mapped by the Linux kernel during initialization.
 117  */
 118 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 119
 120 /*-----------------------------------------------------------------------
 121  * FLASH organization
 122  *-----------------------------------------------------------------------
 123  *
 124  */
 125
 126 #define CONFIG_SYS_FLASH_PROTECTION
 127 #define CONFIG_SYS_FLASH_EMPTY_INFO
 128
 129 #define CONFIG_SYS_FLASH_CFI
 130 #define CONFIG_FLASH_CFI_DRIVER
 131
 132 #define CONFIG_FLASH_SHOW_PROGRESS      45
 133
 134 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 135 #define CONFIG_SYS_MAX_FLASH_SECT       128
 136
 137 #define CONFIG_ENV_IS_IN_EEPROM
 138 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 139 #define CONFIG_ENV_OFFSET               0
 140 #define CONFIG_ENV_SIZE         2048
 141 #endif
 142
 143 #undef  CONFIG_ENV_IS_IN_FLASH
 144 #ifdef  CONFIG_ENV_IS_IN_FLASH
 145 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 146 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 147 #endif
 148
 149 #define CONFIG_SPI              1
 150 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 151 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 152 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 153 /*-----------------------------------------------------------------------
 154  * SYPCR - System Protection Control
 155  * SYPCR can only be written once after reset!
 156  *-----------------------------------------------------------------------
 157  * SW Watchdog freeze
 158  */
 159 #undef CONFIG_WATCHDOG
 160 #if defined(CONFIG_WATCHDOG)
 161 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 162                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 163 #else
 164 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 165                          SYPCR_SWP)
 166 #endif  /* CONFIG_WATCHDOG */
 167
 168 /*-----------------------------------------------------------------------
 169  * TBSCR - Time Base Status and Control
 170  *-----------------------------------------------------------------------
 171  * Clear Reference Interrupt Status, Timebase freezing enabled
 172  */
 173 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 174
 175 /*-----------------------------------------------------------------------
 176  * PISCR - Periodic Interrupt Status and Control
 177  *-----------------------------------------------------------------------
 178  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 179  */
 180 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 181
 182 /*-----------------------------------------------------------------------
 183  * SCCR - System Clock and reset Control Register
 184  *-----------------------------------------------------------------------
 185  * Set clock output, timebase and RTC source and divider,
 186  * power management and some other internal clocks
 187  */
 188 #define SCCR_MASK       SCCR_EBDF00
 189 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 190                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 191
 192 /*-----------------------------------------------------------------------
 193  * SIUMCR - SIU Module Configuration
 194  *-----------------------------------------------------------------------
 195  * Data show cycle
 196  */
 197 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 198
 199 /*-----------------------------------------------------------------------
 200  * PLPRCR - PLL, Low-Power, and Reset Control Register
 201  *-----------------------------------------------------------------------
 202  * Set all bits to 40 Mhz
 203  *
 204  */
 205 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 206
 207 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 208
 209 /*-----------------------------------------------------------------------
 210  * UMCR - UIMB Module Configuration Register
 211  *-----------------------------------------------------------------------
 212  *
 213  */
 214 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 215
 216 /*-----------------------------------------------------------------------
 217  * ICTRL - I-Bus Support Control Register
 218  */
 219 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 220
 221 /*-----------------------------------------------------------------------
 222  * USIU - Memory Controller Register
 223  *-----------------------------------------------------------------------
 224  */
 225 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 226 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 227 /* SDRAM */
 228 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 229 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 230 /* PCI */
 231 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 232 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 233 /* config registers: */
 234 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 235 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 236
 237 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 238
 239 /*-----------------------------------------------------------------------
 240  * DER - Timer Decrementer
 241  *-----------------------------------------------------------------------
 242  * Initialise to zero
 243  */
 244 #define CONFIG_SYS_DER                  0x00000000
 245
 246 #endif  /* __CONFIG_H */