include/configs/PMC405DE.h

   1 /*
   2  * (C) Copyright 2009
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  12 #define CONFIG_PMC405DE         1       /* ...on a PMC405DE board       */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  17 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  18 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  19
  20 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  21
  22 #define CONFIG_BAUDRATE         115200
  23
  24 #undef  CONFIG_BOOTARGS
  25 #undef  CONFIG_BOOTCOMMAND
  26
  27 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  28
  29 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change*/
  30
  31 #define CONFIG_HAS_ETH1
  32
  33 #define CONFIG_PPC4xx_EMAC
  34 #define CONFIG_MII              1       /* MII PHY management           */
  35 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
  36 #define CONFIG_PHY1_ADDR        2       /* 2nd PHY address              */
  37
  38 #define CONFIG_SYS_RX_ETH_BUFFER        16 /* use 16 rx buffer on 405 emac */
  39
  40 /*
  41  * BOOTP options
  42  */
  43 #define CONFIG_BOOTP_SUBNETMASK
  44 #define CONFIG_BOOTP_GATEWAY
  45 #define CONFIG_BOOTP_HOSTNAME
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_DNS
  48 #define CONFIG_BOOTP_DNS2
  49 #define CONFIG_BOOTP_SEND_HOSTNAME
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #define CONFIG_CMD_BSP
  55 #define CONFIG_CMD_CHIP_CONFIG
  56 #define CONFIG_CMD_DATE
  57 #define CONFIG_CMD_EEPROM
  58 #define CONFIG_CMD_IRQ
  59 #define CONFIG_CMD_PCI
  60
  61 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
  62 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  63 #define CONFIG_PRAM             0
  64
  65 /*
  66  * Miscellaneous configurable options
  67  */
  68 #define CONFIG_SYS_LONGHELP
  69
  70 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
  71 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  72 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
  73 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  74
  75 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  76
  77 #define CONFIG_SYS_MEMTEST_START        0x0100000 /* memtest works on */
  78 #define CONFIG_SYS_MEMTEST_END          0x3000000 /* 1 ... 48 MB in DRAM */
  79
  80 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  81 #define CONFIG_SYS_NS16550_SERIAL
  82 #define CONFIG_SYS_NS16550_REG_SIZE     1
  83 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  84
  85 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK
  86 #define CONFIG_SYS_BASE_BAUD            691200
  87
  88 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  89 #define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
  90
  91 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
  92 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  93
  94 /*
  95  * PCI stuff
  96  */
  97 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
  98 #define PCI_HOST_FORCE          1       /* configure as pci host        */
  99 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 100
 101 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 102 #define CONFIG_PCI_HOST PCI_HOST_AUTO  /* select pci host function      */
 103 #define CONFIG_PCI_PNP          /* do (not) pci plug-and-play           */
 104
 105 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup          */
 106
 107 /*
 108  * PCI identification
 109  */
 110 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          PCI_VENDOR_ID_ESDGMBH
 111 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
 112 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
 113 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 114 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 115
 116 #define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
 117 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 118
 119 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
 120 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
 121 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
 122 #define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
 123 #define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
 124 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
 125
 126 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 127
 128 /*
 129  * For booting Linux, the board info and command line data
 130  * have to be in the first 8 MB of memory, since this is
 131  * the maximum mapped by the Linux kernel during initialization.
 132  */
 133 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 134 /*
 135  * FLASH organization
 136  */
 137 #define CONFIG_SYS_FLASH_CFI            1       /* CFI compatible */
 138 #define CONFIG_FLASH_CFI_DRIVER         1       /* Use common CFI driver */
 139
 140 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 141
 142 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max. no. memory banks */
 143 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per chip */
 144
 145 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* erase timeout (in ms) */
 146 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* write timeout (in ms) */
 147
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buffered writes (faster) */
 149 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection */
 150
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO     1 /* 'E' for empty sector (flinfo) */
 152 #define CONFIG_SYS_FLASH_QUIET_TEST     1 /* don't warn upon unknown flash */
 153
 154 /*
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 #define CONFIG_SYS_FLASH_BASE           0xfe000000
 161 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 162 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 163 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 164
 165 /*
 166  * Environment in EEPROM setup
 167  */
 168 #define CONFIG_ENV_IS_IN_EEPROM         1
 169 #define CONFIG_ENV_OFFSET               0x100
 170 #define CONFIG_ENV_SIZE                 0x700
 171
 172 /*
 173  * I2C EEPROM (24W16) for environment
 174  */
 175 #define CONFIG_SYS_I2C
 176 #define CONFIG_SYS_I2C_PPC4XX
 177 #define CONFIG_SYS_I2C_PPC4XX_CH0
 178 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 179 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 180
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24W16 */
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 183 /* mask of address bits that overflow into the "EEPROM chip address" */
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has */
 186                                         /* 16 byte page write mode using*/
 187                                         /* last 4 bits of the address */
 188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 189 #define CONFIG_SYS_EEPROM_WREN          1
 190
 191 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 192 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0x40
 193 #define CONFIG_4xx_CONFIG_BLOCKSIZE             0x20
 194
 195 /*
 196  * RTC
 197  */
 198 #define CONFIG_RTC_RX8025
 199
 200 /*
 201  * External Bus Controller (EBC) Setup
 202  * (max. 55MHZ EBC clock)
 203  */
 204 /* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
 205 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 206 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xba000)
 207
 208 /* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
 209 #define CONFIG_SYS_CPLD_BASE            0xef000000
 210 #define CONFIG_SYS_EBC_PB1AP            0x00800000
 211 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 212
 213 /*
 214  * Definitions for initial stack pointer and data area (in data cache)
 215  */
 216 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 217 #define CONFIG_SYS_TEMP_STACK_OCM         1
 218
 219 /* On Chip Memory location */
 220 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 221 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 222 /* inside SDRAM */
 223 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 224 /* End of used area in RAM */
 225 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 226
 227 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 228                                          GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 /*
 232  * GPIO Configuration
 233  */
 234 #define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
 235 {                                                                             \
 236 /* GPIO Core 0 */                                                             \
 237 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 238 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 239 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 240 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 241 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 242 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
 243 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
 244 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
 245 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 246 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
 247 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 248 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 249 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 250 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 251 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 252 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 253 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 254 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 255 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 256 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 257 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 258 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 259 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 260 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 261 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 262 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 263 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 264 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 265 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 266 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 267 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 268 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 269 }                                                                             \
 270 }
 271
 272 #define CONFIG_SYS_GPIO_HWREV_MASK      (0xf0000000 >> 1)       /* GPIO1..4 */
 273 #define CONFIG_SYS_GPIO_HWREV_SHIFT     27
 274 #define CONFIG_SYS_GPIO_LEDRUN_N        (0x80000000 >> 5)       /* GPIO5 */
 275 #define CONFIG_SYS_GPIO_LEDA_N          (0x80000000 >> 6)       /* GPIO6 */
 276 #define CONFIG_SYS_GPIO_LEDB_N          (0x80000000 >> 7)       /* GPIO7 */
 277 #define CONFIG_SYS_GPIO_SELFRST_N       (0x80000000 >> 8)       /* GPIO8 */
 278 #define CONFIG_SYS_GPIO_EEPROM_WP       (0x80000000 >> 9)       /* GPIO9 */
 279 #define CONFIG_SYS_GPIO_MONARCH_N       (0x80000000 >> 11)      /* GPIO11 */
 280 #define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 12)      /* GPIO12 */
 281 #define CONFIG_SYS_GPIO_M66EN           (0x80000000 >> 13)      /* GPIO13 */
 282
 283 /*
 284  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 285  * This value will be set if iic boot eprom is disabled.
 286  */
 287 #undef CONFIG_SYS_FCPU333MHZ
 288 #define CONFIG_SYS_FCPU266MHZ
 289 #undef CONFIG_SYS_FCPU133MHZ
 290
 291 #if defined(CONFIG_SYS_FCPU333MHZ)
 292 /*
 293  * CPU: 333MHz
 294  * PLB/SDRAM/MAL: 111MHz
 295  * OPB: 55MHz
 296  * EBC: 55MHz
 297  * PCI: 55MHz (111MHz on M66EN=1)
 298  */
 299 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |           \
 300                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |        \
 301                         PLL_MALDIV_1 | PLL_PCIDIV_2)
 302 #define PLLMR1_DEFAULT (PLL_FBKDIV_10  |                        \
 303                         PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 304                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 305 #endif
 306
 307 #if defined(CONFIG_SYS_FCPU266MHZ)
 308 /*
 309  * CPU: 266MHz
 310  * PLB/SDRAM/MAL: 133MHz
 311  * OPB: 66MHz
 312  * EBC: 44MHz
 313  * PCI: 44MHz (66MHz on M66EN=1)
 314  */
 315 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |           \
 316                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 317                         PLL_MALDIV_1 | PLL_PCIDIV_3)
 318 #define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
 319                         PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 320                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 321 #endif
 322
 323 #if defined(CONFIG_SYS_FCPU133MHZ)
 324 /*
 325  * CPU: 133MHz
 326  * PLB/SDRAM/MAL: 133MHz
 327  * OPB: 66MHz
 328  * EBC: 44MHz
 329  * PCI: 44MHz (66MHz on M66EN=1)
 330  */
 331 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |           \
 332                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 333                         PLL_MALDIV_1 | PLL_PCIDIV_3)
 334 #define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
 335                         PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |         \
 336                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 337 #endif
 338
 339 #endif /* __CONFIG_H */