include/configs/TQM823M.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_TQM823M          1       /* ...on a TQM8xxM module       */
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 #define CONFIG_SYS_TEXT_BASE    0x40000000
  25
  26 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  27 #define CONFIG_MPC8XX_LCD
  28 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display       */
  29 #endif
  30
  31 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  32 #define CONFIG_SYS_SMC_RXBUFLEN 128
  33 #define CONFIG_SYS_MAXIDLE      10
  34 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  35
  36 #define CONFIG_BOOTCOUNT_LIMIT
  37
  38 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  39
  40 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  41
  42 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  43
  44 #undef  CONFIG_BOOTARGS
  45
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         "netdev=eth0\0"                                                 \
  48         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  49                 "nfsroot=${serverip}:${rootpath}\0"                     \
  50         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  51         "addip=setenv bootargs ${bootargs} "                            \
  52                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  53                 ":${hostname}:${netdev}:off panic=1\0"                  \
  54         "flash_nfs=run nfsargs addip;"                                  \
  55                 "bootm ${kernel_addr}\0"                                \
  56         "flash_self=run ramargs addip;"                                 \
  57                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  58         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  59         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  60         "hostname=TQM823M\0"                                            \
  61         "bootfile=TQM823M/uImage\0"                                     \
  62         "fdt_addr=40080000\0"                                           \
  63         "kernel_addr=400A0000\0"                                        \
  64         "ramdisk_addr=40280000\0"                                       \
  65         "u-boot=TQM823M/u-image.bin\0"                                  \
  66         "load=tftp 200000 ${u-boot}\0"                                  \
  67         "update=prot off 40000000 +${filesize};"                        \
  68                 "era 40000000 +${filesize};"                            \
  69                 "cp.b 200000 40000000 ${filesize};"                     \
  70                 "sete filesize;save\0"                                  \
  71         ""
  72 #define CONFIG_BOOTCOMMAND      "run flash_self"
  73
  74 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  75 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #ifdef CONFIG_LCD
  80 # undef  CONFIG_STATUS_LED              /* disturbs display             */
  81 #else
  82 # define CONFIG_STATUS_LED      1       /* Status LED enabled           */
  83 #endif  /* CONFIG_LCD */
  84
  85 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  86
  87 /*
  88  * BOOTP options
  89  */
  90 #define CONFIG_BOOTP_SUBNETMASK
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95
  96
  97 #define CONFIG_MAC_PARTITION
  98 #define CONFIG_DOS_PARTITION
  99
 100 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 101
 102
 103 /*
 104  * Command line configuration.
 105  */
 106 #define CONFIG_CMD_ASKENV
 107 #define CONFIG_CMD_DATE
 108 #define CONFIG_CMD_DHCP
 109 #define CONFIG_CMD_EXT2
 110 #define CONFIG_CMD_IDE
 111 #define CONFIG_CMD_JFFS2
 112 #define CONFIG_CMD_SNTP
 113
 114
 115 #define CONFIG_NETCONSOLE
 116
 117
 118 /*
 119  * Miscellaneous configurable options
 120  */
 121 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 122
 123 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 124
 125 #if defined(CONFIG_CMD_KGDB)
 126 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 127 #else
 128 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 129 #endif
 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 131 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 132 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 133
 134 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 135 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 136
 137 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 138
 139 /*
 140  * Low Level Configuration Settings
 141  * (address mappings, register initial values, etc.)
 142  * You should know what you are doing if you make changes here.
 143  */
 144 /*-----------------------------------------------------------------------
 145  * Internal Memory Mapped Register
 146  */
 147 #define CONFIG_SYS_IMMR         0xFFF00000
 148
 149 /*-----------------------------------------------------------------------
 150  * Definitions for initial stack pointer and data area (in DPRAM)
 151  */
 152 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 153 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 154 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 155 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 /*-----------------------------------------------------------------------
 158  * Start addresses for the final memory configuration
 159  * (Set up by the startup code)
 160  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 161  */
 162 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 163 #define CONFIG_SYS_FLASH_BASE           0x40000000
 164 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 166 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 167
 168 /*
 169  * For booting Linux, the board info and command line data
 170  * have to be in the first 8 MB of memory, since this is
 171  * the maximum mapped by the Linux kernel during initialization.
 172  */
 173 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 174
 175 /*-----------------------------------------------------------------------
 176  * FLASH organization
 177  */
 178
 179 /* use CFI flash driver */
 180 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 181 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 182 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 183 #define CONFIG_SYS_FLASH_EMPTY_INFO
 184 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 186 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 187
 188 #define CONFIG_ENV_IS_IN_FLASH  1
 189 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 190 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 191 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 192
 193 /* Address and size of Redundant Environment Sector     */
 194 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 195 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 196
 197 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 198
 199 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 200
 201 /*-----------------------------------------------------------------------
 202  * Dynamic MTD partition support
 203  */
 204 #define CONFIG_CMD_MTDPARTS
 205 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 206 #define CONFIG_FLASH_CFI_MTD
 207 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 208
 209 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 210                                                 "128k(dtb),"            \
 211                                                 "1920k(kernel),"        \
 212                                                 "5632(rootfs),"         \
 213                                                 "4m(data)"
 214
 215 /*-----------------------------------------------------------------------
 216  * Hardware Information Block
 217  */
 218 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 219 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 220 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 221
 222 /*-----------------------------------------------------------------------
 223  * Cache Configuration
 224  */
 225 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 226 #if defined(CONFIG_CMD_KGDB)
 227 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 228 #endif
 229
 230 /*-----------------------------------------------------------------------
 231  * SYPCR - System Protection Control                            11-9
 232  * SYPCR can only be written once after reset!
 233  *-----------------------------------------------------------------------
 234  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 235  */
 236 #if defined(CONFIG_WATCHDOG)
 237 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 238                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 239 #else
 240 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 241 #endif
 242
 243 /*-----------------------------------------------------------------------
 244  * SIUMCR - SIU Module Configuration                            11-6
 245  *-----------------------------------------------------------------------
 246  * PCMCIA config., multi-function pin tri-state
 247  */
 248 #ifndef CONFIG_CAN_DRIVER
 249 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 250 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 251 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 252 #endif  /* CONFIG_CAN_DRIVER */
 253
 254 /*-----------------------------------------------------------------------
 255  * TBSCR - Time Base Status and Control                         11-26
 256  *-----------------------------------------------------------------------
 257  * Clear Reference Interrupt Status, Timebase freezing enabled
 258  */
 259 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 260
 261 /*-----------------------------------------------------------------------
 262  * RTCSC - Real-Time Clock Status and Control Register          11-27
 263  *-----------------------------------------------------------------------
 264  */
 265 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 266
 267 /*-----------------------------------------------------------------------
 268  * PISCR - Periodic Interrupt Status and Control                11-31
 269  *-----------------------------------------------------------------------
 270  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 271  */
 272 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 273
 274 /*-----------------------------------------------------------------------
 275  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 276  *-----------------------------------------------------------------------
 277  * Reset PLL lock status sticky bit, timer expired status bit and timer
 278  * interrupt status bit
 279  */
 280 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 281
 282 /*-----------------------------------------------------------------------
 283  * SCCR - System Clock and reset Control Register               15-27
 284  *-----------------------------------------------------------------------
 285  * Set clock output, timebase and RTC source and divider,
 286  * power management and some other internal clocks
 287  */
 288 #define SCCR_MASK       SCCR_EBDF11
 289 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 290                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 291                          SCCR_DFALCD00)
 292
 293 /*-----------------------------------------------------------------------
 294  * PCMCIA stuff
 295  *-----------------------------------------------------------------------
 296  *
 297  */
 298 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 299 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 300 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 301 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 302 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 303 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 304 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 305 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 306
 307 /*-----------------------------------------------------------------------
 308  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 309  *-----------------------------------------------------------------------
 310  */
 311
 312 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 313 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 314
 315 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 316 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 317 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 318
 319 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 320 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 321
 322 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 323
 324 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 325
 326 /* Offset for data I/O                  */
 327 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 328
 329 /* Offset for normal register accesses  */
 330 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 331
 332 /* Offset for alternate registers       */
 333 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 334
 335 /*-----------------------------------------------------------------------
 336  *
 337  *-----------------------------------------------------------------------
 338  *
 339  */
 340 #define CONFIG_SYS_DER  0
 341
 342 /*
 343  * Init Memory Controller:
 344  *
 345  * BR0/1 and OR0/1 (FLASH)
 346  */
 347
 348 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 349 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 350
 351 /* used to re-map FLASH both when starting from SRAM or FLASH:
 352  * restrict access enough to keep SRAM working (if any)
 353  * but not too much to meddle with FLASH accesses
 354  */
 355 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 356 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 357
 358 /*
 359  * FLASH timing:
 360  */
 361 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 362                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 363
 364 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 365 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 366 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 367
 368 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 369 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 370 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 371
 372 /*
 373  * BR2/3 and OR2/3 (SDRAM)
 374  *
 375  */
 376 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 377 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 378 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 379
 380 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 381 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 382
 383 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 384 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 385
 386 #ifndef CONFIG_CAN_DRIVER
 387 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 388 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 389 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 390 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 391 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 392 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 393 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 394                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 395 #endif  /* CONFIG_CAN_DRIVER */
 396
 397 /*
 398  * Memory Periodic Timer Prescaler
 399  *
 400  * The Divider for PTA (refresh timer) configuration is based on an
 401  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 402  * the number of chip selects (NCS) and the actually needed refresh
 403  * rate is done by setting MPTPR.
 404  *
 405  * PTA is calculated from
 406  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 407  *
 408  *      gclk      CPU clock (not bus clock!)
 409  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 410  *
 411  * 4096  Rows from SDRAM example configuration
 412  * 1000  factor s -> ms
 413  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 414  *    4  Number of refresh cycles per period
 415  *   64  Refresh cycle in ms per number of rows
 416  * --------------------------------------------
 417  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 418  *
 419  * 50 MHz => 50.000.000 / Divider =  98
 420  * 66 Mhz => 66.000.000 / Divider = 129
 421  * 80 Mhz => 80.000.000 / Divider = 156
 422  */
 423
 424 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 425 #define CONFIG_SYS_MAMR_PTA     98
 426
 427 /*
 428  * For 16 MBit, refresh rates could be 31.3 us
 429  * (= 64 ms / 2K = 125 / quad bursts).
 430  * For a simpler initialization, 15.6 us is used instead.
 431  *
 432  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 433  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 434  */
 435 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 436 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 437
 438 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 439 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 440 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 441
 442 /*
 443  * MAMR settings for SDRAM
 444  */
 445
 446 /* 8 column SDRAM */
 447 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 448                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 449                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 450 /* 9 column SDRAM */
 451 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 452                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 453                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 454
 455 #define CONFIG_HWCONFIG         1
 456
 457 #endif  /* __CONFIG_H */