include/configs/TQM855L.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  21 #define CONFIG_TQM855L          1       /* ...on a TQM8xxL module       */
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 #define CONFIG_SYS_TEXT_BASE    0x40000000
  25
  26 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  27 #define CONFIG_SYS_SMC_RXBUFLEN 128
  28 #define CONFIG_SYS_MAXIDLE      10
  29 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  30
  31 #define CONFIG_BOOTCOUNT_LIMIT
  32
  33 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  34
  35 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  36
  37 #define CONFIG_PREBOOT  "echo;" \
  38         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  39         "echo"
  40
  41 #undef  CONFIG_BOOTARGS
  42
  43 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  44         "netdev=eth0\0"                                                 \
  45         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  46                 "nfsroot=${serverip}:${rootpath}\0"                     \
  47         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  48         "addip=setenv bootargs ${bootargs} "                            \
  49                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  50                 ":${hostname}:${netdev}:off panic=1\0"                  \
  51         "flash_nfs=run nfsargs addip;"                                  \
  52                 "bootm ${kernel_addr}\0"                                \
  53         "flash_self=run ramargs addip;"                                 \
  54                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  55         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  56         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  57         "hostname=TQM855L\0"                                            \
  58         "bootfile=TQM855L/uImage\0"                                     \
  59         "fdt_addr=40040000\0"                                           \
  60         "kernel_addr=40060000\0"                                        \
  61         "ramdisk_addr=40200000\0"                                       \
  62         "u-boot=TQM855L/u-image.bin\0"                                  \
  63         "load=tftp 200000 ${u-boot}\0"                                  \
  64         "update=prot off 40000000 +${filesize};"                        \
  65                 "era 40000000 +${filesize};"                            \
  66                 "cp.b 200000 40000000 ${filesize};"                     \
  67                 "sete filesize;save\0"                                  \
  68         ""
  69 #define CONFIG_BOOTCOMMAND      "run flash_self"
  70
  71 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  72 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  73
  74 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  75
  76 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  77
  78 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88
  89
  90 #define CONFIG_MAC_PARTITION
  91 #define CONFIG_DOS_PARTITION
  92
  93 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  94
  95
  96 /*
  97  * Command line configuration.
  98  */
  99 #define CONFIG_CMD_ASKENV
 100 #define CONFIG_CMD_DATE
 101 #define CONFIG_CMD_DHCP
 102 #define CONFIG_CMD_EXT2
 103 #define CONFIG_CMD_IDE
 104 #define CONFIG_CMD_JFFS2
 105 #define CONFIG_CMD_SNTP
 106
 107
 108 #define CONFIG_NETCONSOLE
 109
 110
 111 /*
 112  * Miscellaneous configurable options
 113  */
 114 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 115
 116 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 117 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 118
 119 #if defined(CONFIG_CMD_KGDB)
 120 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 121 #else
 122 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 123 #endif
 124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 125 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 126 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 127
 128 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 129 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 130
 131 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 132
 133 /*
 134  * Low Level Configuration Settings
 135  * (address mappings, register initial values, etc.)
 136  * You should know what you are doing if you make changes here.
 137  */
 138 /*-----------------------------------------------------------------------
 139  * Internal Memory Mapped Register
 140  */
 141 #define CONFIG_SYS_IMMR         0xFFF00000
 142
 143 /*-----------------------------------------------------------------------
 144  * Definitions for initial stack pointer and data area (in DPRAM)
 145  */
 146 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 147 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 148 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 149 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 150
 151 /*-----------------------------------------------------------------------
 152  * Start addresses for the final memory configuration
 153  * (Set up by the startup code)
 154  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 155  */
 156 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 157 #define CONFIG_SYS_FLASH_BASE           0x40000000
 158 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 160 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 161
 162 /*
 163  * For booting Linux, the board info and command line data
 164  * have to be in the first 8 MB of memory, since this is
 165  * the maximum mapped by the Linux kernel during initialization.
 166  */
 167 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 168
 169 /*-----------------------------------------------------------------------
 170  * FLASH organization
 171  */
 172
 173 /* use CFI flash driver */
 174 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 175 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 176 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO
 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 181
 182 #define CONFIG_ENV_IS_IN_FLASH  1
 183 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 184 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 185
 186 /* Address and size of Redundant Environment Sector     */
 187 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 188 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 189
 190 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 191
 192 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 193
 194 /*-----------------------------------------------------------------------
 195  * Dynamic MTD partition support
 196  */
 197 #define CONFIG_CMD_MTDPARTS
 198 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 199 #define CONFIG_FLASH_CFI_MTD
 200 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 201
 202 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 203                                                 "128k(dtb),"            \
 204                                                 "1664k(kernel),"        \
 205                                                 "2m(rootfs),"           \
 206                                                 "4m(data)"
 207
 208 /*-----------------------------------------------------------------------
 209  * Hardware Information Block
 210  */
 211 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 212 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 213 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 214
 215 /*-----------------------------------------------------------------------
 216  * Cache Configuration
 217  */
 218 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 219 #if defined(CONFIG_CMD_KGDB)
 220 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 221 #endif
 222
 223 /*-----------------------------------------------------------------------
 224  * SYPCR - System Protection Control                            11-9
 225  * SYPCR can only be written once after reset!
 226  *-----------------------------------------------------------------------
 227  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 228  */
 229 #if defined(CONFIG_WATCHDOG)
 230 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 231                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 232 #else
 233 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 234 #endif
 235
 236 /*-----------------------------------------------------------------------
 237  * SIUMCR - SIU Module Configuration                            11-6
 238  *-----------------------------------------------------------------------
 239  * PCMCIA config., multi-function pin tri-state
 240  */
 241 #ifndef CONFIG_CAN_DRIVER
 242 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 243 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 244 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 245 #endif  /* CONFIG_CAN_DRIVER */
 246
 247 /*-----------------------------------------------------------------------
 248  * TBSCR - Time Base Status and Control                         11-26
 249  *-----------------------------------------------------------------------
 250  * Clear Reference Interrupt Status, Timebase freezing enabled
 251  */
 252 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 253
 254 /*-----------------------------------------------------------------------
 255  * RTCSC - Real-Time Clock Status and Control Register          11-27
 256  *-----------------------------------------------------------------------
 257  */
 258 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 259
 260 /*-----------------------------------------------------------------------
 261  * PISCR - Periodic Interrupt Status and Control                11-31
 262  *-----------------------------------------------------------------------
 263  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 264  */
 265 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 266
 267 /*-----------------------------------------------------------------------
 268  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 269  *-----------------------------------------------------------------------
 270  * Reset PLL lock status sticky bit, timer expired status bit and timer
 271  * interrupt status bit
 272  */
 273 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 274
 275 /*-----------------------------------------------------------------------
 276  * SCCR - System Clock and reset Control Register               15-27
 277  *-----------------------------------------------------------------------
 278  * Set clock output, timebase and RTC source and divider,
 279  * power management and some other internal clocks
 280  */
 281 #define SCCR_MASK       SCCR_EBDF11
 282 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 283                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 284                          SCCR_DFALCD00)
 285
 286 /*-----------------------------------------------------------------------
 287  * PCMCIA stuff
 288  *-----------------------------------------------------------------------
 289  *
 290  */
 291 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 292 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 293 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 294 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 295 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 296 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 297 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 298 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 299
 300 /*-----------------------------------------------------------------------
 301  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 302  *-----------------------------------------------------------------------
 303  */
 304
 305 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 306 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 307
 308 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 309 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 310 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 311
 312 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 313 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 314
 315 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 316
 317 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 318
 319 /* Offset for data I/O                  */
 320 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 321
 322 /* Offset for normal register accesses  */
 323 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 324
 325 /* Offset for alternate registers       */
 326 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 327
 328 /*-----------------------------------------------------------------------
 329  *
 330  *-----------------------------------------------------------------------
 331  *
 332  */
 333 #define CONFIG_SYS_DER  0
 334
 335 /*
 336  * Init Memory Controller:
 337  *
 338  * BR0/1 and OR0/1 (FLASH)
 339  */
 340
 341 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 342 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 343
 344 /* used to re-map FLASH both when starting from SRAM or FLASH:
 345  * restrict access enough to keep SRAM working (if any)
 346  * but not too much to meddle with FLASH accesses
 347  */
 348 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 349 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 350
 351 /*
 352  * FLASH timing:
 353  */
 354 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 355                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 356
 357 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 358 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 359 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 360
 361 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 362 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 363 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 364
 365 /*
 366  * BR2/3 and OR2/3 (SDRAM)
 367  *
 368  */
 369 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 370 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 371 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 372
 373 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 374 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 375
 376 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 377 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 378
 379 #ifndef CONFIG_CAN_DRIVER
 380 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 381 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 382 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 383 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 384 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 385 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 386 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 387                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 388 #endif  /* CONFIG_CAN_DRIVER */
 389
 390 /*
 391  * Memory Periodic Timer Prescaler
 392  *
 393  * The Divider for PTA (refresh timer) configuration is based on an
 394  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 395  * the number of chip selects (NCS) and the actually needed refresh
 396  * rate is done by setting MPTPR.
 397  *
 398  * PTA is calculated from
 399  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 400  *
 401  *      gclk      CPU clock (not bus clock!)
 402  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 403  *
 404  * 4096  Rows from SDRAM example configuration
 405  * 1000  factor s -> ms
 406  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 407  *    4  Number of refresh cycles per period
 408  *   64  Refresh cycle in ms per number of rows
 409  * --------------------------------------------
 410  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 411  *
 412  * 50 MHz => 50.000.000 / Divider =  98
 413  * 66 Mhz => 66.000.000 / Divider = 129
 414  * 80 Mhz => 80.000.000 / Divider = 156
 415  */
 416
 417 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 418 #define CONFIG_SYS_MAMR_PTA     98
 419
 420 /*
 421  * For 16 MBit, refresh rates could be 31.3 us
 422  * (= 64 ms / 2K = 125 / quad bursts).
 423  * For a simpler initialization, 15.6 us is used instead.
 424  *
 425  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 426  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 427  */
 428 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 429 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 430
 431 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 432 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 433 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 434
 435 /*
 436  * MAMR settings for SDRAM
 437  */
 438
 439 /* 8 column SDRAM */
 440 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 441                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 442                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 443 /* 9 column SDRAM */
 444 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 445                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 446                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 447
 448 #define CONFIG_SCC1_ENET
 449 #define CONFIG_FEC_ENET
 450 #define CONFIG_ETHPRIME         "SCC"
 451
 452 /* pass open firmware flat tree */
 453 #define CONFIG_OF_BOARD_SETUP   1
 454 #define CONFIG_HWCONFIG         1
 455
 456 #endif  /* __CONFIG_H */