include/configs/TQM866M.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  21 #define CONFIG_TQM866M          1       /* ...on a TQM8xxM module       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  26 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000        /*  15 MHz - CPU minimum clock  */
  27 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000       /* 133 MHz - CPU maximum clock  */
  28 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000        /*  50 MHz - CPU default clock  */
  29                                                 /* (it will be used if there is no      */
  30                                                 /* 'cpuclk' variable with valid value)  */
  31
  32 #undef CONFIG_SYS_MEASURE_CPUCLK                        /* Measure real cpu clock       */
  33                                                 /* (function measure_gclk()     */
  34                                                 /* will be called)              */
  35 #ifdef CONFIG_SYS_MEASURE_CPUCLK
  36 #define CONFIG_SYS_8XX_XIN              10000000        /* measure_gclk() needs this    */
  37 #endif
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #define CONFIG_SYS_SMC_RXBUFLEN 128
  41 #define CONFIG_SYS_MAXIDLE      10
  42
  43 #define CONFIG_BOOTCOUNT_LIMIT
  44
  45
  46 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  47
  48 #define CONFIG_PREBOOT  "echo;" \
  49         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  50         "echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53
  54 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  55         "netdev=eth0\0"                                                 \
  56         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  57                 "nfsroot=${serverip}:${rootpath}\0"                     \
  58         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  59         "addip=setenv bootargs ${bootargs} "                            \
  60                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  61                 ":${hostname}:${netdev}:off panic=1\0"                  \
  62         "flash_nfs=run nfsargs addip;"                                  \
  63                 "bootm ${kernel_addr}\0"                                \
  64         "flash_self=run ramargs addip;"                                 \
  65                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  66         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  67         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  68         "hostname=TQM866M\0"                                            \
  69         "bootfile=TQM866M/uImage\0"                                     \
  70         "fdt_addr=400C0000\0"                                           \
  71         "kernel_addr=40100000\0"                                        \
  72         "ramdisk_addr=40280000\0"                                       \
  73         "u-boot=TQM866M/u-image.bin\0"                                  \
  74         "load=tftp 200000 ${u-boot}\0"                                  \
  75         "update=prot off 40000000 +${filesize};"                        \
  76                 "era 40000000 +${filesize};"                            \
  77                 "cp.b 200000 40000000 ${filesize};"                     \
  78                 "sete filesize;save\0"                                  \
  79         ""
  80 #define CONFIG_BOOTCOMMAND      "run flash_self"
  81
  82 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  83 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  84
  85 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  86
  87 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  88
  89 /* enable I2C and select the hardware/software driver */
  90 #define CONFIG_SYS_I2C
  91 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
  92 #define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
  93 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  94
  95 /*
  96  * Software (bit-bang) I2C driver configuration
  97  */
  98 #define PB_SCL          0x00000020      /* PB 26 */
  99 #define PB_SDA          0x00000010      /* PB 27 */
 100
 101 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 102 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 103 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 104 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 105 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 106                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 107 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 108                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 109 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 110
 111 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C256      */
 112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2                /* two byte address     */
 113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 115
 116 /*
 117  * BOOTP options
 118  */
 119 #define CONFIG_BOOTP_SUBNETMASK
 120 #define CONFIG_BOOTP_GATEWAY
 121 #define CONFIG_BOOTP_HOSTNAME
 122 #define CONFIG_BOOTP_BOOTPATH
 123 #define CONFIG_BOOTP_BOOTFILESIZE
 124
 125 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 126
 127 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 128
 129 /*
 130  * Command line configuration.
 131  */
 132
 133 #define CONFIG_NETCONSOLE
 134
 135 /*
 136  * Miscellaneous configurable options
 137  */
 138 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 139
 140 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 141
 142 #if defined(CONFIG_CMD_KGDB)
 143 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 144 #else
 145 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 146 #endif
 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 148 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 149 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 150
 151 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 152 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 153
 154 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 155
 156 /*
 157  * Low Level Configuration Settings
 158  * (address mappings, register initial values, etc.)
 159  * You should know what you are doing if you make changes here.
 160  */
 161 /*-----------------------------------------------------------------------
 162  * Internal Memory Mapped Register
 163  */
 164 #define CONFIG_SYS_IMMR         0xFFF00000
 165
 166 /*-----------------------------------------------------------------------
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 170 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_FLASH_BASE           0x40000000
 181 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 183 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization.
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 191
 192 /*-----------------------------------------------------------------------
 193  * FLASH organization
 194  */
 195 /* use CFI flash driver */
 196 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 197 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 198 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 199 #define CONFIG_SYS_FLASH_EMPTY_INFO
 200 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 203
 204 #define CONFIG_ENV_IS_IN_FLASH  1
 205 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 206 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 207 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 208
 209 /* Address and size of Redundant Environment Sector     */
 210 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 211 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 212
 213 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 214
 215 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 216
 217 /*-----------------------------------------------------------------------
 218  * Dynamic MTD partition support
 219  */
 220 #define CONFIG_CMD_MTDPARTS
 221 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 222 #define CONFIG_FLASH_CFI_MTD
 223 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 224
 225 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 226                                                 "128k(dtb),"            \
 227                                                 "1920k(kernel),"        \
 228                                                 "5632(rootfs),"         \
 229                                                 "4m(data)"
 230
 231 /*-----------------------------------------------------------------------
 232  * Hardware Information Block
 233  */
 234 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 235 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 236 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 237
 238 /*-----------------------------------------------------------------------
 239  * Cache Configuration
 240  */
 241 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 242 #if defined(CONFIG_CMD_KGDB)
 243 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 244 #endif
 245
 246 /*-----------------------------------------------------------------------
 247  * SYPCR - System Protection Control                            11-9
 248  * SYPCR can only be written once after reset!
 249  *-----------------------------------------------------------------------
 250  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 251  */
 252 #if defined(CONFIG_WATCHDOG)
 253 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 254                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 255 #else
 256 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 257 #endif
 258
 259 /*-----------------------------------------------------------------------
 260  * SIUMCR - SIU Module Configuration                            11-6
 261  *-----------------------------------------------------------------------
 262  * PCMCIA config., multi-function pin tri-state
 263  */
 264 #ifndef CONFIG_CAN_DRIVER
 265 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 266 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 267 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 268 #endif  /* CONFIG_CAN_DRIVER */
 269
 270 /*-----------------------------------------------------------------------
 271  * TBSCR - Time Base Status and Control                         11-26
 272  *-----------------------------------------------------------------------
 273  * Clear Reference Interrupt Status, Timebase freezing enabled
 274  */
 275 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 276
 277 /*-----------------------------------------------------------------------
 278  * PISCR - Periodic Interrupt Status and Control                11-31
 279  *-----------------------------------------------------------------------
 280  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 281  */
 282 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 283
 284 /*-----------------------------------------------------------------------
 285  * SCCR - System Clock and reset Control Register               15-27
 286  *-----------------------------------------------------------------------
 287  * Set clock output, timebase and RTC source and divider,
 288  * power management and some other internal clocks
 289  */
 290 #define SCCR_MASK       SCCR_EBDF11
 291 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 292                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 293                          SCCR_DFALCD00)
 294
 295 /*-----------------------------------------------------------------------
 296  * PCMCIA stuff
 297  *-----------------------------------------------------------------------
 298  *
 299  */
 300 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 301 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 302 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 303 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 304 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 305 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 307 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 308
 309 /*-----------------------------------------------------------------------
 310  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 311  *-----------------------------------------------------------------------
 312  */
 313
 314 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 315 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 316
 317 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 318 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 319 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 320
 321 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 322 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 323
 324 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 325
 326 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 327
 328 /* Offset for data I/O                  */
 329 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 330
 331 /* Offset for normal register accesses  */
 332 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 333
 334 /* Offset for alternate registers       */
 335 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 336
 337 /*-----------------------------------------------------------------------
 338  *
 339  *-----------------------------------------------------------------------
 340  *
 341  */
 342 #define CONFIG_SYS_DER 0
 343
 344 /*
 345  * Init Memory Controller:
 346  *
 347  * BR0/1 and OR0/1 (FLASH)
 348  */
 349
 350 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 351 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 352
 353 /* used to re-map FLASH both when starting from SRAM or FLASH:
 354  * restrict access enough to keep SRAM working (if any)
 355  * but not too much to meddle with FLASH accesses
 356  */
 357 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 358 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 359
 360 /*
 361  * FLASH timing: Default value of OR0 after reset
 362  */
 363 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 364                                  OR_SCY_15_CLK | OR_TRLX)
 365
 366 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 367 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 368 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 369
 370 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 371 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 372 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 373
 374 /*
 375  * BR2/3 and OR2/3 (SDRAM)
 376  *
 377  */
 378 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 379 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 380 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 381
 382 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 383 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 384
 385 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 386 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 387
 388 #ifndef CONFIG_CAN_DRIVER
 389 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 390 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 391 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 392 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 393 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 394 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 395 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 396                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 397 #endif  /* CONFIG_CAN_DRIVER */
 398
 399 /*
 400  * 4096 Rows from SDRAM example configuration
 401  * 1000 factor s -> ms
 402  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 403  * 4    Number of refresh cycles per period
 404  * 64   Refresh cycle in ms per number of rows
 405  */
 406 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 407
 408 /*
 409  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 410  *
 411  *                        CPUclock(MHz) * 31.2
 412  * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 413  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 414  *
 415  * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 416  * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 417  * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 418  * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 419  *
 420  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 421  * be met also in the default configuration, i.e. if environment variable
 422  * 'cpuclk' is not set.
 423  */
 424 #define CONFIG_SYS_MAMR_PTA             97
 425
 426 /*
 427  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 428  */
 429 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 430 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
 431 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 432 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
 433
 434 /*
 435  * MAMR settings for SDRAM
 436  */
 437
 438 /* 8 column SDRAM */
 439 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 440                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 441                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 442 /* 9 column SDRAM */
 443 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 444                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 445                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 446 /* 10 column SDRAM */
 447 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 448                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 449                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 450
 451 #define CONFIG_SCC1_ENET
 452 #define CONFIG_FEC_ENET
 453 #define CONFIG_ETHPRIME         "SCC"
 454
 455 #define CONFIG_HWCONFIG         1
 456
 457 #endif  /* __CONFIG_H */