include/configs/TQM885D.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22
  23 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  24 #define CONFIG_TQM885D          1       /* ...on a TQM88D module        */
  25 #define CONFIG_DISPLAY_BOARDINFO
  26
  27 #define CONFIG_SYS_TEXT_BASE    0x40000000
  28
  29 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  30 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000        /*  15 MHz - CPU minimum clock  */
  31 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000       /* 133 MHz - CPU maximum clock  */
  32 #define CONFIG_8xx_CPUCLK_DEFAULT       66000000        /*  66 MHz - CPU default clock  */
  33                                                 /* (it will be used if there is no      */
  34                                                 /* 'cpuclk' variable with valid value)  */
  35
  36 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  37 #define CONFIG_SYS_SMC_RXBUFLEN 128
  38 #define CONFIG_SYS_MAXIDLE      10
  39 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  40
  41 #define CONFIG_BOOTCOUNT_LIMIT
  42
  43 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  44
  45 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  46
  47 #define CONFIG_PREBOOT  "echo;" \
  48         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  49         "echo"
  50
  51 #undef  CONFIG_BOOTARGS
  52
  53 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  54         "netdev=eth0\0"                                                 \
  55         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  56                 "nfsroot=${serverip}:${rootpath}\0"                     \
  57         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  58         "addip=setenv bootargs ${bootargs} "                            \
  59                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  60                 ":${hostname}:${netdev}:off panic=1\0"                  \
  61         "flash_nfs=run nfsargs addip;"                                  \
  62                 "bootm ${kernel_addr}\0"                                \
  63         "flash_self=run ramargs addip;"                                 \
  64                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  65         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  66         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  67         "bootfile=/tftpboot/TQM885D/uImage\0"                           \
  68         "fdt_addr=400C0000\0"                                           \
  69         "kernel_addr=40100000\0"                                        \
  70         "ramdisk_addr=40280000\0"                                       \
  71         "load=tftp 200000 ${u-boot}\0"                                  \
  72         "update=protect off 40000000 +${filesize};"                     \
  73                 "erase 40000000 +${filesize};"                          \
  74                 "cp.b 200000 40000000 ${filesize};"                     \
  75                 "protect on 40000000 +${filesize}\0"                    \
  76         ""
  77 #define CONFIG_BOOTCOMMAND      "run flash_self"
  78
  79 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  80 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  81
  82 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  83
  84 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  85
  86 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  87
  88 /* enable I2C and select the hardware/software driver */
  89 #define CONFIG_SYS_I2C
  90 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
  91 #define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
  92 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  93 /*
  94  * Software (bit-bang) I2C driver configuration
  95  */
  96 #define PB_SCL          0x00000020      /* PB 26 */
  97 #define PB_SDA          0x00000010      /* PB 27 */
  98
  99 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 100 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 101 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 102 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 103 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 104                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 105 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 106                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 107 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 108
 109 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C??       */
 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2                /* two byte address     */
 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 113
 114 # define CONFIG_RTC_DS1337 1
 115 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
 116
 117 /*
 118  * BOOTP options
 119  */
 120 #define CONFIG_BOOTP_SUBNETMASK
 121 #define CONFIG_BOOTP_GATEWAY
 122 #define CONFIG_BOOTP_HOSTNAME
 123 #define CONFIG_BOOTP_BOOTPATH
 124 #define CONFIG_BOOTP_BOOTFILESIZE
 125
 126
 127 #define CONFIG_MAC_PARTITION
 128 #define CONFIG_DOS_PARTITION
 129
 130 #undef CONFIG_RTC_MPC8xx                /* MPC885 does not support RTC  */
 131
 132 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 133
 134
 135 /*
 136  * Command line configuration.
 137  */
 138 #define CONFIG_CMD_ASKENV
 139 #define CONFIG_CMD_DATE
 140 #define CONFIG_CMD_DHCP
 141 #define CONFIG_CMD_EEPROM
 142 #define CONFIG_CMD_EXT2
 143 #define CONFIG_CMD_I2C
 144 #define CONFIG_CMD_IDE
 145 #define CONFIG_CMD_MII
 146 #define CONFIG_CMD_PING
 147
 148
 149 /*
 150  * Miscellaneous configurable options
 151  */
 152 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 153
 154 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 155
 156 #if defined(CONFIG_CMD_KGDB)
 157 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 158 #else
 159 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 160 #endif
 161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 162 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 163 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 164
 165 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 166 #define CONFIG_SYS_MEMTEST_END          0x0300000       /* 1 ... 3 MB in DRAM   */
 167 #define CONFIG_SYS_ALT_MEMTEST                          /* alternate, more extensive
 168                                                    memory test.*/
 169
 170 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 171
 172 /*
 173  * Enable loopw command.
 174  */
 175 #define CONFIG_LOOPW
 176
 177 /*
 178  * Low Level Configuration Settings
 179  * (address mappings, register initial values, etc.)
 180  * You should know what you are doing if you make changes here.
 181  */
 182 /*-----------------------------------------------------------------------
 183  * Internal Memory Mapped Register
 184  */
 185 #define CONFIG_SYS_IMMR         0xFFF00000
 186
 187 /*-----------------------------------------------------------------------
 188  * Definitions for initial stack pointer and data area (in DPRAM)
 189  */
 190 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 191 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 192 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 193 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 194
 195 /*-----------------------------------------------------------------------
 196  * Start addresses for the final memory configuration
 197  * (Set up by the startup code)
 198  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 199  */
 200 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 201 #define CONFIG_SYS_FLASH_BASE           0x40000000
 202 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 204 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 128 kB for malloc()  */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 212
 213 /*-----------------------------------------------------------------------
 214  * FLASH organization
 215  */
 216
 217 /* use CFI flash driver */
 218 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 219 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 220 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 221 #define CONFIG_SYS_FLASH_EMPTY_INFO
 222 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 225
 226 #define CONFIG_ENV_IS_IN_FLASH  1
 227 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 228 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 229 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 230
 231 /* Address and size of Redundant Environment Sector     */
 232 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 233 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 234
 235 /*-----------------------------------------------------------------------
 236  * Hardware Information Block
 237  */
 238 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 239 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 240 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 241
 242 /*-----------------------------------------------------------------------
 243  * Cache Configuration
 244  */
 245 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 246 #if defined(CONFIG_CMD_KGDB)
 247 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 248 #endif
 249
 250 /*-----------------------------------------------------------------------
 251  * SYPCR - System Protection Control                            11-9
 252  * SYPCR can only be written once after reset!
 253  *-----------------------------------------------------------------------
 254  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 255  */
 256 #if defined(CONFIG_WATCHDOG)
 257 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 258                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 259 #else
 260 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 261 #endif
 262
 263 /*-----------------------------------------------------------------------
 264  * SIUMCR - SIU Module Configuration                            11-6
 265  *-----------------------------------------------------------------------
 266  * PCMCIA config., multi-function pin tri-state
 267  */
 268 #ifndef CONFIG_CAN_DRIVER
 269 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 270 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 271 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 272 #endif  /* CONFIG_CAN_DRIVER */
 273
 274 /*-----------------------------------------------------------------------
 275  * TBSCR - Time Base Status and Control                         11-26
 276  *-----------------------------------------------------------------------
 277  * Clear Reference Interrupt Status, Timebase freezing enabled
 278  */
 279 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 280
 281 /*-----------------------------------------------------------------------
 282  * PISCR - Periodic Interrupt Status and Control                11-31
 283  *-----------------------------------------------------------------------
 284  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 285  */
 286 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 287
 288 /*-----------------------------------------------------------------------
 289  * SCCR - System Clock and reset Control Register               15-27
 290  *-----------------------------------------------------------------------
 291  * Set clock output, timebase and RTC source and divider,
 292  * power management and some other internal clocks
 293  */
 294 #define SCCR_MASK       SCCR_EBDF11
 295 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 296                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 297                          SCCR_DFALCD00)
 298
 299 /*-----------------------------------------------------------------------
 300  * PCMCIA stuff
 301  *-----------------------------------------------------------------------
 302  *
 303  */
 304 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 305 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 307 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 309 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 310 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 311 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 312
 313 /*-----------------------------------------------------------------------
 314  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 315  *-----------------------------------------------------------------------
 316  */
 317
 318 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 319 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 320
 321 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 322 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 323 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 324
 325 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 326 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 327
 328 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 329
 330 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 331
 332 /* Offset for data I/O                  */
 333 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 334
 335 /* Offset for normal register accesses  */
 336 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for alternate registers       */
 339 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 340
 341 /*-----------------------------------------------------------------------
 342  *
 343  *-----------------------------------------------------------------------
 344  *
 345  */
 346 #define CONFIG_SYS_DER 0
 347
 348 /*
 349  * Init Memory Controller:
 350  *
 351  * BR0/1 and OR0/1 (FLASH)
 352  */
 353
 354 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 355 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 362 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 363
 364 /*
 365  * FLASH timing: Default value of OR0 after reset
 366  */
 367 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 368                                  OR_SCY_6_CLK | OR_TRLX)
 369
 370 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 371 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 372 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 373
 374 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 375 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 376 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 377
 378 /*
 379  * BR2/3 and OR2/3 (SDRAM)
 380  *
 381  */
 382 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 383 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 384 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 385
 386 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 387 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 388
 389 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 390 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 391
 392 #ifndef CONFIG_CAN_DRIVER
 393 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 394 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 395 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 396 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 397 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 398 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 399 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 400                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 401 #endif  /* CONFIG_CAN_DRIVER */
 402
 403 /*
 404  * 4096 Rows from SDRAM example configuration
 405  * 1000 factor s -> ms
 406  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 407  * 4    Number of refresh cycles per period
 408  * 64   Refresh cycle in ms per number of rows
 409  */
 410 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 411
 412 /*
 413  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 414  *
 415  *                        CPUclock(MHz) * 31.2
 416  * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 417  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 418  *
 419  * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 420  * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 421  * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 422  * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 423  *
 424  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 425  * be met also in the default configuration, i.e. if environment variable
 426  * 'cpuclk' is not set.
 427  */
 428 #define CONFIG_SYS_MAMR_PTA             128
 429
 430 /*
 431  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 432  */
 433 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 434 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
 435 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 436 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
 437
 438 /*
 439  * MAMR settings for SDRAM
 440  */
 441
 442 /* 8 column SDRAM */
 443 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 444                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 445                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 446 /* 9 column SDRAM */
 447 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 448                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 449                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 450 /* 10 column SDRAM */
 451 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 452                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 453                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 454
 455 /*
 456  * Network configuration
 457  */
 458 #define CONFIG_SCC2_ENET                /* enable ethernet on SCC2 */
 459 #define CONFIG_FEC_ENET                 /* enable ethernet on FEC */
 460 #define CONFIG_ETHER_ON_FEC1            /* ... for FEC1 */
 461 #define CONFIG_ETHER_ON_FEC2            /* ... for FEC2 */
 462
 463 #if defined(CONFIG_CMD_MII)
 464 #define CONFIG_SYS_DISCOVER_PHY
 465 #define CONFIG_MII_INIT 1
 466 #endif
 467
 468 #define CONFIG_NET_RETRY_COUNT 1        /* reduce max. timeout before
 469                                            switching to another netwok (if the
 470                                            tried network is unreachable) */
 471
 472 #define CONFIG_ETHPRIME         "SCC"
 473
 474 #define CONFIG_HWCONFIG         1
 475
 476 #endif  /* __CONFIG_H */