include/configs/a4m072.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is a MPC5200 CPU */
  20 #define CONFIG_A4M072           1       /* ... on A4M072 board */
  21 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM */
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  25
  26 #define CONFIG_MISC_INIT_R
  27
  28 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  29
  30 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  31
  32 /*
  33  * Serial console configuration
  34  */
  35 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  36 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  37 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  38 /* define to enable silent console */
  39 #define CONFIG_SILENT_CONSOLE
  40 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  41
  42 /*
  43  * PCI Mapping:
  44  * 0x40000000 - 0x4fffffff - PCI Memory
  45  * 0x50000000 - 0x50ffffff - PCI IO Space
  46  */
  47 #define CONFIG_PCI
  48
  49 #if defined(CONFIG_PCI)
  50 #define CONFIG_PCI_PNP          1
  51 #define CONFIG_PCI_SCAN_SHOW    1
  52 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  53
  54 #define CONFIG_PCI_MEM_BUS      0x40000000
  55 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  56 #define CONFIG_PCI_MEM_SIZE     0x10000000
  57
  58 #define CONFIG_PCI_IO_BUS       0x50000000
  59 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  60 #define CONFIG_PCI_IO_SIZE      0x01000000
  61 #endif
  62
  63 #define CONFIG_SYS_XLB_PIPELINING       1
  64
  65 #undef CONFIG_EEPRO100
  66
  67 /* Partitions */
  68 #define CONFIG_MAC_PARTITION
  69 #define CONFIG_DOS_PARTITION
  70
  71 /* USB */
  72 #define CONFIG_USB_OHCI_NEW
  73 #define CONFIG_USB_STORAGE
  74 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  75 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  76 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  77 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
  78 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
  79 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  80
  81 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90
  91
  92 /*
  93  * Command line configuration.
  94  */
  95 #define CONFIG_CMD_EEPROM
  96 #define CONFIG_CMD_FAT
  97 #define CONFIG_CMD_I2C
  98 #define CONFIG_CMD_IDE
  99 #define CONFIG_CMD_SNTP
 100 #define CONFIG_CMD_USB
 101 #define CONFIG_CMD_MII
 102 #define CONFIG_CMD_DHCP
 103 #define CONFIG_CMD_PING
 104 #define CONFIG_CMD_DISPLAY
 105
 106 #if defined(CONFIG_PCI)
 107 #define CONFIG_CMD_PCI
 108 #endif
 109
 110 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low with 32 MB Flash */
 111 #define CONFIG_SYS_LOWBOOT              1
 112 #define CONFIG_SYS_LOWBOOT32            1
 113 #endif
 114
 115 /*
 116  * Autobooting
 117  */
 118 #define CONFIG_BOOTDELAY        2       /* autoboot after 2 seconds */
 119
 120 #define CONFIG_SYS_AUTOLOAD     "n"
 121
 122 #undef  CONFIG_BOOTARGS
 123 #define CONFIG_PREBOOT                          "run try_update"
 124
 125 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 126         "bk=run add_mtd ; run add_consolespec ; bootm 200000\0"         \
 127         "cf1=diskboot 200000 0:1\0"                                     \
 128         "bootcmd_cf1=run bcf1\0"                                        \
 129         "bcf=setenv bootargs root=/dev/hda3\0"                          \
 130         "bootcmd_nfs=run bnfs\0"                                        \
 131         "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
 132                 "panic=1\0"                                             \
 133         "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"                \
 134                         "run norargs addip; run bk\0"                   \
 135         "bnfs=nfs 200000 ${rootpath}/boot/uImage;"                      \
 136                         "run nfsargs addip ; run bk\0"                  \
 137         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 138                                 "nfsroot=${serverip}:${rootpath}\0"     \
 139         "try_update=usb start;sleep 2;usb start;sleep 1;"               \
 140                         "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"   \
 141                         "source 2F0000\0"                               \
 142         "env_addr=FE060000\0"                                           \
 143         "kernel_addr=FE100000\0"                                        \
 144         "rootfs_addr=FE200000\0"                                        \
 145         "add_mtd=setenv bootargs ${bootargs} mtdparts="                 \
 146                 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"      \
 147         "bcf1=run cf1; run bcf; run addip; run bk\0"                    \
 148         "add_consolespec=setenv bootargs ${bootargs} "                  \
 149                                 "console=/dev/null quiet\0"             \
 150         "addip=if test -n ${ethaddr};"                                  \
 151                 "then if test -n ${ipaddr};"                            \
 152                         "then setenv bootargs ${bootargs} "             \
 153                                 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
 154                                 "${netmask}:${hostname}:${netdev}:off;" \
 155                         "fi;"                                           \
 156                 "else;"                                                 \
 157                         "setenv bootargs ${bootargs} no_ethaddr;"       \
 158                 "fi\0"                                                  \
 159         "hostname=CPUP0\0"                                              \
 160         "netdev=eth0\0"                                                 \
 161         "bootcmd=run bootcmd_nor\0"                                     \
 162         ""
 163 /*
 164  * IPB Bus clocking configuration.
 165  */
 166 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 167
 168 /*
 169  * I2C configuration
 170  */
 171 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 172 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 173
 174 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 175 #define CONFIG_SYS_I2C_SLAVE            0x7F
 176
 177 /*
 178  * EEPROM configuration
 179  */
 180 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1010010x */
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 184 #define CONFIG_SYS_EEPROM_WREN                  1
 185 #define CONFIG_SYS_EEPROM_WP                    GPIO_PSC2_4
 186
 187 /*
 188  * Flash configuration
 189  */
 190 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 191 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 192 #if !defined(CONFIG_SYS_LOWBOOT)
 193 #error "CONFIG_SYS_LOWBOOT not defined?"
 194 #else   /* CONFIG_SYS_LOWBOOT */
 195 #if defined(CONFIG_SYS_LOWBOOT32)
 196 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 197 #endif
 198 #endif  /* CONFIG_SYS_LOWBOOT */
 199
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 202 #define CONFIG_FLASH_CFI_DRIVER
 203 #define CONFIG_SYS_FLASH_CFI
 204 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 205 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS0_START}
 206 #define CONFIG_SYS_FLASH_BANKS_SIZES    {CONFIG_SYS_CS0_SIZE}
 207
 208 /*
 209  * Environment settings
 210  */
 211 #define CONFIG_ENV_IS_IN_FLASH  1
 212 #define CONFIG_ENV_SIZE         0x10000
 213 #define CONFIG_ENV_SECT_SIZE    0x20000
 214 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 215 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 216
 217 #define CONFIG_ENV_OVERWRITE    1
 218
 219 /*
 220  * Memory map
 221  */
 222 #define CONFIG_SYS_MBAR         0xF0000000
 223 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 224 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 225
 226 /* Use SRAM until RAM will be available */
 227 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 228 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 229
 230
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233
 234 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 235 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 236 #   define CONFIG_SYS_RAMBOOT           1
 237 #endif
 238
 239 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 240 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 241 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 242
 243 /*
 244  * Ethernet configuration
 245  */
 246 #define CONFIG_MPC5xxx_FEC      1
 247 #define CONFIG_MPC5xxx_FEC_MII100
 248 /*
 249  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 250  */
 251 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 252 #define CONFIG_PHY_ADDR         0x1f
 253 #define CONFIG_PHY_TYPE         0x79c874                /* AMD Phy Controller */
 254
 255 /*
 256  * GPIO configuration
 257  */
 258 #define CONFIG_SYS_GPS_PORT_CONFIG      0x18000004
 259
 260 /*
 261  * Miscellaneous configurable options
 262  */
 263 #define CONFIG_SYS_HUSH_PARSER
 264 #define CONFIG_CMDLINE_EDITING  1
 265 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 266 #if defined(CONFIG_CMD_KGDB)
 267 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 268 #else
 269 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 270 #endif
 271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 272 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 273 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 274
 275 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 276 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 277
 278 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 279
 280 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 281 #if defined(CONFIG_CMD_KGDB)
 282 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 283 #endif
 284
 285
 286 /*
 287  * Various low-level settings
 288  */
 289 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 290 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 291 /* Flash at CSBoot, CS0 */
 292 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 293 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 294 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 295 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 296 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 297 /* External SRAM at CS1 */
 298 #define CONFIG_SYS_CS1_START            0x62000000
 299 #define CONFIG_SYS_CS1_SIZE             0x00400000
 300 #define CONFIG_SYS_CS1_CFG              0x00009930
 301 #define CONFIG_SYS_SRAM_BASE            CONFIG_SYS_CS1_START
 302 #define CONFIG_SYS_SRAM_SIZE            CONFIG_SYS_CS1_SIZE
 303 /* LED display at CS7 */
 304 #define CONFIG_SYS_CS7_START            0x6a000000
 305 #define CONFIG_SYS_CS7_SIZE             (64*1024)
 306 #define CONFIG_SYS_CS7_CFG              0x0000bf30
 307
 308 #define CONFIG_SYS_CS_BURST             0x00000000
 309 #define CONFIG_SYS_CS_DEADCYCLE         0x33333003
 310
 311 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 312
 313 /*-----------------------------------------------------------------------
 314  * USB stuff
 315  *-----------------------------------------------------------------------
 316  */
 317 #define CONFIG_USB_CLOCK        0x0001BBBB
 318 #define CONFIG_USB_CONFIG       0x00001000 /* 0x4000 for SE mode */
 319
 320 /*-----------------------------------------------------------------------
 321  * IDE/ATA stuff Supports IDE harddisk
 322  *-----------------------------------------------------------------------
 323  */
 324
 325 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 326
 327 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 328 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 329
 330 #define CONFIG_IDE_PREINIT
 331
 332 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 333 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 334
 335 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 336
 337 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 338
 339 /* Offset for data I/O                  */
 340 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 341
 342 /* Offset for normal register accesses  */
 343 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 344
 345 /* Offset for alternate registers       */
 346 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 347
 348 /* Interval between registers                                                */
 349 #define CONFIG_SYS_ATA_STRIDE          4
 350
 351 #define CONFIG_ATAPI                   1
 352
 353 /*-----------------------------------------------------------------------
 354  * Open firmware flat tree support
 355  *-----------------------------------------------------------------------
 356  */
 357 #define CONFIG_OF_BOARD_SETUP   1
 358
 359 #define OF_CPU                  "PowerPC,5200@0"
 360 #define OF_SOC                  "soc5200@f0000000"
 361 #define OF_TBCLK                (bd->bi_busfreq / 4)
 362 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 363
 364 /* Support for the 7-segment display */
 365 #define CONFIG_SYS_DISP_CHR_RAM      CONFIG_SYS_CS7_START
 366 #define CONFIG_SHOW_ACTIVITY            /* used for display realization */
 367
 368 #define CONFIG_SHOW_BOOT_PROGRESS
 369
 370 #endif /* __CONFIG_H */