include/configs/da850evm.h

   1 /*
   2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * Based on davinci_dvevm.h. Original Copyrights follow:
   5  *
   6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Board
  16  */
  17 #define CONFIG_DRIVER_TI_EMAC
  18 /* check if direct NOR boot config is used */
  19 #ifndef CONFIG_DIRECT_NOR_BOOT
  20 #define CONFIG_USE_SPIFLASH
  21 #endif
  22
  23 /*
  24  * SoC Configuration
  25  */
  26 #define CONFIG_MACH_DAVINCI_DA850_EVM
  27 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  28 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  29 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  30 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  31 #define CONFIG_SYS_OSCIN_FREQ           24000000
  32 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  33 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  34 #define CONFIG_SYS_DA850_PLL_INIT
  35 #define CONFIG_SYS_DA850_DDR_INIT
  36
  37 #ifdef CONFIG_DIRECT_NOR_BOOT
  38 #define CONFIG_ARCH_CPU_INIT
  39 #define CONFIG_DA8XX_GPIO
  40 #define CONFIG_SYS_TEXT_BASE            0x60000000
  41 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  42 #define CONFIG_DA850_LOWLEVEL
  43 #else
  44 #define CONFIG_SYS_TEXT_BASE            0xc1080000
  45 #endif
  46
  47 /*
  48  * Memory Info
  49  */
  50 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  51 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  52 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  53 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  54
  55 /* memtest start addr */
  56 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  57
  58 /* memtest will be run on 16MB */
  59 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  60
  61 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  62
  63 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  64         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  65         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  66         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  67         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  68         DAVINCI_SYSCFG_SUSPSRC_I2C)
  69
  70 /*
  71  * PLL configuration
  72  */
  73 #define CONFIG_SYS_DV_CLKMODE          0
  74 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  75 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  76 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  77 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  78 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  79 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  80 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  81 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  82
  83 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  84 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  85 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  86 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  87
  88 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  89 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  90
  91 /*
  92  * DDR2 memory configuration
  93  */
  94 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  95                                         DV_DDR_PHY_EXT_STRBEN | \
  96                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  97
  98 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  99         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
 100         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
 101         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
 102         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
 103         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
 104         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
 105         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 106
 107 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
 108 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
 109
 110 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
 111         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
 112         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
 113         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
 114         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
 115         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
 116         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 117         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 118         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 119
 120 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 121         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 122         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 123         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 124         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 125         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 126         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 127         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 128
 129 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 130 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 131
 132 /*
 133  * Serial Driver info
 134  */
 135 #define CONFIG_SYS_NS16550_SERIAL
 136 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 137 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 138 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 139 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 140 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 141
 142 #define CONFIG_SPI
 143 #define CONFIG_DAVINCI_SPI
 144 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 145 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 146 #define CONFIG_SF_DEFAULT_SPEED         30000000
 147 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 148
 149 #ifdef CONFIG_USE_SPIFLASH
 150 #define CONFIG_SPL_SPI_LOAD
 151 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 152 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 153 #endif
 154
 155 /*
 156  * I2C Configuration
 157  */
 158 #define CONFIG_SYS_I2C
 159 #define CONFIG_SYS_I2C_DAVINCI
 160 #define CONFIG_SYS_DAVINCI_I2C_SPEED            25000
 161 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 162 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 163
 164 /*
 165  * Flash & Environment
 166  */
 167 #ifdef CONFIG_USE_NAND
 168 #undef CONFIG_ENV_IS_IN_FLASH
 169 #define CONFIG_NAND_DAVINCI
 170 #define CONFIG_SYS_NO_FLASH
 171 #define CONFIG_ENV_IS_IN_NAND           /* U-Boot env in NAND Flash  */
 172 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 173 #define CONFIG_ENV_SIZE                 (128 << 10)
 174 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 175 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 176 #define CONFIG_SYS_NAND_PAGE_2K
 177 #define CONFIG_SYS_NAND_CS              3
 178 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 179 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 180 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 181 #undef CONFIG_SYS_NAND_HW_ECC
 182 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 183 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 184 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 185 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 186 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 187 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
 188 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 189 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 190 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 191 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 192                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 193                                         CONFIG_SYS_MALLOC_LEN -       \
 194                                         GENERATED_GBL_DATA_SIZE)
 195 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 196                                 24, 25, 26, 27, 28, \
 197                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 198                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 199                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 200                                 59, 60, 61, 62, 63 }
 201 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 202 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 203 #define CONFIG_SYS_NAND_ECCSIZE         512
 204 #define CONFIG_SYS_NAND_ECCBYTES        10
 205 #define CONFIG_SYS_NAND_OOBSIZE         64
 206 #define CONFIG_SPL_NAND_BASE
 207 #define CONFIG_SPL_NAND_DRIVERS
 208 #define CONFIG_SPL_NAND_ECC
 209 #define CONFIG_SPL_NAND_SIMPLE
 210 #define CONFIG_SPL_NAND_LOAD
 211 #endif
 212
 213 /*
 214  * Network & Ethernet Configuration
 215  */
 216 #ifdef CONFIG_DRIVER_TI_EMAC
 217 #define CONFIG_MII
 218 #define CONFIG_BOOTP_DNS
 219 #define CONFIG_BOOTP_DNS2
 220 #define CONFIG_BOOTP_SEND_HOSTNAME
 221 #define CONFIG_NET_RETRY_COUNT  10
 222 #endif
 223
 224 #ifdef CONFIG_USE_NOR
 225 #define CONFIG_ENV_IS_IN_FLASH
 226 #define CONFIG_FLASH_CFI_DRIVER
 227 #define CONFIG_SYS_FLASH_CFI
 228 #define CONFIG_SYS_FLASH_PROTECTION
 229 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 230 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 231 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 232 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 233 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 234 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 235 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 236                + 3)
 237 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 238 #endif
 239
 240 #ifdef CONFIG_USE_SPIFLASH
 241 #undef CONFIG_ENV_IS_IN_FLASH
 242 #undef CONFIG_ENV_IS_IN_NAND
 243 #define CONFIG_ENV_IS_IN_SPI_FLASH
 244 #define CONFIG_ENV_SIZE                 (64 << 10)
 245 #define CONFIG_ENV_OFFSET               (512 << 10)
 246 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
 247 #define CONFIG_SYS_NO_FLASH
 248 #endif
 249
 250 /*
 251  * U-Boot general configuration
 252  */
 253 #define CONFIG_MISC_INIT_R
 254 #define CONFIG_BOARD_EARLY_INIT_F
 255 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 256 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 257 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 258 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
 259 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 260 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 261 #define CONFIG_AUTO_COMPLETE
 262 #define CONFIG_CMDLINE_EDITING
 263 #define CONFIG_SYS_LONGHELP
 264 #define CONFIG_CRC32_VERIFY
 265 #define CONFIG_MX_CYCLIC
 266
 267 /*
 268  * Linux Information
 269  */
 270 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 271 #define CONFIG_HWCONFIG         /* enable hwconfig */
 272 #define CONFIG_CMDLINE_TAG
 273 #define CONFIG_REVISION_TAG
 274 #define CONFIG_SETUP_MEMORY_TAGS
 275 #define CONFIG_BOOTARGS         \
 276         "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
 277 #define CONFIG_EXTRA_ENV_SETTINGS       "hwconfig=dsp:wake=yes"
 278
 279 /*
 280  * U-Boot commands
 281  */
 282 #define CONFIG_CMD_ENV
 283 #define CONFIG_CMD_DIAG
 284 #define CONFIG_CMD_SAVES
 285
 286 #ifdef CONFIG_CMD_BDI
 287 #define CONFIG_CLOCKS
 288 #endif
 289
 290 #ifndef CONFIG_DRIVER_TI_EMAC
 291 #endif
 292
 293 #ifdef CONFIG_USE_NAND
 294 #define CONFIG_CMD_NAND
 295
 296 #define CONFIG_CMD_MTDPARTS
 297 #define CONFIG_MTD_DEVICE
 298 #define CONFIG_MTD_PARTITIONS
 299 #define CONFIG_LZO
 300 #define CONFIG_RBTREE
 301 #define CONFIG_CMD_UBIFS
 302 #endif
 303
 304 #ifdef CONFIG_USE_SPIFLASH
 305 #endif
 306
 307 #if !defined(CONFIG_USE_NAND) && \
 308         !defined(CONFIG_USE_NOR) && \
 309         !defined(CONFIG_USE_SPIFLASH)
 310 #define CONFIG_ENV_IS_NOWHERE
 311 #define CONFIG_SYS_NO_FLASH
 312 #define CONFIG_ENV_SIZE         (16 << 10)
 313 #undef CONFIG_CMD_ENV
 314 #endif
 315
 316 /* SD/MMC configuration */
 317 #ifndef CONFIG_USE_NOR
 318 #define CONFIG_MMC
 319 #define CONFIG_DAVINCI_MMC_SD1
 320 #define CONFIG_GENERIC_MMC
 321 #define CONFIG_DAVINCI_MMC
 322 #endif
 323
 324 /*
 325  * Enable MMC commands only when
 326  * MMC support is present
 327  */
 328 #ifdef CONFIG_MMC
 329 #define CONFIG_DOS_PARTITION
 330 #endif
 331
 332 #ifndef CONFIG_DIRECT_NOR_BOOT
 333 /* defines for SPL */
 334 #define CONFIG_SPL_FRAMEWORK
 335 #define CONFIG_SPL_BOARD_INIT
 336 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 337                                                 CONFIG_SYS_MALLOC_LEN)
 338 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 339 #define CONFIG_SPL_SPI_LOAD
 340 #define CONFIG_SPL_LDSCRIPT     "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
 341 #define CONFIG_SPL_STACK        0x8001ff00
 342 #define CONFIG_SPL_TEXT_BASE    0x80000000
 343 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 344 #define CONFIG_SPL_PAD_TO       32768
 345 #endif
 346
 347 /* Load U-Boot Image From MMC */
 348 #ifdef CONFIG_SPL_MMC_LOAD
 349 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
 350 #undef CONFIG_SPL_SPI_LOAD
 351 #endif
 352
 353 /* additions for new relocation code, must added to all boards */
 354 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 355
 356 #ifdef CONFIG_DIRECT_NOR_BOOT
 357 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 358 #else
 359 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 360                                         GENERATED_GBL_DATA_SIZE)
 361 #endif /* CONFIG_DIRECT_NOR_BOOT */
 362 #endif /* __CONFIG_H */