include/configs/io.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12 #define CONFIG_IO               1       /*  on a Io board */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 /*
  17  * Include common defines/options for all AMCC eval boards
  18  */
  19 #define CONFIG_HOSTNAME         io
  20 #include "amcc-common.h"
  21
  22 #define CONFIG_BOARD_EARLY_INIT_R
  23 #define CONFIG_MISC_INIT_R
  24 #define CONFIG_LAST_STAGE_INIT
  25
  26 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  27
  28 /*
  29  * Configure PLL
  30  */
  31 #define PLLMR0_DEFAULT PLLMR0_266_133_66
  32 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  33
  34 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  35
  36 /*
  37  * Default environment variables
  38  */
  39 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  40         CONFIG_AMCC_DEF_ENV                                             \
  41         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  42         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  43         "kernel_addr=fc000000\0"                                        \
  44         "fdt_addr=fc1e0000\0"                                           \
  45         "ramdisk_addr=fc200000\0"                                       \
  46         ""
  47
  48 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  49 #define CONFIG_HAS_ETH0
  50 #define CONFIG_HAS_ETH1
  51 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  52 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  53
  54 /*
  55  * Commands additional to the ones defined in amcc-common.h
  56  */
  57 #undef CONFIG_CMD_IRQ
  58
  59 /*
  60  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  61  */
  62 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  63
  64 /* SDRAM timings used in datasheet */
  65 #define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  66 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  67 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  68 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  69 #define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  70
  71 /*
  72  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  73  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  74  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  75  * The Linux BASE_BAUD define should match this configuration.
  76  *    baseBaud = cpuClock/(uartDivisor*16)
  77  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  78  * set Linux BASE_BAUD to 403200.
  79  */
  80 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  81 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
  82 #undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
  83 #define CONFIG_SYS_BASE_BAUD            691200
  84
  85 /*
  86  * I2C stuff
  87  */
  88 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  89
  90 /* Temp sensor/hwmon/dtt */
  91
  92 /*
  93  * FLASH organization
  94  */
  95 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
  96 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
  97
  98 #define CONFIG_SYS_FLASH_BASE           0xFC000000
  99 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 100
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 103
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 106
 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 108
 109 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 110 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 111
 112 #ifdef CONFIG_ENV_IS_IN_FLASH
 113 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 114 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 115 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 116
 117 /* Address and size of Redundant Environment Sector     */
 118 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 119 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 120 #endif
 121
 122 /* Gbit PHYs */
 123 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 124 #define CONFIG_BITBANGMII_MULTI
 125
 126 #define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13) /* our MDIO is GPIO0 */
 127 #define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)  /* our MDC  is GPIO7 */
 128
 129 #define CONFIG_SYS_GBIT_MII_BUSNAME     "io_miiphy"
 130
 131 /*
 132  * PPC405 GPIO Configuration
 133  */
 134 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 135 { \
 136 /* GPIO Core 0 */ \
 137 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 138 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 139 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 140 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 141 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 142 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 143 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 144 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 145 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 146 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 147 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 148 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 149 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 150 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 151 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 152 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 153 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 154 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 155 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 156 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 157 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 158 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 159 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 160 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 161 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 162 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 163 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 164 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 165 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 166 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 167 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 168 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 169 } \
 170 }
 171
 172 /*
 173  * Definitions for initial stack pointer and data area (in data cache)
 174  */
 175 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 176 #define CONFIG_SYS_TEMP_STACK_OCM        1
 177
 178 /* On Chip Memory location */
 179 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 180 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 181 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 182 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE
 183
 184 #define CONFIG_SYS_GBL_DATA_OFFSET \
 185         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 186 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 187
 188 /*
 189  * External Bus Controller (EBC) Setup
 190  */
 191
 192 /* Memory Bank 0 (NOR-FLASH) initialization */
 193 #define CONFIG_SYS_EBC_PB0AP            0xa382a880
 194 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 195 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 196
 197 /* Memory Bank 1 (NVRAM) initializatio */
 198 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 199 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 200 #define CONFIG_SYS_EBC_PB1CR            0x7f318000
 201
 202 /* Memory Bank 2 (FPGA) initialization */
 203 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 204 #define CONFIG_SYS_EBC_PB2AP            0x02025080
 205 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 206 #define CONFIG_SYS_EBC_PB2CR            0x7f11a000
 207
 208 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 209 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 210
 211 #define CONFIG_SYS_FPGA_COUNT           1
 212
 213 #define CONFIG_SYS_FPGA_PTR \
 214         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
 215
 216 #define CONFIG_SYS_FPGA_COMMON
 217
 218 /* Memory Bank 3 (Latches) initialization */
 219 #define CONFIG_SYS_LATCH_BASE           0x7f200000
 220 #define CONFIG_SYS_EBC_PB3AP            0xa2015480
 221 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 222 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 223
 224 #define CONFIG_SYS_LATCH0_RESET         0xffff
 225 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 226 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 227 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 228
 229 #endif  /* __CONFIG_H */