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1 /*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2010-2011
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15 /*
16 * for linking errors see
17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
18 */
19
20 #ifndef _CONFIG_KM_ARM_H
21 #define _CONFIG_KM_ARM_H
22
23 /*
24 * High Level Configuration Options (easy to change)
25 */
26 #define CONFIG_MARVELL
27 #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
28 #define CONFIG_KW88F6281 /* SOC Name */
29
30 #define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
31
32 #define CONFIG_NAND_ECC_BCH
33
34 /* include common defines/options for all Keymile boards */
35 #include "keymile-common.h"
36
37 /* SPI NOR Flash default params, used by sf commands */
38 #define CONFIG_SF_DEFAULT_SPEED 8100000
39 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
40
41 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
42 #define CONFIG_ENV_SPI_BUS 0
43 #define CONFIG_ENV_SPI_CS 0
44 #define CONFIG_ENV_SPI_MAX_HZ 8100000
45 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
46 #endif
47
48 /* Reserve 4 MB for malloc */
49 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
50
51 #include "asm/arch/config.h"
52
53 #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
54 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
55 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
56 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
57
58 /* pseudo-non volatile RAM [hex] */
59 #define CONFIG_KM_PNVRAM 0x80000
60 /* physical RAM MTD size [hex] */
61 #define CONFIG_KM_PHRAM 0x17F000
62
63 #define CONFIG_KM_CRAMFS_ADDR 0x2400000
64 #define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
65 #define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
66
67 /* architecture specific default bootargs */
68 #define CONFIG_KM_DEF_BOOT_ARGS_CPU \
69 "bootcountaddr=${bootcountaddr} ${mtdparts}" \
70 " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
71
72 #define CONFIG_KM_DEF_ENV_CPU \
73 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
74 CONFIG_KM_UPDATE_UBOOT \
75 "set_fdthigh=setenv fdt_high ${kernelmem}\0" \
76 "checkfdt=" \
77 "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \
78 "then true; else setenv cramfsloadfdt true; " \
79 "setenv boot bootm ${load_addr_r}; " \
80 "echo No FDT found, booting with the kernel " \
81 "appended one; fi\0" \
82 ""
83
84 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
85 #define CONFIG_MISC_INIT_R
86
87 /*
88 * NS16550 Configuration
89 */
90 #define CONFIG_SYS_NS16550_SERIAL
91 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
92 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
93 #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
94 #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
95
96 /*
97 * Serial Port configuration
98 * The following definitions let you select what serial you want to use
99 * for your console driver.
100 */
101
102 #define CONFIG_CONS_INDEX 1 /* Console on UART0 */
103
104 /*
105 * For booting Linux, the board info and command line data
106 * have to be in the first 8 MB of memory, since this is
107 * the maximum mapped by the Linux kernel during initialization.
108 */
109 #define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
110 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
111 #define CONFIG_INITRD_TAG /* enable INITRD tag */
112 #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
113
114 /*
115 * NAND Flash configuration
116 */
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1
118
119 #define BOOTFLASH_START 0x0
120
121 /* Kirkwood has two serial IF */
122 #if (CONFIG_CONS_INDEX == 2)
123 #define CONFIG_KM_CONSOLE_TTY "ttyS1"
124 #else
125 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
126 #endif
127
128 /*
129 * Other required minimal configurations
130 */
131 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
132 #define CONFIG_NR_DRAM_BANKS 4
133 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
134
135 /*
136 * Ethernet Driver configuration
137 */
138 #define CONFIG_NETCONSOLE /* include NetConsole support */
139 #define CONFIG_MII /* expose smi ove miiphy interface */
140 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
141 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
142 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
143 #define CONFIG_PHY_BASE_ADR 0
144 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
145 #define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
146
147 /*
148 * I2C related stuff
149 */
150 #undef CONFIG_I2C_MVTWSI
151 #define CONFIG_SYS_I2C
152 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
153 #define CONFIG_SYS_I2C_INIT_BOARD
154
155 #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
156 #define CONFIG_SYS_NUM_I2C_BUSES 6
157 #define CONFIG_SYS_I2C_MAX_HOPS 1
158 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
159 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
160 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
161 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
162 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
163 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
164 }
165
166 #ifndef __ASSEMBLY__
167 #include <asm/arch/gpio.h>
168 extern void __set_direction(unsigned pin, int high);
169 void set_sda(int state);
170 void set_scl(int state);
171 int get_sda(void);
172 int get_scl(void);
173 #define KM_KIRKWOOD_SDA_PIN 8
174 #define KM_KIRKWOOD_SCL_PIN 9
175 #define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
176 #define KM_KIRKWOOD_ENV_WP 38
177
178 #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
179 #define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1)
180 #define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
181 #define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
182 #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
183 #endif
184
185 #define I2C_DELAY udelay(1)
186 #define I2C_SOFT_DECLARATIONS
187
188 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x0
189 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
190
191 /* EEprom support 24C128, 24C256 valid for environment eeprom */
192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
195
196 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
197 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
198
199 /*
200 * Environment variables configurations
201 */
202 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
203 #define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
204 #define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
205 #define CONFIG_ENV_SECT_SIZE 0x10000
206 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
207 CONFIG_ENV_SECT_SIZE)
208 #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
209 #else
210 #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
211 #define CONFIG_ENV_EEPROM_IS_ON_I2C
212 #define CONFIG_SYS_EEPROM_WREN
213 #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
214 #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
215 #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
216 #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
217 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
218 #endif
219
220 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
221
222
223 /* SPI bus claim MPP configuration */
224 #define CONFIG_SYS_KW_SPI_MPP 0x0
225
226 #define FLASH_GPIO_PIN 0x00010000
227 #define KM_FLASH_GPIO_PIN 16
228
229 #define CONFIG_KM_UPDATE_UBOOT \
230 "update=" \
231 "sf probe 0;sf erase 0 +${filesize};" \
232 "sf write ${load_addr_r} 0 ${filesize};\0"
233
234 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
235 #define CONFIG_KM_NEW_ENV \
236 "newenv=sf probe 0;" \
237 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
238 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
239 #else
240 #define CONFIG_KM_NEW_ENV \
241 "newenv=setenv addr 0x100000 && " \
242 "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \
243 "mw.b ${addr} 0 4 && " \
244 "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
245 " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
246 "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
247 " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
248 #endif
249
250 #ifndef CONFIG_KM_BOARD_EXTRA_ENV
251 #define CONFIG_KM_BOARD_EXTRA_ENV ""
252 #endif
253
254 /*
255 * Default environment variables
256 */
257 #define CONFIG_EXTRA_ENV_SETTINGS \
258 CONFIG_KM_BOARD_EXTRA_ENV \
259 CONFIG_KM_DEF_ENV \
260 CONFIG_KM_NEW_ENV \
261 "arch=arm\0" \
262 ""
263
264 #if !defined(CONFIG_MTD_NOR_FLASH)
265 #undef CONFIG_FLASH_CFI_MTD
266 #undef CONFIG_JFFS2_CMDLINE
267 #endif
268
269 /* additions for new relocation code, must be added to all boards */
270 #define CONFIG_SYS_SDRAM_BASE 0x00000000
271 /* Do early setups now in board_init_f() */
272
273 /*
274 * resereved pram area at the end of memroy [hex]
275 * 8Mbytes for switch + 4Kbytes for bootcount
276 */
277 #define CONFIG_KM_RESERVED_PRAM 0x801000
278 /* address for the bootcount (taken from end of RAM) */
279 #define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
280 /* Use generic bootcount RAM driver */
281 #define CONFIG_BOOTCOUNT_RAM
282
283 /* enable POST tests */
284 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
285 #define CONFIG_POST_SKIP_ENV_FLAGS
286 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
287
288 /* we do the whole PCIe FPGA config stuff here */
289
290 #endif /* _CONFIG_KM_ARM_H */