include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19
  20 #define CONFIG_DEEP_SLEEP
  21
  22 /*
  23  * Size of malloc() pool
  24  */
  25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  29
  30 /*
  31  * Generic Timer Definitions
  32  */
  33 #define GENERIC_TIMER_CLK               12500000
  34
  35 #ifndef __ASSEMBLY__
  36 unsigned long get_board_sys_clk(void);
  37 unsigned long get_board_ddr_clk(void);
  38 #endif
  39
  40 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  41 #define CONFIG_SYS_CLK_FREQ             100000000
  42 #define CONFIG_DDR_CLK_FREQ             100000000
  43 #define CONFIG_QIXIS_I2C_ACCESS
  44 #else
  45 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  46 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  47 #endif
  48
  49 #ifdef CONFIG_RAMBOOT_PBL
  50 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  51 #endif
  52
  53 #ifdef CONFIG_SD_BOOT
  54 #ifdef CONFIG_SD_BOOT_QSPI
  55 #define CONFIG_SYS_FSL_PBL_RCW  \
  56         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  57 #else
  58 #define CONFIG_SYS_FSL_PBL_RCW  \
  59         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  60 #endif
  61 #define CONFIG_SPL_FRAMEWORK
  62 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  63
  64 #define CONFIG_SPL_TEXT_BASE            0x10000000
  65 #define CONFIG_SPL_MAX_SIZE             0x1a000
  66 #define CONFIG_SPL_STACK                0x1001d000
  67 #define CONFIG_SPL_PAD_TO               0x1c000
  68 #define CONFIG_SYS_TEXT_BASE            0x82000000
  69
  70 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  71                 CONFIG_SYS_MONITOR_LEN)
  72 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  73 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  74 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  75 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  76 #endif
  77
  78 #ifdef CONFIG_QSPI_BOOT
  79 #define CONFIG_SYS_TEXT_BASE            0x40010000
  80 #endif
  81
  82 #ifdef CONFIG_NAND_BOOT
  83 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  84 #define CONFIG_SPL_FRAMEWORK
  85 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  86
  87 #define CONFIG_SPL_TEXT_BASE            0x10000000
  88 #define CONFIG_SPL_MAX_SIZE             0x1a000
  89 #define CONFIG_SPL_STACK                0x1001d000
  90 #define CONFIG_SPL_PAD_TO               0x1c000
  91 #define CONFIG_SYS_TEXT_BASE            0x82000000
  92
  93 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  94 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  95 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  96 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  97 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  98
  99 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 100 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 101 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 102 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 103 #define CONFIG_SYS_MONITOR_LEN          0x80000
 104 #endif
 105
 106 #ifndef CONFIG_SYS_TEXT_BASE
 107 #define CONFIG_SYS_TEXT_BASE            0x60100000
 108 #endif
 109
 110 #define CONFIG_NR_DRAM_BANKS            1
 111
 112 #define CONFIG_DDR_SPD
 113 #define SPD_EEPROM_ADDRESS              0x51
 114 #define CONFIG_SYS_SPD_BUS_NUM          0
 115
 116 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
 117 #ifndef CONFIG_SYS_FSL_DDR4
 118 #define CONFIG_SYS_DDR_RAW_TIMING
 119 #endif
 120 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 121 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 122
 123 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 124 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 125
 126 #define CONFIG_DDR_ECC
 127 #ifdef CONFIG_DDR_ECC
 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 129 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 130 #endif
 131
 132 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 133
 134 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 135         !defined(CONFIG_QSPI_BOOT)
 136 #define CONFIG_U_QE
 137 #endif
 138
 139 /*
 140  * IFC Definitions
 141  */
 142 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 143 #define CONFIG_FSL_IFC
 144 #define CONFIG_SYS_FLASH_BASE           0x60000000
 145 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 146
 147 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 148 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 149                                 CSPR_PORT_SIZE_16 | \
 150                                 CSPR_MSEL_NOR | \
 151                                 CSPR_V)
 152 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 153 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 154                                 + 0x8000000) | \
 155                                 CSPR_PORT_SIZE_16 | \
 156                                 CSPR_MSEL_NOR | \
 157                                 CSPR_V)
 158 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 159
 160 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 161                                         CSOR_NOR_TRHZ_80)
 162 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 163                                         FTIM0_NOR_TEADC(0x5) | \
 164                                         FTIM0_NOR_TEAHC(0x5))
 165 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 166                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 167                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 168 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 169                                         FTIM2_NOR_TCH(0x4) | \
 170                                         FTIM2_NOR_TWPH(0xe) | \
 171                                         FTIM2_NOR_TWP(0x1c))
 172 #define CONFIG_SYS_NOR_FTIM3            0
 173
 174 #define CONFIG_FLASH_CFI_DRIVER
 175 #define CONFIG_SYS_FLASH_CFI
 176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 177 #define CONFIG_SYS_FLASH_QUIET_TEST
 178 #define CONFIG_FLASH_SHOW_PROGRESS      45
 179 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 180 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 184 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 185 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 186
 187 #define CONFIG_SYS_FLASH_EMPTY_INFO
 188 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 189                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 190
 191 /*
 192  * NAND Flash Definitions
 193  */
 194 #define CONFIG_NAND_FSL_IFC
 195
 196 #define CONFIG_SYS_NAND_BASE            0x7e800000
 197 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 198
 199 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 200
 201 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 202                                 | CSPR_PORT_SIZE_8      \
 203                                 | CSPR_MSEL_NAND        \
 204                                 | CSPR_V)
 205 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 206 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 207                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 208                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 209                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 210                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 211                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 212                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 213
 214 #define CONFIG_SYS_NAND_ONFI_DETECTION
 215
 216 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 217                                         FTIM0_NAND_TWP(0x18)   | \
 218                                         FTIM0_NAND_TWCHT(0x7) | \
 219                                         FTIM0_NAND_TWH(0xa))
 220 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 221                                         FTIM1_NAND_TWBE(0x39)  | \
 222                                         FTIM1_NAND_TRR(0xe)   | \
 223                                         FTIM1_NAND_TRP(0x18))
 224 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 225                                         FTIM2_NAND_TREH(0xa) | \
 226                                         FTIM2_NAND_TWHRE(0x1e))
 227 #define CONFIG_SYS_NAND_FTIM3           0x0
 228
 229 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 230 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 231 #define CONFIG_CMD_NAND
 232
 233 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 234 #endif
 235
 236 /*
 237  * QIXIS Definitions
 238  */
 239 #define CONFIG_FSL_QIXIS
 240
 241 #ifdef CONFIG_FSL_QIXIS
 242 #define QIXIS_BASE                      0x7fb00000
 243 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 244 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 245 #define QIXIS_LBMAP_SWITCH              6
 246 #define QIXIS_LBMAP_MASK                0x0f
 247 #define QIXIS_LBMAP_SHIFT               0
 248 #define QIXIS_LBMAP_DFLTBANK            0x00
 249 #define QIXIS_LBMAP_ALTBANK             0x04
 250 #define QIXIS_PWR_CTL                   0x21
 251 #define QIXIS_PWR_CTL_POWEROFF          0x80
 252 #define QIXIS_RST_CTL_RESET             0x44
 253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 254 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 256 #define QIXIS_CTL_SYS                   0x5
 257 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 258 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 259 #define QIXIS_RST_FORCE_3               0x45
 260 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 261 #define QIXIS_PWR_CTL2                  0x21
 262 #define QIXIS_PWR_CTL2_PCTL             0x2
 263
 264 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 265 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 266                                         CSPR_PORT_SIZE_8 | \
 267                                         CSPR_MSEL_GPCM | \
 268                                         CSPR_V)
 269 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 270 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 271                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 272                                         CSOR_NOR_TRHZ_80)
 273
 274 /*
 275  * QIXIS Timing parameters for IFC GPCM
 276  */
 277 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 278                                         FTIM0_GPCM_TEADC(0xe) | \
 279                                         FTIM0_GPCM_TEAHC(0xe))
 280 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 281                                         FTIM1_GPCM_TRAD(0x1f))
 282 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 283                                         FTIM2_GPCM_TCH(0xe) | \
 284                                         FTIM2_GPCM_TWP(0xf0))
 285 #define CONFIG_SYS_FPGA_FTIM3           0x0
 286 #endif
 287
 288 #if defined(CONFIG_NAND_BOOT)
 289 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 290 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 291 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 292 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 293 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 294 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 295 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 296 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 297 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 298 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 299 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 300 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 301 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 302 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 303 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 304 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 305 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 306 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 307 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 308 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 309 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 310 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 311 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 312 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 313 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 314 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 315 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 316 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 317 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 318 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 319 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 320 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 321 #else
 322 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 323 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 324 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 325 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 326 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 327 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 328 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 329 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 330 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 331 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 332 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 333 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 334 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 335 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 336 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 337 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 338 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 339 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 340 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 341 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 342 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 343 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 344 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 345 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 346 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 347 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 348 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 349 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 350 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 351 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 352 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 353 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 354 #endif
 355
 356 /*
 357  * Serial Port
 358  */
 359 #ifdef CONFIG_LPUART
 360 #define CONFIG_LPUART_32B_REG
 361 #else
 362 #define CONFIG_CONS_INDEX               1
 363 #define CONFIG_SYS_NS16550_SERIAL
 364 #ifndef CONFIG_DM_SERIAL
 365 #define CONFIG_SYS_NS16550_REG_SIZE     1
 366 #endif
 367 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 368 #endif
 369
 370 #define CONFIG_BAUDRATE                 115200
 371
 372 /*
 373  * I2C
 374  */
 375 #define CONFIG_SYS_I2C
 376 #define CONFIG_SYS_I2C_MXC
 377 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 378 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 379 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 380
 381 /*
 382  * I2C bus multiplexer
 383  */
 384 #define I2C_MUX_PCA_ADDR_PRI            0x77
 385 #define I2C_MUX_CH_DEFAULT              0x8
 386 #define I2C_MUX_CH_CH7301               0xC
 387
 388 /*
 389  * MMC
 390  */
 391 #define CONFIG_FSL_ESDHC
 392
 393 /* SPI */
 394 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 395 /* QSPI */
 396 #define QSPI0_AMBA_BASE                 0x40000000
 397 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 398 #define FSL_QSPI_FLASH_NUM              2
 399
 400 /* DSPI */
 401
 402 /* DM SPI */
 403 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 404 #define CONFIG_DM_SPI_FLASH
 405 #define CONFIG_SPI_FLASH_DATAFLASH
 406 #endif
 407 #endif
 408
 409 /*
 410  * USB
 411  */
 412 /* EHCI Support - disbaled by default */
 413 /*#define CONFIG_HAS_FSL_DR_USB*/
 414
 415 #ifdef CONFIG_HAS_FSL_DR_USB
 416 #define CONFIG_USB_EHCI
 417 #define CONFIG_USB_EHCI_FSL
 418 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 419 #endif
 420
 421 /*XHCI Support - enabled by default*/
 422 #define CONFIG_HAS_FSL_XHCI_USB
 423
 424 #ifdef CONFIG_HAS_FSL_XHCI_USB
 425 #define CONFIG_USB_XHCI_FSL
 426 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 427 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 428 #endif
 429
 430 /*
 431  * Video
 432  */
 433 #define CONFIG_FSL_DCU_FB
 434
 435 #ifdef CONFIG_FSL_DCU_FB
 436 #define CONFIG_CMD_BMP
 437 #define CONFIG_VIDEO_LOGO
 438 #define CONFIG_VIDEO_BMP_LOGO
 439
 440 #define CONFIG_FSL_DIU_CH7301
 441 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 442 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 443 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 444 #endif
 445
 446 /*
 447  * eTSEC
 448  */
 449 #define CONFIG_TSEC_ENET
 450
 451 #ifdef CONFIG_TSEC_ENET
 452 #define CONFIG_MII
 453 #define CONFIG_MII_DEFAULT_TSEC         3
 454 #define CONFIG_TSEC1                    1
 455 #define CONFIG_TSEC1_NAME               "eTSEC1"
 456 #define CONFIG_TSEC2                    1
 457 #define CONFIG_TSEC2_NAME               "eTSEC2"
 458 #define CONFIG_TSEC3                    1
 459 #define CONFIG_TSEC3_NAME               "eTSEC3"
 460
 461 #define TSEC1_PHY_ADDR                  1
 462 #define TSEC2_PHY_ADDR                  2
 463 #define TSEC3_PHY_ADDR                  3
 464
 465 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 466 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 467 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 468
 469 #define TSEC1_PHYIDX                    0
 470 #define TSEC2_PHYIDX                    0
 471 #define TSEC3_PHYIDX                    0
 472
 473 #define CONFIG_ETHPRIME                 "eTSEC1"
 474
 475 #define CONFIG_PHY_GIGE
 476 #define CONFIG_PHYLIB
 477 #define CONFIG_PHY_REALTEK
 478
 479 #define CONFIG_HAS_ETH0
 480 #define CONFIG_HAS_ETH1
 481 #define CONFIG_HAS_ETH2
 482
 483 #define CONFIG_FSL_SGMII_RISER          1
 484 #define SGMII_RISER_PHY_OFFSET          0x1b
 485
 486 #ifdef CONFIG_FSL_SGMII_RISER
 487 #define CONFIG_SYS_TBIPA_VALUE          8
 488 #endif
 489
 490 #endif
 491
 492 /* PCIe */
 493 #define CONFIG_PCIE1            /* PCIE controller 1 */
 494 #define CONFIG_PCIE2            /* PCIE controller 2 */
 495
 496 #ifdef CONFIG_PCI
 497 #define CONFIG_PCI_SCAN_SHOW
 498 #define CONFIG_CMD_PCI
 499 #endif
 500
 501 #define CONFIG_CMDLINE_TAG
 502 #define CONFIG_CMDLINE_EDITING
 503
 504 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 505 #define CONFIG_LAYERSCAPE_NS_ACCESS
 506 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 507 #define CONFIG_TIMER_CLK_FREQ           12500000
 508
 509 #define CONFIG_HWCONFIG
 510 #define HWCONFIG_BUFFER_SIZE            256
 511
 512 #define CONFIG_FSL_DEVICE_DISABLE
 513
 514
 515 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 516
 517 #ifdef CONFIG_LPUART
 518 #define CONFIG_EXTRA_ENV_SETTINGS       \
 519         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 520         "fdt_high=0xffffffff\0"         \
 521         "initrd_high=0xffffffff\0"      \
 522         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 523 #else
 524 #define CONFIG_EXTRA_ENV_SETTINGS       \
 525         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 526         "fdt_high=0xffffffff\0"         \
 527         "initrd_high=0xffffffff\0"      \
 528         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 529 #endif
 530
 531 /*
 532  * Miscellaneous configurable options
 533  */
 534 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 535 #define CONFIG_AUTO_COMPLETE
 536 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 537 #define CONFIG_SYS_PBSIZE               \
 538                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 539 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 540 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 541
 542 #define CONFIG_SYS_MEMTEST_START        0x80000000
 543 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 544
 545 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 546
 547 #define CONFIG_LS102XA_STREAM_ID
 548
 549 /*
 550  * Stack sizes
 551  * The stack sizes are set up in start.S using the settings below
 552  */
 553 #define CONFIG_STACKSIZE                (30 * 1024)
 554
 555 #define CONFIG_SYS_INIT_SP_OFFSET \
 556         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 557 #define CONFIG_SYS_INIT_SP_ADDR \
 558         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 559
 560 #ifdef CONFIG_SPL_BUILD
 561 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 562 #else
 563 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 564 #endif
 565
 566 /*
 567  * Environment
 568  */
 569 #define CONFIG_ENV_OVERWRITE
 570
 571 #if defined(CONFIG_SD_BOOT)
 572 #define CONFIG_ENV_OFFSET               0x100000
 573 #define CONFIG_ENV_IS_IN_MMC
 574 #define CONFIG_SYS_MMC_ENV_DEV          0
 575 #define CONFIG_ENV_SIZE                 0x2000
 576 #elif defined(CONFIG_QSPI_BOOT)
 577 #define CONFIG_ENV_IS_IN_SPI_FLASH
 578 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 579 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 580 #define CONFIG_ENV_SECT_SIZE            0x10000
 581 #elif defined(CONFIG_NAND_BOOT)
 582 #define CONFIG_ENV_IS_IN_NAND
 583 #define CONFIG_ENV_SIZE                 0x2000
 584 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 585 #else
 586 #define CONFIG_ENV_IS_IN_FLASH
 587 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 588 #define CONFIG_ENV_SIZE                 0x2000
 589 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 590 #endif
 591
 592 #define CONFIG_MISC_INIT_R
 593
 594 /* Hash command with SHA acceleration supported in hardware */
 595 #ifdef CONFIG_FSL_CAAM
 596 #define CONFIG_CMD_HASH
 597 #define CONFIG_SHA_HW_ACCEL
 598 #endif
 599
 600 #include <asm/fsl_secure_boot.h>
 601 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 602
 603 #endif