include/configs/ls2080aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 unsigned long get_board_ddr_clk(void);
  15 #endif
  16
  17 #ifdef CONFIG_FSL_QSPI
  18 #undef CONFIG_CMD_IMLS
  19 #define CONFIG_QIXIS_I2C_ACCESS
  20 #define CONFIG_SYS_I2C_EARLY_INIT
  21 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  22 #endif
  23
  24 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  27 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  28
  29 #define CONFIG_DDR_SPD
  30 #define CONFIG_DDR_ECC
  31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  32 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  33 #define SPD_EEPROM_ADDRESS1     0x51
  34 #define SPD_EEPROM_ADDRESS2     0x52
  35 #define SPD_EEPROM_ADDRESS3     0x53
  36 #define SPD_EEPROM_ADDRESS4     0x54
  37 #define SPD_EEPROM_ADDRESS5     0x55
  38 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  39 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  40 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  41 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  42 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  43 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  44 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  45 #endif
  46 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  47
  48 /* SATA */
  49 #define CONFIG_LIBATA
  50 #define CONFIG_SCSI_AHCI
  51 #define CONFIG_SCSI_AHCI_PLAT
  52 #define CONFIG_SCSI
  53
  54 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  55 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  56
  57 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  58 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  59 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  60                                                 CONFIG_SYS_SCSI_MAX_LUN)
  61
  62 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  63
  64 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  65 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  66 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  67
  68 #define CONFIG_SYS_NOR0_CSPR                                    \
  69         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  70         CSPR_PORT_SIZE_16                                       | \
  71         CSPR_MSEL_NOR                                           | \
  72         CSPR_V)
  73 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  74         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  75         CSPR_PORT_SIZE_16                                       | \
  76         CSPR_MSEL_NOR                                           | \
  77         CSPR_V)
  78 #define CONFIG_SYS_NOR1_CSPR                                    \
  79         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  80         CSPR_PORT_SIZE_16                                       | \
  81         CSPR_MSEL_NOR                                           | \
  82         CSPR_V)
  83 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  84         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  85         CSPR_PORT_SIZE_16                                       | \
  86         CSPR_MSEL_NOR                                           | \
  87         CSPR_V)
  88 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  89 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  90                                 FTIM0_NOR_TEADC(0x5) | \
  91                                 FTIM0_NOR_TEAHC(0x5))
  92 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  93                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  94                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  95 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  96                                 FTIM2_NOR_TCH(0x4) | \
  97                                 FTIM2_NOR_TWPH(0x0E) | \
  98                                 FTIM2_NOR_TWP(0x1c))
  99 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 100 #define CONFIG_SYS_IFC_CCR      0x01000000
 101
 102 #ifdef CONFIG_MTD_NOR_FLASH
 103 #define CONFIG_FLASH_CFI_DRIVER
 104 #define CONFIG_SYS_FLASH_CFI
 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 106 #define CONFIG_SYS_FLASH_QUIET_TEST
 107 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 108
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 110 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 111 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 112 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 113
 114 #define CONFIG_SYS_FLASH_EMPTY_INFO
 115 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 116                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 117 #endif
 118
 119 #define CONFIG_NAND_FSL_IFC
 120 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 121 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 122
 123 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 124 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 125                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 126                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 127                                 | CSPR_V)
 128 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 129
 130 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 131                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 132                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 133                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 134                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 135                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 136                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 137
 138 #define CONFIG_SYS_NAND_ONFI_DETECTION
 139
 140 /* ONFI NAND Flash mode0 Timing Params */
 141 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 142                                         FTIM0_NAND_TWP(0x18)   | \
 143                                         FTIM0_NAND_TWCHT(0x07) | \
 144                                         FTIM0_NAND_TWH(0x0a))
 145 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 146                                         FTIM1_NAND_TWBE(0x39)  | \
 147                                         FTIM1_NAND_TRR(0x0e)   | \
 148                                         FTIM1_NAND_TRP(0x18))
 149 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 150                                         FTIM2_NAND_TREH(0x0a) | \
 151                                         FTIM2_NAND_TWHRE(0x1e))
 152 #define CONFIG_SYS_NAND_FTIM3           0x0
 153
 154 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 156 #define CONFIG_MTD_NAND_VERIFY_WRITE
 157 #define CONFIG_CMD_NAND
 158
 159 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 160
 161 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 162 #define QIXIS_LBMAP_SWITCH              0x06
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_LBMAP_NAND                0x09
 168 #define QIXIS_LBMAP_QSPI                0x0f
 169 #define QIXIS_RST_CTL_RESET             0x31
 170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 171 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 173 #define QIXIS_RCW_SRC_NAND              0x107
 174 #define QIXIS_RCW_SRC_QSPI              0x62
 175 #define QIXIS_RST_FORCE_MEM             0x01
 176
 177 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 178 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 179                                 | CSPR_PORT_SIZE_8 \
 180                                 | CSPR_MSEL_GPCM \
 181                                 | CSPR_V)
 182 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 183                                 | CSPR_PORT_SIZE_8 \
 184                                 | CSPR_MSEL_GPCM \
 185                                 | CSPR_V)
 186
 187 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 188 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 189 /* QIXIS Timing parameters for IFC CS3 */
 190 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 191                                         FTIM0_GPCM_TEADC(0x0e) | \
 192                                         FTIM0_GPCM_TEAHC(0x0e))
 193 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 194                                         FTIM1_GPCM_TRAD(0x3f))
 195 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 196                                         FTIM2_GPCM_TCH(0xf) | \
 197                                         FTIM2_GPCM_TWP(0x3E))
 198 #define CONFIG_SYS_CS3_FTIM3            0x0
 199
 200 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 203 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 204 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 205 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 206 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 207 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 208 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 209 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 210 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 211 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 212 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 213 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 214 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 215 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 216 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 217 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 218 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 219 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 220 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 221 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 222 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 223 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 224 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 225 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 226 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 227 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 228
 229 #define CONFIG_ENV_IS_IN_NAND
 230 #define CONFIG_ENV_OFFSET               (896 * 1024)
 231 #define CONFIG_ENV_SECT_SIZE            0x20000
 232 #define CONFIG_ENV_SIZE                 0x2000
 233 #define CONFIG_SPL_PAD_TO               0x20000
 234 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 235 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 236 #else
 237 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 238 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 239 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 240 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 241 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 242 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 243 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 244 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 245 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 246 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 247 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 248 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 249 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 250 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 251 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 252 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 253 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 254 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 255 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 256 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 257 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 258 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 259 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 260 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 261 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 262 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 263 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 264
 265 #if defined(CONFIG_QSPI_BOOT)
 266 #define CONFIG_SYS_TEXT_BASE            0x20010000
 267 #define CONFIG_ENV_IS_IN_SPI_FLASH
 268 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 269 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 270 #define CONFIG_ENV_SECT_SIZE            0x10000
 271 #else
 272 #define CONFIG_ENV_IS_IN_FLASH
 273 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 274 #define CONFIG_ENV_SECT_SIZE            0x20000
 275 #define CONFIG_ENV_SIZE                 0x2000
 276 #endif
 277 #endif
 278
 279 /* Debug Server firmware */
 280 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 281 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 282
 283 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 284
 285 /*
 286  * I2C
 287  */
 288 #define I2C_MUX_PCA_ADDR                0x77
 289 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 290
 291 /* I2C bus multiplexer */
 292 #define I2C_MUX_CH_DEFAULT      0x8
 293
 294 /* SPI */
 295 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 296 #define CONFIG_SPI_FLASH
 297
 298 #ifdef CONFIG_FSL_DSPI
 299 #define CONFIG_SPI_FLASH_STMICRO
 300 #define CONFIG_SPI_FLASH_SST
 301 #define CONFIG_SPI_FLASH_EON
 302 #endif
 303
 304 #ifdef CONFIG_FSL_QSPI
 305 #define CONFIG_SPI_FLASH_SPANSION
 306 #define FSL_QSPI_FLASH_SIZE             (1 << 26) /* 64MB */
 307 #define FSL_QSPI_FLASH_NUM              4
 308 #endif
 309 /*
 310  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 311  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 312  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 313  */
 314 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 315
 316 #endif
 317
 318 /*
 319  * MMC
 320  */
 321 #ifdef CONFIG_MMC
 322 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 323         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 324 #endif
 325
 326 /*
 327  * RTC configuration
 328  */
 329 #define RTC
 330 #define CONFIG_RTC_DS3231               1
 331 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 332
 333 /* EEPROM */
 334 #define CONFIG_ID_EEPROM
 335 #define CONFIG_SYS_I2C_EEPROM_NXID
 336 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 340 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 341
 342 #define CONFIG_FSL_MEMAC
 343
 344 #ifdef CONFIG_PCI
 345 #define CONFIG_PCI_SCAN_SHOW
 346 #define CONFIG_CMD_PCI
 347 #endif
 348
 349 /*  MMC  */
 350 #ifdef CONFIG_MMC
 351 #define CONFIG_FSL_ESDHC
 352 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 353 #endif
 354
 355 /* Initial environment variables */
 356 #undef CONFIG_EXTRA_ENV_SETTINGS
 357 #ifdef CONFIG_SECURE_BOOT
 358 #define CONFIG_EXTRA_ENV_SETTINGS               \
 359         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 360         "loadaddr=0x80100000\0"                 \
 361         "kernel_addr=0x100000\0"                \
 362         "ramdisk_addr=0x800000\0"               \
 363         "ramdisk_size=0x2000000\0"              \
 364         "fdt_high=0xa0000000\0"                 \
 365         "initrd_high=0xffffffffffffffff\0"      \
 366         "kernel_start=0x581100000\0"            \
 367         "kernel_load=0xa0000000\0"              \
 368         "kernel_size=0x2800000\0"               \
 369         "mcmemsize=0x40000000\0"                \
 370         "mcinitcmd=esbc_validate 0x580c80000;"  \
 371         "esbc_validate 0x580cc0000;"            \
 372         "fsl_mc start mc 0x580300000"           \
 373         " 0x580800000 \0"
 374 #else
 375 #define CONFIG_EXTRA_ENV_SETTINGS               \
 376         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 377         "loadaddr=0x80100000\0"                 \
 378         "kernel_addr=0x100000\0"                \
 379         "ramdisk_addr=0x800000\0"               \
 380         "ramdisk_size=0x2000000\0"              \
 381         "fdt_high=0xa0000000\0"                 \
 382         "initrd_high=0xffffffffffffffff\0"      \
 383         "kernel_start=0x581100000\0"            \
 384         "kernel_load=0xa0000000\0"              \
 385         "kernel_size=0x2800000\0"               \
 386         "mcmemsize=0x40000000\0"                \
 387         "mcinitcmd=fsl_mc start mc 0x580300000" \
 388         " 0x580800000 \0"
 389 #endif /* CONFIG_SECURE_BOOT */
 390
 391
 392 #ifdef CONFIG_FSL_MC_ENET
 393 #define CONFIG_FSL_MEMAC
 394 #define CONFIG_PHYLIB
 395 #define CONFIG_PHYLIB_10G
 396 #define CONFIG_PHY_VITESSE
 397 #define CONFIG_PHY_REALTEK
 398 #define CONFIG_PHY_TERANETICS
 399 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 400 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 401 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 402 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 403
 404 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 405 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 406 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 407 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 408 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 409 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 410 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 411 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 412 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 413 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 414 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 415 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 416 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 417 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 418 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 419 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 420
 421 #define CONFIG_MII              /* MII PHY management */
 422 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 423 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 424
 425 #endif
 426
 427 /*
 428  * USB
 429  */
 430 #define CONFIG_HAS_FSL_XHCI_USB
 431 #define CONFIG_USB_XHCI_FSL
 432 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 433 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 434
 435 #include <asm/fsl_secure_boot.h>
 436
 437 #endif /* __LS2_QDS_H */