include/configs/p1_p2_rdb_pc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ RDB boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #ifdef CONFIG_36BIT
  16 #define CONFIG_PHYS_64BIT
  17 #endif
  18
  19 #if defined(CONFIG_P1020MBG)
  20 #define CONFIG_BOARDNAME "P1020MBG-PC"
  21 #define CONFIG_P1020
  22 #define CONFIG_VSC7385_ENET
  23 #define CONFIG_SLIC
  24 #define __SW_BOOT_MASK          0x03
  25 #define __SW_BOOT_NOR           0xe4
  26 #define __SW_BOOT_SD            0x54
  27 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  28 #endif
  29
  30 #if defined(CONFIG_P1020UTM)
  31 #define CONFIG_BOARDNAME "P1020UTM-PC"
  32 #define CONFIG_P1020
  33 #define __SW_BOOT_MASK          0x03
  34 #define __SW_BOOT_NOR           0xe0
  35 #define __SW_BOOT_SD            0x50
  36 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  37 #endif
  38
  39 #if defined(CONFIG_P1020RDB_PC)
  40 #define CONFIG_BOARDNAME "P1020RDB-PC"
  41 #define CONFIG_NAND_FSL_ELBC
  42 #define CONFIG_P1020
  43 #define CONFIG_VSC7385_ENET
  44 #define CONFIG_SLIC
  45 #define __SW_BOOT_MASK          0x03
  46 #define __SW_BOOT_NOR           0x5c
  47 #define __SW_BOOT_SPI           0x1c
  48 #define __SW_BOOT_SD            0x9c
  49 #define __SW_BOOT_NAND          0xec
  50 #define __SW_BOOT_PCIE          0x6c
  51 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  52 #endif
  53
  54 /*
  55  * P1020RDB-PD board has user selectable switches for evaluating different
  56  * frequency and boot options for the P1020 device. The table that
  57  * follow describe the available options. The front six binary number was in
  58  * accordance with SW3[1:6].
  59  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  60  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  61  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  62  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  63  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  64  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  65  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  66  */
  67 #if defined(CONFIG_P1020RDB_PD)
  68 #define CONFIG_BOARDNAME "P1020RDB-PD"
  69 #define CONFIG_NAND_FSL_ELBC
  70 #define CONFIG_P1020
  71 #define CONFIG_VSC7385_ENET
  72 #define CONFIG_SLIC
  73 #define __SW_BOOT_MASK          0x03
  74 #define __SW_BOOT_NOR           0x64
  75 #define __SW_BOOT_SPI           0x34
  76 #define __SW_BOOT_SD            0x24
  77 #define __SW_BOOT_NAND          0x44
  78 #define __SW_BOOT_PCIE          0x74
  79 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  80 /*
  81  * Dynamic MTD Partition support with mtdparts
  82  */
  83 #define CONFIG_MTD_DEVICE
  84 #define CONFIG_MTD_PARTITIONS
  85 #define CONFIG_CMD_MTDPARTS
  86 #define CONFIG_FLASH_CFI_MTD
  87 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
  88 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
  89                         "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
  90 #endif
  91
  92 #if defined(CONFIG_P1021RDB)
  93 #define CONFIG_BOARDNAME "P1021RDB-PC"
  94 #define CONFIG_NAND_FSL_ELBC
  95 #define CONFIG_P1021
  96 #define CONFIG_QE
  97 #define CONFIG_VSC7385_ENET
  98 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
  99                                                 addresses in the LBC */
 100 #define __SW_BOOT_MASK          0x03
 101 #define __SW_BOOT_NOR           0x5c
 102 #define __SW_BOOT_SPI           0x1c
 103 #define __SW_BOOT_SD            0x9c
 104 #define __SW_BOOT_NAND          0xec
 105 #define __SW_BOOT_PCIE          0x6c
 106 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 107 /*
 108  * Dynamic MTD Partition support with mtdparts
 109  */
 110 #define CONFIG_MTD_DEVICE
 111 #define CONFIG_MTD_PARTITIONS
 112 #define CONFIG_CMD_MTDPARTS
 113 #define CONFIG_FLASH_CFI_MTD
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 116 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 117                         "256k(dtb),4608k(kernel),9728k(fs)," \
 118                         "256k(qe-ucode-firmware),1280k(u-boot)"
 119 #else
 120 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 121 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 122                         "256k(dtb),4608k(kernel),9728k(fs)," \
 123                         "256k(qe-ucode-firmware),1280k(u-boot)"
 124 #endif
 125 #endif
 126
 127 #if defined(CONFIG_P1024RDB)
 128 #define CONFIG_BOARDNAME "P1024RDB"
 129 #define CONFIG_NAND_FSL_ELBC
 130 #define CONFIG_P1024
 131 #define CONFIG_SLIC
 132 #define __SW_BOOT_MASK          0xf3
 133 #define __SW_BOOT_NOR           0x00
 134 #define __SW_BOOT_SPI           0x08
 135 #define __SW_BOOT_SD            0x04
 136 #define __SW_BOOT_NAND          0x0c
 137 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 138 #endif
 139
 140 #if defined(CONFIG_P1025RDB)
 141 #define CONFIG_BOARDNAME "P1025RDB"
 142 #define CONFIG_NAND_FSL_ELBC
 143 #define CONFIG_P1025
 144 #define CONFIG_QE
 145 #define CONFIG_SLIC
 146
 147 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
 148                                                 addresses in the LBC */
 149 #define __SW_BOOT_MASK          0xf3
 150 #define __SW_BOOT_NOR           0x00
 151 #define __SW_BOOT_SPI           0x08
 152 #define __SW_BOOT_SD            0x04
 153 #define __SW_BOOT_NAND          0x0c
 154 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 155 #endif
 156
 157 #if defined(CONFIG_P2020RDB)
 158 #define CONFIG_BOARDNAME "P2020RDB-PCA"
 159 #define CONFIG_NAND_FSL_ELBC
 160 #define CONFIG_P2020
 161 #define CONFIG_VSC7385_ENET
 162 #define __SW_BOOT_MASK          0x03
 163 #define __SW_BOOT_NOR           0xc8
 164 #define __SW_BOOT_SPI           0x28
 165 #define __SW_BOOT_SD            0x68 /* or 0x18 */
 166 #define __SW_BOOT_NAND          0xe8
 167 #define __SW_BOOT_PCIE          0xa8
 168 #define CONFIG_SYS_L2_SIZE      (512 << 10)
 169 /*
 170  * Dynamic MTD Partition support with mtdparts
 171  */
 172 #define CONFIG_MTD_DEVICE
 173 #define CONFIG_MTD_PARTITIONS
 174 #define CONFIG_CMD_MTDPARTS
 175 #define CONFIG_FLASH_CFI_MTD
 176 #ifdef CONFIG_PHYS_64BIT
 177 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 178 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 179                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 180 #else
 181 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 182 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 183                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 184 #endif
 185 #endif
 186
 187 #ifdef CONFIG_SDCARD
 188 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 189 #define CONFIG_SPL_ENV_SUPPORT
 190 #define CONFIG_SPL_SERIAL_SUPPORT
 191 #define CONFIG_SPL_MMC_SUPPORT
 192 #define CONFIG_SPL_MMC_MINIMAL
 193 #define CONFIG_SPL_FLUSH_IMAGE
 194 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 195 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 196 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 197 #define CONFIG_SPL_I2C_SUPPORT
 198 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 199 #define CONFIG_SYS_TEXT_BASE            0x11001000
 200 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 201 #define CONFIG_SPL_PAD_TO               0x20000
 202 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 203 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 204 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
 205 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
 206 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
 207 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 208 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 209 #define CONFIG_SPL_MMC_BOOT
 210 #ifdef CONFIG_SPL_BUILD
 211 #define CONFIG_SPL_COMMON_INIT_DDR
 212 #endif
 213 #endif
 214
 215 #ifdef CONFIG_SPIFLASH
 216 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 217 #define CONFIG_SPL_ENV_SUPPORT
 218 #define CONFIG_SPL_SERIAL_SUPPORT
 219 #define CONFIG_SPL_SPI_SUPPORT
 220 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 221 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 222 #define CONFIG_SPL_FLUSH_IMAGE
 223 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 224 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 225 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 226 #define CONFIG_SPL_I2C_SUPPORT
 227 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 228 #define CONFIG_SYS_TEXT_BASE            0x11001000
 229 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 230 #define CONFIG_SPL_PAD_TO               0x20000
 231 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 232 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
 233 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
 234 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
 235 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
 236 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 237 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 238 #define CONFIG_SPL_SPI_BOOT
 239 #ifdef CONFIG_SPL_BUILD
 240 #define CONFIG_SPL_COMMON_INIT_DDR
 241 #endif
 242 #endif
 243
 244 #ifdef CONFIG_NAND
 245 #ifdef CONFIG_TPL_BUILD
 246 #define CONFIG_SPL_NAND_BOOT
 247 #define CONFIG_SPL_FLUSH_IMAGE
 248 #define CONFIG_SPL_ENV_SUPPORT
 249 #define CONFIG_SPL_NAND_INIT
 250 #define CONFIG_SPL_SERIAL_SUPPORT
 251 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 252 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 253 #define CONFIG_SPL_I2C_SUPPORT
 254 #define CONFIG_SPL_NAND_SUPPORT
 255 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 256 #define CONFIG_SPL_COMMON_INIT_DDR
 257 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 258 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 259 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 260 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
 261 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 262 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 263 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 264 #elif defined(CONFIG_SPL_BUILD)
 265 #define CONFIG_SPL_INIT_MINIMAL
 266 #define CONFIG_SPL_SERIAL_SUPPORT
 267 #define CONFIG_SPL_NAND_SUPPORT
 268 #define CONFIG_SPL_FLUSH_IMAGE
 269 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 270 #define CONFIG_SPL_TEXT_BASE            0xff800000
 271 #define CONFIG_SPL_MAX_SIZE             4096
 272 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 273 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 274 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 275 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 276 #endif /* not CONFIG_TPL_BUILD */
 277
 278 #define CONFIG_SPL_PAD_TO               0x20000
 279 #define CONFIG_TPL_PAD_TO               0x20000
 280 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 281 #define CONFIG_SYS_TEXT_BASE            0x11001000
 282 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 283 #endif
 284
 285 #ifndef CONFIG_SYS_TEXT_BASE
 286 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 287 #endif
 288
 289 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 290 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 291 #endif
 292
 293 #ifndef CONFIG_SYS_MONITOR_BASE
 294 #ifdef CONFIG_SPL_BUILD
 295 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 296 #else
 297 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 298 #endif
 299 #endif
 300
 301 /* High Level Configuration Options */
 302 #define CONFIG_BOOKE
 303 #define CONFIG_E500
 304
 305 #define CONFIG_MP
 306
 307 #define CONFIG_FSL_ELBC
 308 #define CONFIG_PCI
 309 #define CONFIG_PCIE1    /* PCIE controler 1 (slot 1) */
 310 #define CONFIG_PCIE2    /* PCIE controler 2 (slot 2) */
 311 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 312 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 313 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
 314 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 315
 316 #define CONFIG_FSL_LAW
 317 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
 318 #define CONFIG_ENV_OVERWRITE
 319
 320 #define CONFIG_CMD_SATA
 321 #define CONFIG_SATA_SIL
 322 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 323 #define CONFIG_LIBATA
 324 #define CONFIG_LBA48
 325
 326 #if defined(CONFIG_P2020RDB)
 327 #define CONFIG_SYS_CLK_FREQ     100000000
 328 #else
 329 #define CONFIG_SYS_CLK_FREQ     66666666
 330 #endif
 331 #define CONFIG_DDR_CLK_FREQ     66666666
 332
 333 #define CONFIG_HWCONFIG
 334 /*
 335  * These can be toggled for performance analysis, otherwise use default.
 336  */
 337 #define CONFIG_L2_CACHE
 338 #define CONFIG_BTB
 339
 340 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 341
 342 #define CONFIG_ENABLE_36BIT_PHYS
 343
 344 #ifdef CONFIG_PHYS_64BIT
 345 #define CONFIG_ADDR_MAP                 1
 346 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 347 #endif
 348
 349 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 350 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 351 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 352
 353 #define CONFIG_SYS_CCSRBAR              0xffe00000
 354 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 355
 356 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 357        SPL code*/
 358 #ifdef CONFIG_SPL_BUILD
 359 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 360 #endif
 361
 362 /* DDR Setup */
 363 #define CONFIG_SYS_FSL_DDR3
 364 #define CONFIG_SYS_DDR_RAW_TIMING
 365 #define CONFIG_DDR_SPD
 366 #define CONFIG_SYS_SPD_BUS_NUM 1
 367 #define SPD_EEPROM_ADDRESS 0x52
 368 #undef CONFIG_FSL_DDR_INTERACTIVE
 369
 370 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 371 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 372 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 373 #else
 374 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_1G
 375 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 376 #endif
 377 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 378 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 379 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 380
 381 #define CONFIG_NUM_DDR_CONTROLLERS      1
 382 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 383
 384 /* Default settings for DDR3 */
 385 #ifndef CONFIG_P2020RDB
 386 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 387 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 388 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 389 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 390 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 391 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 392
 393 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 394 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 395 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 396 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 397
 398 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 399 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 400 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 401 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 402 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 403 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 404 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 405 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 406 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 407
 408 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 409 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 410 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 411 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 412 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 413 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 414 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 415 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 416 #endif
 417
 418 #undef CONFIG_CLOCKS_IN_MHZ
 419
 420 /*
 421  * Memory map
 422  *
 423  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 424  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 425  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 426  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 512K cacheable
 427  *   (early boot only)
 428  * 0xff80_0000 0xff80_7fff      NAND flash      32K non-cacheable       CS1/0
 429  * 0xff98_0000 0xff98_ffff      PMC             64K non-cacheable       CS2
 430  * 0xffa0_0000 0xffaf_ffff      CPLD            1M non-cacheable        CS3
 431  * 0xffb0_0000 0xffbf_ffff      VSC7385 switch  1M non-cacheable        CS2
 432  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 433  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 434  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 435  */
 436
 437
 438 /*
 439  * Local Bus Definitions
 440  */
 441 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 442 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 443 #define CONFIG_SYS_FLASH_BASE           0xec000000
 444 #elif defined(CONFIG_P1020UTM)
 445 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 446 #define CONFIG_SYS_FLASH_BASE           0xee000000
 447 #else
 448 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* 16M */
 449 #define CONFIG_SYS_FLASH_BASE           0xef000000
 450 #endif
 451
 452
 453 #ifdef CONFIG_PHYS_64BIT
 454 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 455 #else
 456 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 457 #endif
 458
 459 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 460         | BR_PS_16 | BR_V)
 461
 462 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 463
 464 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 465 #define CONFIG_SYS_FLASH_QUIET_TEST
 466 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 467
 468 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 469
 470 #undef CONFIG_SYS_FLASH_CHECKSUM
 471 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 472 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 473
 474 #define CONFIG_FLASH_CFI_DRIVER
 475 #define CONFIG_SYS_FLASH_CFI
 476 #define CONFIG_SYS_FLASH_EMPTY_INFO
 477 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 478
 479 /* Nand Flash */
 480 #ifdef CONFIG_NAND_FSL_ELBC
 481 #define CONFIG_SYS_NAND_BASE            0xff800000
 482 #ifdef CONFIG_PHYS_64BIT
 483 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 484 #else
 485 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 486 #endif
 487
 488 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 489 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 490 #define CONFIG_CMD_NAND
 491 #if defined(CONFIG_P1020RDB_PD)
 492 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 493 #else
 494 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 495 #endif
 496
 497 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 498         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 499         | BR_PS_8       /* Port Size = 8 bit */ \
 500         | BR_MS_FCM     /* MSEL = FCM */ \
 501         | BR_V) /* valid */
 502 #if defined(CONFIG_P1020RDB_PD)
 503 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 504         | OR_FCM_PGS    /* Large Page*/ \
 505         | OR_FCM_CSCT \
 506         | OR_FCM_CST \
 507         | OR_FCM_CHT \
 508         | OR_FCM_SCY_1 \
 509         | OR_FCM_TRLX \
 510         | OR_FCM_EHTR)
 511 #else
 512 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB     /* small page */ \
 513         | OR_FCM_CSCT \
 514         | OR_FCM_CST \
 515         | OR_FCM_CHT \
 516         | OR_FCM_SCY_1 \
 517         | OR_FCM_TRLX \
 518         | OR_FCM_EHTR)
 519 #endif
 520 #endif /* CONFIG_NAND_FSL_ELBC */
 521
 522 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 523
 524 #define CONFIG_SYS_INIT_RAM_LOCK
 525 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 526 #ifdef CONFIG_PHYS_64BIT
 527 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 528 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 529 /* The assembler doesn't like typecast */
 530 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 531         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 532           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 533 #else
 534 /* Initial L1 address */
 535 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 536 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 537 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 538 #endif
 539 /* Size of used area in RAM */
 540 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 541
 542 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 543                                         GENERATED_GBL_DATA_SIZE)
 544 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 545
 546 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 547 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 548
 549 #define CONFIG_SYS_CPLD_BASE    0xffa00000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffa00000ull
 552 #else
 553 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 554 #endif
 555 /* CPLD config size: 1Mb */
 556 #define CONFIG_CPLD_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 557                                         BR_PS_8 | BR_V)
 558 #define CONFIG_CPLD_OR_PRELIM   (0xfff009f7)
 559
 560 #define CONFIG_SYS_PMC_BASE     0xff980000
 561 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 562 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 563                                         BR_PS_8 | BR_V)
 564 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 565                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 566                                  OR_GPCM_EAD)
 567
 568 #ifdef CONFIG_NAND
 569 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 570 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 571 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 572 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 573 #else
 574 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 575 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 576 #ifdef CONFIG_NAND_FSL_ELBC
 577 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 578 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 579 #endif
 580 #endif
 581 #define CONFIG_SYS_BR3_PRELIM   CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
 582 #define CONFIG_SYS_OR3_PRELIM   CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
 583
 584
 585 /* Vsc7385 switch */
 586 #ifdef CONFIG_VSC7385_ENET
 587 #define CONFIG_SYS_VSC7385_BASE         0xffb00000
 588
 589 #ifdef CONFIG_PHYS_64BIT
 590 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 591 #else
 592 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 593 #endif
 594
 595 #define CONFIG_SYS_VSC7385_BR_PRELIM    \
 596         (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
 597 #define CONFIG_SYS_VSC7385_OR_PRELIM    (OR_AM_128KB | OR_GPCM_CSNT | \
 598                         OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 599                         OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 600
 601 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_VSC7385_BR_PRELIM
 602 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_VSC7385_OR_PRELIM
 603
 604 /* The size of the VSC7385 firmware image */
 605 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 606 #endif
 607
 608 /*
 609  * Config the L2 Cache as L2 SRAM
 610 */
 611 #if defined(CONFIG_SPL_BUILD)
 612 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 613 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 614 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 615 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 616 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 617 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 618 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 619 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 620 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 621 #if defined(CONFIG_P2020RDB)
 622 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (364 << 10)
 623 #else
 624 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 625 #endif
 626 #elif defined(CONFIG_NAND)
 627 #ifdef CONFIG_TPL_BUILD
 628 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 629 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 630 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 631 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 632 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 633 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 634 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 635 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 636 #else
 637 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 638 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 639 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 640 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 641 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 642 #endif /* CONFIG_TPL_BUILD */
 643 #endif
 644 #endif
 645
 646 /* Serial Port - controlled on board with jumper J8
 647  * open - index 2
 648  * shorted - index 1
 649  */
 650 #define CONFIG_CONS_INDEX               1
 651 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 652 #define CONFIG_SYS_NS16550_SERIAL
 653 #define CONFIG_SYS_NS16550_REG_SIZE     1
 654 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 655 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 656 #define CONFIG_NS16550_MIN_FUNCTIONS
 657 #endif
 658
 659 #define CONFIG_SYS_BAUDRATE_TABLE       \
 660         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 661
 662 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 663 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 664
 665 /* Use the HUSH parser */
 666 #define CONFIG_SYS_HUSH_PARSER
 667
 668 /*
 669  * Pass open firmware flat tree
 670  */
 671 #define CONFIG_OF_BOARD_SETUP
 672 #define CONFIG_OF_STDOUT_VIA_ALIAS
 673
 674 /* new uImage format support */
 675 #define CONFIG_FIT
 676 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 677
 678 /* I2C */
 679 #define CONFIG_SYS_I2C
 680 #define CONFIG_SYS_I2C_FSL
 681 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 682 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 683 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 684 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 685 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 686 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 687 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 688 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 689 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 690
 691 /*
 692  * I2C2 EEPROM
 693  */
 694 #undef CONFIG_ID_EEPROM
 695
 696 #define CONFIG_RTC_PT7C4338
 697 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 698 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 699
 700 /* enable read and write access to EEPROM */
 701 #define CONFIG_CMD_EEPROM
 702 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 703 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 704 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 705
 706 /*
 707  * eSPI - Enhanced SPI
 708  */
 709 #define CONFIG_HARD_SPI
 710
 711 #if defined(CONFIG_SPI_FLASH)
 712 #define CONFIG_CMD_SF
 713 #define CONFIG_SF_DEFAULT_SPEED 10000000
 714 #define CONFIG_SF_DEFAULT_MODE  0
 715 #endif
 716
 717 #if defined(CONFIG_PCI)
 718 /*
 719  * General PCI
 720  * Memory space is mapped 1-1, but I/O space must start from 0.
 721  */
 722
 723 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 724 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT"
 725 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 726 #ifdef CONFIG_PHYS_64BIT
 727 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 728 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 729 #else
 730 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 731 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 732 #endif
 733 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 734 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 735 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 736 #ifdef CONFIG_PHYS_64BIT
 737 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 738 #else
 739 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 740 #endif
 741 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 742
 743 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 744 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 745 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 746 #ifdef CONFIG_PHYS_64BIT
 747 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 748 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 749 #else
 750 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 751 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 752 #endif
 753 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 754 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 755 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 756 #ifdef CONFIG_PHYS_64BIT
 757 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 758 #else
 759 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 760 #endif
 761 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 762
 763 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 764 #define CONFIG_CMD_PCI
 765
 766 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 767 #define CONFIG_DOS_PARTITION
 768 #endif /* CONFIG_PCI */
 769
 770 #if defined(CONFIG_TSEC_ENET)
 771 #define CONFIG_MII              /* MII PHY management */
 772 #define CONFIG_TSEC1
 773 #define CONFIG_TSEC1_NAME       "eTSEC1"
 774 #define CONFIG_TSEC2
 775 #define CONFIG_TSEC2_NAME       "eTSEC2"
 776 #define CONFIG_TSEC3
 777 #define CONFIG_TSEC3_NAME       "eTSEC3"
 778
 779 #define TSEC1_PHY_ADDR  2
 780 #define TSEC2_PHY_ADDR  0
 781 #define TSEC3_PHY_ADDR  1
 782
 783 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 784 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 785 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 786
 787 #define TSEC1_PHYIDX    0
 788 #define TSEC2_PHYIDX    0
 789 #define TSEC3_PHYIDX    0
 790
 791 #define CONFIG_ETHPRIME "eTSEC1"
 792
 793 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 794
 795 #define CONFIG_HAS_ETH0
 796 #define CONFIG_HAS_ETH1
 797 #define CONFIG_HAS_ETH2
 798 #endif /* CONFIG_TSEC_ENET */
 799
 800 #ifdef CONFIG_QE
 801 /* QE microcode/firmware address */
 802 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 803 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 804 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 805 #endif /* CONFIG_QE */
 806
 807 #ifdef CONFIG_P1025RDB
 808 /*
 809  * QE UEC ethernet configuration
 810  */
 811 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 812
 813 #undef CONFIG_UEC_ETH
 814 #define CONFIG_PHY_MODE_NEED_CHANGE
 815
 816 #define CONFIG_UEC_ETH1 /* ETH1 */
 817 #define CONFIG_HAS_ETH0
 818
 819 #ifdef CONFIG_UEC_ETH1
 820 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 821 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 822 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 823 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 824 #define CONFIG_SYS_UEC1_PHY_ADDR        0x0     /* 0x0 for MII */
 825 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 826 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 827 #endif /* CONFIG_UEC_ETH1 */
 828
 829 #define CONFIG_UEC_ETH5 /* ETH5 */
 830 #define CONFIG_HAS_ETH1
 831
 832 #ifdef CONFIG_UEC_ETH5
 833 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 834 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 835 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 836 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 837 #define CONFIG_SYS_UEC5_PHY_ADDR        0x3     /* 0x3 for RMII */
 838 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 839 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 840 #endif /* CONFIG_UEC_ETH5 */
 841 #endif /* CONFIG_P1025RDB */
 842
 843 /*
 844  * Environment
 845  */
 846 #ifdef CONFIG_SPIFLASH
 847 #define CONFIG_ENV_IS_IN_SPI_FLASH
 848 #define CONFIG_ENV_SPI_BUS      0
 849 #define CONFIG_ENV_SPI_CS       0
 850 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 851 #define CONFIG_ENV_SPI_MODE     0
 852 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 853 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 854 #define CONFIG_ENV_SECT_SIZE    0x10000
 855 #elif defined(CONFIG_SDCARD)
 856 #define CONFIG_ENV_IS_IN_MMC
 857 #define CONFIG_FSL_FIXED_MMC_LOCATION
 858 #define CONFIG_ENV_SIZE         0x2000
 859 #define CONFIG_SYS_MMC_ENV_DEV  0
 860 #elif defined(CONFIG_NAND)
 861 #ifdef CONFIG_TPL_BUILD
 862 #define CONFIG_ENV_SIZE         0x2000
 863 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 864 #else
 865 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 866 #endif
 867 #define CONFIG_ENV_IS_IN_NAND
 868 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 869 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 870 #elif defined(CONFIG_SYS_RAMBOOT)
 871 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 872 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 873 #define CONFIG_ENV_SIZE         0x2000
 874 #else
 875 #define CONFIG_ENV_IS_IN_FLASH
 876 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 877 #define CONFIG_ENV_SIZE         0x2000
 878 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 879 #endif
 880
 881 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 882 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 883
 884 /*
 885  * Command line configuration.
 886  */
 887 #define CONFIG_CMD_IRQ
 888 #define CONFIG_CMD_PING
 889 #define CONFIG_CMD_I2C
 890 #define CONFIG_CMD_MII
 891 #define CONFIG_CMD_DATE
 892 #define CONFIG_CMD_REGINFO
 893
 894 /*
 895  * USB
 896  */
 897 #define CONFIG_HAS_FSL_DR_USB
 898
 899 #if defined(CONFIG_HAS_FSL_DR_USB)
 900 #define CONFIG_USB_EHCI
 901
 902 #ifdef CONFIG_USB_EHCI
 903 #define CONFIG_CMD_USB
 904 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 905 #define CONFIG_USB_EHCI_FSL
 906 #define CONFIG_USB_STORAGE
 907 #endif
 908 #endif
 909
 910 #if defined(CONFIG_P1020RDB_PD)
 911 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 912 #endif
 913
 914 #define CONFIG_MMC
 915
 916 #ifdef CONFIG_MMC
 917 #define CONFIG_FSL_ESDHC
 918 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 919 #define CONFIG_CMD_MMC
 920 #define CONFIG_GENERIC_MMC
 921 #endif
 922
 923 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 924                  || defined(CONFIG_FSL_SATA)
 925 #define CONFIG_CMD_EXT2
 926 #define CONFIG_CMD_FAT
 927 #define CONFIG_DOS_PARTITION
 928 #endif
 929
 930 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 931
 932 /*
 933  * Miscellaneous configurable options
 934  */
 935 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 936 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 937 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 938 #if defined(CONFIG_CMD_KGDB)
 939 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 940 #else
 941 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 942 #endif
 943 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 944         /* Print Buffer Size */
 945 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 946 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 947
 948 /*
 949  * For booting Linux, the board info and command line data
 950  * have to be in the first 64 MB of memory, since this is
 951  * the maximum mapped by the Linux kernel during initialization.
 952  */
 953 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 954 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 955
 956 #if defined(CONFIG_CMD_KGDB)
 957 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 958 #endif
 959
 960 /*
 961  * Environment Configuration
 962  */
 963 #define CONFIG_HOSTNAME         unknown
 964 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 965 #define CONFIG_BOOTFILE         "uImage"
 966 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 967
 968 /* default location for tftp and bootm */
 969 #define CONFIG_LOADADDR 1000000
 970
 971 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 972 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 973
 974 #define CONFIG_BAUDRATE 115200
 975
 976 #ifdef __SW_BOOT_NOR
 977 #define __NOR_RST_CMD   \
 978 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
 979 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 980 #endif
 981 #ifdef __SW_BOOT_SPI
 982 #define __SPI_RST_CMD   \
 983 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
 984 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 985 #endif
 986 #ifdef __SW_BOOT_SD
 987 #define __SD_RST_CMD    \
 988 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
 989 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 990 #endif
 991 #ifdef __SW_BOOT_NAND
 992 #define __NAND_RST_CMD  \
 993 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
 994 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 995 #endif
 996 #ifdef __SW_BOOT_PCIE
 997 #define __PCIE_RST_CMD  \
 998 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
 999 i2c mw 18 3 __SW_BOOT_MASK 1; reset
1000 #endif
1001
1002 #define CONFIG_EXTRA_ENV_SETTINGS       \
1003 "netdev=eth0\0" \
1004 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
1005 "loadaddr=1000000\0"    \
1006 "bootfile=uImage\0"     \
1007 "tftpflash=tftpboot $loadaddr $uboot; " \
1008         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
1009         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
1010         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
1011         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
1012         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
1013 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
1014 "consoledev=ttyS0\0"    \
1015 "ramdiskaddr=2000000\0" \
1016 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
1017 "fdtaddr=c00000\0"      \
1018 "bdev=sda1\0" \
1019 "jffs2nor=mtdblock3\0"  \
1020 "norbootaddr=ef080000\0"        \
1021 "norfdtaddr=ef040000\0" \
1022 "jffs2nand=mtdblock9\0" \
1023 "nandbootaddr=100000\0" \
1024 "nandfdtaddr=80000\0"           \
1025 "ramdisk_size=120000\0" \
1026 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
1027 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
1028 __stringify(__NOR_RST_CMD)"\0" \
1029 __stringify(__SPI_RST_CMD)"\0" \
1030 __stringify(__SD_RST_CMD)"\0" \
1031 __stringify(__NAND_RST_CMD)"\0" \
1032 __stringify(__PCIE_RST_CMD)"\0"
1033
1034 #define CONFIG_NFSBOOTCOMMAND   \
1035 "setenv bootargs root=/dev/nfs rw "     \
1036 "nfsroot=$serverip:$rootpath "  \
1037 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
1038 "console=$consoledev,$baudrate $othbootargs;" \
1039 "tftp $loadaddr $bootfile;"     \
1040 "tftp $fdtaddr $fdtfile;"       \
1041 "bootm $loadaddr - $fdtaddr"
1042
1043 #define CONFIG_HDBOOT   \
1044 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
1045 "console=$consoledev,$baudrate $othbootargs;" \
1046 "usb start;"    \
1047 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
1048 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
1049 "bootm $loadaddr - $fdtaddr"
1050
1051 #define CONFIG_USB_FAT_BOOT     \
1052 "setenv bootargs root=/dev/ram rw "     \
1053 "console=$consoledev,$baudrate $othbootargs " \
1054 "ramdisk_size=$ramdisk_size;"   \
1055 "usb start;"    \
1056 "fatload usb 0:2 $loadaddr $bootfile;"  \
1057 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
1058 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
1059 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1060
1061 #define CONFIG_USB_EXT2_BOOT    \
1062 "setenv bootargs root=/dev/ram rw "     \
1063 "console=$consoledev,$baudrate $othbootargs " \
1064 "ramdisk_size=$ramdisk_size;"   \
1065 "usb start;"    \
1066 "ext2load usb 0:4 $loadaddr $bootfile;" \
1067 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1068 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1069 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1070
1071 #define CONFIG_NORBOOT  \
1072 "setenv bootargs root=/dev/$jffs2nor rw "       \
1073 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
1074 "bootm $norbootaddr - $norfdtaddr"
1075
1076 #define CONFIG_RAMBOOTCOMMAND   \
1077 "setenv bootargs root=/dev/ram rw "     \
1078 "console=$consoledev,$baudrate $othbootargs " \
1079 "ramdisk_size=$ramdisk_size;"   \
1080 "tftp $ramdiskaddr $ramdiskfile;"       \
1081 "tftp $loadaddr $bootfile;"     \
1082 "tftp $fdtaddr $fdtfile;"       \
1083 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1084
1085 #define CONFIG_BOOTCOMMAND      CONFIG_HDBOOT
1086
1087 #endif /* __CONFIG_H */