include/configs/p1_twr.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ P1 Tower boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #if defined(CONFIG_TWR_P1025)
  14 #define CONFIG_BOARDNAME "TWR-P1025"
  15 #define CONFIG_P1025
  16 #define CONFIG_PHY_ATHEROS
  17 #define CONFIG_QE
  18 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Conversion of LBC addr */
  19 #define CONFIG_SYS_LBC_LCRR     0x80000002      /* LB clock ratio reg */
  20 #endif
  21
  22 #ifdef CONFIG_SDCARD
  23 #define CONFIG_RAMBOOT_SDCARD
  24 #define CONFIG_SYS_RAMBOOT
  25 #define CONFIG_SYS_EXTRA_ENV_RELOC
  26 #define CONFIG_SYS_TEXT_BASE            0x11000000
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  28 #endif
  29
  30 #ifndef CONFIG_SYS_TEXT_BASE
  31 #define CONFIG_SYS_TEXT_BASE            0xeff40000
  32 #endif
  33
  34 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  36 #endif
  37
  38 #ifndef CONFIG_SYS_MONITOR_BASE
  39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  40 #endif
  41
  42 /* High Level Configuration Options */
  43 #define CONFIG_BOOKE
  44 #define CONFIG_E500
  45
  46 #define CONFIG_MP
  47
  48 #define CONFIG_FSL_ELBC
  49 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
  50 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
  51 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  52 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  53 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  54 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  55
  56 #define CONFIG_FSL_LAW
  57 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 #define CONFIG_CMD_SATA
  61 #define CONFIG_SATA_SIL3114
  62 #define CONFIG_SYS_SATA_MAX_DEVICE      2
  63 #define CONFIG_LIBATA
  64 #define CONFIG_LBA48
  65
  66 #ifndef __ASSEMBLY__
  67 extern unsigned long get_board_sys_clk(unsigned long dummy);
  68 #endif
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for TWR-P1025 */
  70
  71 #define CONFIG_DDR_CLK_FREQ     66666666
  72
  73 #define CONFIG_HWCONFIG
  74 /*
  75  * These can be toggled for performance analysis, otherwise use default.
  76  */
  77 #define CONFIG_L2_CACHE
  78 #define CONFIG_BTB
  79
  80 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
  81
  82 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  83 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
  84 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  85
  86 #define CONFIG_SYS_CCSRBAR              0xffe00000
  87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  88
  89 /* DDR Setup */
  90 #define CONFIG_SYS_FSL_DDR3
  91
  92 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
  93 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  94
  95 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_NUM_DDR_CONTROLLERS      1
 100 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 101
 102 /* Default settings for DDR3 */
 103 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
 104 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 105 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 106 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 107 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 108 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 109
 110 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 111 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 112 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 113 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 114
 115 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 116 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655a608
 117 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 118 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 119 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 120 #define CONFIG_SYS_DDR_CONTROL          0xc70c0000      /* Type = DDR3  */
 121 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 122 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 123 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 124
 125 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 126 #define CONFIG_SYS_DDR_TIMING_0         0x00220004
 127 #define CONFIG_SYS_DDR_TIMING_1         0x5c5b6544
 128 #define CONFIG_SYS_DDR_TIMING_2         0x0fa880de
 129 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 130 #define CONFIG_SYS_DDR_MODE_1           0x80461320
 131 #define CONFIG_SYS_DDR_MODE_2           0x00008000
 132 #define CONFIG_SYS_DDR_INTERVAL         0x09480000
 133
 134 /*
 135  * Memory map
 136  *
 137  * 0x0000_0000 0x1fff_ffff      DDR             Up to 512MB cacheable
 138  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 139  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 140  *
 141  * Localbus
 142  * 0xe000_0000 0xe002_0000      SSD1289         128K non-cacheable
 143  * 0xec00_0000 0xefff_ffff      FLASH           Up to 64M non-cacheable
 144  *
 145  * 0xff90_0000 0xff97_ffff      L2 SRAM         Up to 512K cacheable
 146  * 0xffd0_0000 0xffd0_3fff      init ram        16K Cacheable
 147  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 148  */
 149
 150 /*
 151  * Local Bus Definitions
 152  */
 153 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 154 #define CONFIG_SYS_FLASH_BASE           0xec000000
 155
 156 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 157
 158 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
 159         | BR_PS_16 | BR_V)
 160
 161 #define CONFIG_FLASH_OR_PRELIM  0xfc0000b1
 162
 163 #define CONFIG_SYS_SSD_BASE     0xe0000000
 164 #define CONFIG_SYS_SSD_BASE_PHYS        CONFIG_SYS_SSD_BASE
 165 #define CONFIG_SSD_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
 166                                         BR_PS_16 | BR_V)
 167 #define CONFIG_SSD_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 168                                  OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
 169                                  OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 170
 171 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
 172 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
 173
 174 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 175 #define CONFIG_SYS_FLASH_QUIET_TEST
 176 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 177
 178 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 179
 180 #undef CONFIG_SYS_FLASH_CHECKSUM
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 183
 184 #define CONFIG_FLASH_CFI_DRIVER
 185 #define CONFIG_SYS_FLASH_CFI
 186 #define CONFIG_SYS_FLASH_EMPTY_INFO
 187 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 188
 189 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 190
 191 #define CONFIG_SYS_INIT_RAM_LOCK
 192 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 193 /* Initial L1 address */
 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 197 /* Size of used area in RAM */
 198 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 199
 200 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 201                                         GENERATED_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 203
 204 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 205 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 206
 207 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 208 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 209
 210 /* Serial Port
 211  * open - index 2
 212  * shorted - index 1
 213  */
 214 #define CONFIG_CONS_INDEX               1
 215 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 219
 220 #define CONFIG_SYS_BAUDRATE_TABLE       \
 221         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 222
 223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 225
 226 /* I2C */
 227 #define CONFIG_SYS_I2C
 228 #define CONFIG_SYS_I2C_FSL                      /* Use FSL common I2C driver */
 229 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C spd and slave address */
 230 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 231 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 233
 234 /*
 235  * I2C2 EEPROM
 236  */
 237 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C spd and slave address */
 238 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 239 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 240
 241 #define CONFIG_SYS_I2C_PCA9555_ADDR     0x23
 242
 243 /* enable read and write access to EEPROM */
 244 #define CONFIG_CMD_EEPROM
 245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 248
 249 /*
 250  * eSPI - Enhanced SPI
 251  */
 252 #define CONFIG_HARD_SPI
 253
 254 #if defined(CONFIG_PCI)
 255 /*
 256  * General PCI
 257  * Memory space is mapped 1-1, but I/O space must start from 0.
 258  */
 259
 260 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 261 #define CONFIG_SYS_PCIE2_NAME           "TWR-ELEV PCIe SLOT"
 262 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 263 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 264 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 265 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 266 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 267 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 268 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 269 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 270
 271 /* controller 1, tgtid 1, Base address a000 */
 272 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 273 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 274 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 275 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 276 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 277 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 278 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 279 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 280 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 281
 282 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 283 #define CONFIG_CMD_PCI
 284
 285 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 286 #define CONFIG_DOS_PARTITION
 287 #endif /* CONFIG_PCI */
 288
 289 #if defined(CONFIG_TSEC_ENET)
 290
 291 #define CONFIG_MII              /* MII PHY management */
 292 #define CONFIG_TSEC1
 293 #define CONFIG_TSEC1_NAME       "eTSEC1"
 294 #undef CONFIG_TSEC2
 295 #undef CONFIG_TSEC2_NAME
 296 #define CONFIG_TSEC3
 297 #define CONFIG_TSEC3_NAME       "eTSEC3"
 298
 299 #define TSEC1_PHY_ADDR  2
 300 #define TSEC2_PHY_ADDR  0
 301 #define TSEC3_PHY_ADDR  1
 302
 303 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 304 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 305 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 306
 307 #define TSEC1_PHYIDX    0
 308 #define TSEC2_PHYIDX    0
 309 #define TSEC3_PHYIDX    0
 310
 311 #define CONFIG_ETHPRIME "eTSEC1"
 312
 313 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 314
 315 #define CONFIG_HAS_ETH0
 316 #define CONFIG_HAS_ETH1
 317 #undef CONFIG_HAS_ETH2
 318 #endif /* CONFIG_TSEC_ENET */
 319
 320 #ifdef CONFIG_QE
 321 /* QE microcode/firmware address */
 322 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 323 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 324 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 325 #endif /* CONFIG_QE */
 326
 327 #ifdef CONFIG_TWR_P1025
 328 /*
 329  * QE UEC ethernet configuration
 330  */
 331 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 332
 333 #undef CONFIG_UEC_ETH
 334 #define CONFIG_PHY_MODE_NEED_CHANGE
 335
 336 #define CONFIG_UEC_ETH1 /* ETH1 */
 337 #define CONFIG_HAS_ETH0
 338
 339 #ifdef CONFIG_UEC_ETH1
 340 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 341 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 342 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 343 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 344 #define CONFIG_SYS_UEC1_PHY_ADDR        0x18    /* 0x18 for MII */
 345 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
 346 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 347 #endif /* CONFIG_UEC_ETH1 */
 348
 349 #define CONFIG_UEC_ETH5 /* ETH5 */
 350 #define CONFIG_HAS_ETH1
 351
 352 #ifdef CONFIG_UEC_ETH5
 353 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 354 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 355 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 356 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 357 #define CONFIG_SYS_UEC5_PHY_ADDR        0x19    /* 0x19 for RMII */
 358 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 359 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 360 #endif /* CONFIG_UEC_ETH5 */
 361 #endif /* CONFIG_TWR-P1025 */
 362
 363 /*
 364  * Dynamic MTD Partition support with mtdparts
 365  */
 366 #define CONFIG_MTD_DEVICE
 367 #define CONFIG_MTD_PARTITIONS
 368 #define CONFIG_CMD_MTDPARTS
 369 #define CONFIG_FLASH_CFI_MTD
 370 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
 371 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
 372                         "256k(dtb),5632k(kernel),57856k(fs)," \
 373                         "256k(qe-ucode-firmware),1280k(u-boot)"
 374
 375 /*
 376  * Environment
 377  */
 378 #ifdef CONFIG_SYS_RAMBOOT
 379 #ifdef CONFIG_RAMBOOT_SDCARD
 380 #define CONFIG_ENV_IS_IN_MMC
 381 #define CONFIG_ENV_SIZE         0x2000
 382 #define CONFIG_SYS_MMC_ENV_DEV  0
 383 #else
 384 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 385 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 386 #define CONFIG_ENV_SIZE         0x2000
 387 #endif
 388 #else
 389 #define CONFIG_ENV_IS_IN_FLASH
 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 391 #define CONFIG_ENV_SIZE         0x2000
 392 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 393 #endif
 394
 395 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 397
 398 /*
 399  * Command line configuration.
 400  */
 401 #define CONFIG_CMD_IRQ
 402 #define CONFIG_CMD_REGINFO
 403
 404 /*
 405  * USB
 406  */
 407 #define CONFIG_HAS_FSL_DR_USB
 408
 409 #if defined(CONFIG_HAS_FSL_DR_USB)
 410 #define CONFIG_USB_EHCI
 411
 412 #ifdef CONFIG_USB_EHCI
 413 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 414 #define CONFIG_USB_EHCI_FSL
 415 #endif
 416 #endif
 417
 418 #define CONFIG_MMC
 419
 420 #ifdef CONFIG_MMC
 421 #define CONFIG_FSL_ESDHC
 422 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 423 #define CONFIG_GENERIC_MMC
 424 #endif
 425
 426 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 427                  || defined(CONFIG_FSL_SATA)
 428 #define CONFIG_DOS_PARTITION
 429 #endif
 430
 431 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 432
 433 /*
 434  * Miscellaneous configurable options
 435  */
 436 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 437 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 438 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 439 #if defined(CONFIG_CMD_KGDB)
 440 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 441 #else
 442 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 443 #endif
 444 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 445         /* Print Buffer Size */
 446 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 447 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 448
 449 /*
 450  * For booting Linux, the board info and command line data
 451  * have to be in the first 64 MB of memory, since this is
 452  * the maximum mapped by the Linux kernel during initialization.
 453  */
 454 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 455 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 456
 457 /*
 458  * Environment Configuration
 459  */
 460 #define CONFIG_HOSTNAME         unknown
 461 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 462 #define CONFIG_BOOTFILE         "uImage"
 463 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 464
 465 /* default location for tftp and bootm */
 466 #define CONFIG_LOADADDR 1000000
 467
 468 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 469
 470 #define CONFIG_BAUDRATE 115200
 471
 472 #define CONFIG_EXTRA_ENV_SETTINGS       \
 473 "netdev=eth0\0" \
 474 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 475 "loadaddr=1000000\0"    \
 476 "bootfile=uImage\0"     \
 477 "dtbfile=twr-p1025twr.dtb\0"    \
 478 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 479 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"   \
 480 "tftpflash=tftpboot $loadaddr $uboot; " \
 481         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 482         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 483         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 484         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 485         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 486 "kernelflash=tftpboot $loadaddr $bootfile; "    \
 487         "protect off 0xefa80000 +$filesize; "   \
 488         "erase 0xefa80000 +$filesize; " \
 489         "cp.b $loadaddr 0xefa80000 $filesize; " \
 490         "protect on 0xefa80000 +$filesize; "    \
 491         "cmp.b $loadaddr 0xefa80000 $filesize\0"        \
 492 "dtbflash=tftpboot $loadaddr $dtbfile; "        \
 493         "protect off 0xefe80000 +$filesize; "   \
 494         "erase 0xefe80000 +$filesize; " \
 495         "cp.b $loadaddr 0xefe80000 $filesize; " \
 496         "protect on 0xefe80000 +$filesize; "    \
 497         "cmp.b $loadaddr 0xefe80000 $filesize\0"        \
 498 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; "        \
 499         "protect off 0xeeb80000 +$filesize; "   \
 500         "erase 0xeeb80000 +$filesize; " \
 501         "cp.b $loadaddr 0xeeb80000 $filesize; " \
 502         "protect on 0xeeb80000 +$filesize; "    \
 503         "cmp.b $loadaddr 0xeeb80000 $filesize\0"        \
 504 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "  \
 505         "protect off 0xefec0000 +$filesize; "   \
 506         "erase 0xefec0000 +$filesize; " \
 507         "cp.b $loadaddr 0xefec0000 $filesize; " \
 508         "protect on 0xefec0000 +$filesize; "    \
 509         "cmp.b $loadaddr 0xefec0000 $filesize\0"        \
 510 "consoledev=ttyS0\0"    \
 511 "ramdiskaddr=2000000\0" \
 512 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 513 "fdtaddr=1e00000\0"     \
 514 "bdev=sda1\0"   \
 515 "norbootaddr=ef080000\0"        \
 516 "norfdtaddr=ef040000\0" \
 517 "ramdisk_size=120000\0" \
 518 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
 519 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
 520
 521 #define CONFIG_NFSBOOTCOMMAND   \
 522 "setenv bootargs root=/dev/nfs rw "     \
 523 "nfsroot=$serverip:$rootpath "  \
 524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 525 "console=$consoledev,$baudrate $othbootargs;" \
 526 "tftp $loadaddr $bootfile&&"    \
 527 "tftp $fdtaddr $fdtfile&&"      \
 528 "bootm $loadaddr - $fdtaddr"
 529
 530 #define CONFIG_HDBOOT   \
 531 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 532 "console=$consoledev,$baudrate $othbootargs;" \
 533 "usb start;"    \
 534 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 535 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 536 "bootm $loadaddr - $fdtaddr"
 537
 538 #define CONFIG_USB_FAT_BOOT     \
 539 "setenv bootargs root=/dev/ram rw "     \
 540 "console=$consoledev,$baudrate $othbootargs " \
 541 "ramdisk_size=$ramdisk_size;"   \
 542 "usb start;"    \
 543 "fatload usb 0:2 $loadaddr $bootfile;"  \
 544 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 545 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 546 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 547
 548 #define CONFIG_USB_EXT2_BOOT    \
 549 "setenv bootargs root=/dev/ram rw "     \
 550 "console=$consoledev,$baudrate $othbootargs " \
 551 "ramdisk_size=$ramdisk_size;"   \
 552 "usb start;"    \
 553 "ext2load usb 0:4 $loadaddr $bootfile;" \
 554 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
 555 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
 556 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 557
 558 #define CONFIG_NORBOOT  \
 559 "setenv bootargs root=/dev/mtdblock3 rw "       \
 560 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 561 "bootm $norbootaddr - $norfdtaddr"
 562
 563 #define CONFIG_RAMBOOTCOMMAND_TFTP      \
 564 "setenv bootargs root=/dev/ram rw "     \
 565 "console=$consoledev,$baudrate $othbootargs " \
 566 "ramdisk_size=$ramdisk_size;"   \
 567 "tftp $ramdiskaddr $ramdiskfile;"       \
 568 "tftp $loadaddr $bootfile;"     \
 569 "tftp $fdtaddr $fdtfile;"       \
 570 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 571
 572 #define CONFIG_RAMBOOTCOMMAND   \
 573 "setenv bootargs root=/dev/ram rw "     \
 574 "console=$consoledev,$baudrate $othbootargs " \
 575 "ramdisk_size=$ramdisk_size;"   \
 576 "bootm 0xefa80000 0xeeb80000 0xefe80000"
 577
 578 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 579
 580 #endif /* __CONFIG_H */