include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /*
  13  * sequoia.h - configuration for Sequoia & Rainier boards
  14  */
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  22 #ifndef CONFIG_RAINIER
  23 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  24 #define CONFIG_HOSTNAME         sequoia
  25 #else
  26 #define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  27 #define CONFIG_HOSTNAME         rainier
  28 #endif
  29 #define CONFIG_440              1       /* ... PPC440 family            */
  30
  31 #ifndef CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  33 #endif
  34
  35 /*
  36  * Include common defines/options for all AMCC eval boards
  37  */
  38 #include "amcc-common.h"
  39
  40 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  41 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  42                                 33333333 : 33000000)
  43
  44 /*
  45  * Define this if you want support for video console with radeon 9200 pci card
  46  * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  47  */
  48
  49 #ifdef CONFIG_VIDEO
  50 /*
  51  * 44x dcache supported is working now on sequoia, but we don't enable
  52  * it yet since it needs further testing
  53  */
  54 #define CONFIG_4xx_DCACHE               /* enable dcache                */
  55 #endif
  56
  57 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  58 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  59
  60 /*
  61  * Base addresses -- Note these are effective addresses where the actual
  62  * resources get mapped (not physical addresses).
  63  */
  64 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  65 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  66 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  67 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  68 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  69 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  70 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  71 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  72 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  73 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  74 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  75
  76 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  77 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  78 #define CONFIG_SYS_USB_HOST             0xe0000400
  79 #define CONFIG_SYS_BCSR_BASE            0xc0000000
  80
  81 /*
  82  * Initial RAM & stack pointer
  83  */
  84 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  85 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  86 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  87 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  88 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  89
  90 /*
  91  * Serial Port
  92  */
  93 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  94 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
  95
  96 /*
  97  * Environment
  98  */
  99 #if defined(CONFIG_SYS_RAMBOOT)
 100 #define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 101 #define CONFIG_ENV_SIZE         (8 << 10)
 102 #else
 103 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 104 #endif
 105
 106 #if defined(CONFIG_CMD_FLASH)
 107 /*
 108  * FLASH related
 109  */
 110 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 111 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 112
 113 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 114
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 117
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 120
 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 122 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 123
 124 #define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 125 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 126 #endif /* CONFIG_CMD_FLASH */
 127
 128 #ifdef CONFIG_ENV_IS_IN_FLASH
 129 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 130 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 131 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 132
 133 /* Address and size of Redundant Environment Sector     */
 134 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 135 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 136 #endif
 137
 138 /*
 139  * DDR SDRAM
 140  */
 141 #define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 142 #if !defined(CONFIG_SYS_RAMBOOT)
 143 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 144 #endif
 145 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 146                                         /* 440EPx errata CHIP 11        */
 147
 148 /*
 149  * I2C
 150  */
 151 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 152
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 157
 158 /* I2C bootstrap EEPROM */
 159 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 160 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 161 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 162
 163 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 164 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 165 #define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 166 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 167 #define CONFIG_SYS_DTT_MAX_TEMP 70
 168 #define CONFIG_SYS_DTT_LOW_TEMP -30
 169 #define CONFIG_SYS_DTT_HYSTERESIS       3
 170
 171 /*
 172  * Default environment variables
 173  */
 174 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 175         CONFIG_AMCC_DEF_ENV                                             \
 176         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 177         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 178         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 179         "kernel_addr=FC000000\0"                                        \
 180         "ramdisk_addr=FC180000\0"                                       \
 181         ""
 182
 183 #define CONFIG_M88E1111_PHY     1
 184 #define CONFIG_IBM_EMAC4_V4     1
 185 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 186
 187 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 188 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 189
 190 #define CONFIG_HAS_ETH0
 191 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 192 #define CONFIG_PHY1_ADDR        1
 193
 194 /* USB */
 195 #ifdef CONFIG_440EPX
 196
 197 #undef CONFIG_USB_EHCI  /* OHCI by default */
 198
 199 #ifdef CONFIG_USB_EHCI
 200 #define CONFIG_USB_EHCI_PPC4XX
 201 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 202 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 203 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 204 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 205 #else /* CONFIG_USB_EHCI */
 206 #define CONFIG_USB_OHCI_NEW
 207 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 208
 209 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 210 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 211 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 212 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 213 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 214 #endif
 215
 216 /* Comment this out to enable USB 1.1 device */
 217 #define USB_2_0_DEVICE
 218
 219 #endif /* CONFIG_440EPX */
 220
 221 /* Partitions */
 222 #define CONFIG_MAC_PARTITION
 223 #define CONFIG_DOS_PARTITION
 224 #define CONFIG_ISO_PARTITION
 225
 226 /*
 227  * Commands additional to the ones defined in amcc-common.h
 228  */
 229 #define CONFIG_CMD_CHIP_CONFIG
 230 #define CONFIG_CMD_DTT
 231 #define CONFIG_CMD_NAND
 232 #define CONFIG_CMD_PCI
 233 #define CONFIG_CMD_SDRAM
 234
 235 #ifdef CONFIG_440EPX
 236 #endif
 237
 238 #ifndef CONFIG_RAINIER
 239 #define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 240 #else
 241 #define CONFIG_SYS_POST_FPU_ON          0
 242 #endif
 243
 244 /*
 245  * Don't run the memory POST on the NAND-booting version. It will
 246  * overwrite part of the U-Boot image which is already loaded from NAND
 247  * to SDRAM.
 248  */
 249 #if defined(CONFIG_SYS_RAMBOOT)
 250 #define CONFIG_SYS_POST_MEMORY_ON       0
 251 #else
 252 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 253 #endif
 254
 255 /* POST support */
 256 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 257                                  CONFIG_SYS_POST_CPU       | \
 258                                  CONFIG_SYS_POST_ETHER     | \
 259                                  CONFIG_SYS_POST_FPU_ON    | \
 260                                  CONFIG_SYS_POST_I2C       | \
 261                                  CONFIG_SYS_POST_MEMORY_ON | \
 262                                  CONFIG_SYS_POST_SPR       | \
 263                                  CONFIG_SYS_POST_UART)
 264
 265 #define CONFIG_LOGBUFFER
 266 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 267
 268 #define CONFIG_SUPPORT_VFAT
 269
 270 /*
 271  * PCI stuff
 272  */
 273 /* General PCI */
 274 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 275 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 276 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 277 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 278 #define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 279                                                 /*   CONFIG_SYS_PCI_MEMBASE     */
 280 /* Board-specific PCI */
 281 #define CONFIG_SYS_PCI_TARGET_INIT
 282 #define CONFIG_SYS_PCI_MASTER_INIT
 283 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 284
 285 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 286 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 287
 288 /*
 289  * External Bus Controller (EBC) Setup
 290  */
 291
 292 /*
 293  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 294  */
 295 #if !defined(CONFIG_SYS_RAMBOOT)
 296 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 297 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 298 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 299 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 300
 301 /* Memory Bank 3 (NAND-FLASH) initialization                            */
 302 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 303 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 304 #else
 305 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 306 /* Memory Bank 3 (NOR-FLASH) initialization                             */
 307 #define CONFIG_SYS_EBC_PB3AP            0x03017200
 308 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 309
 310 /* Memory Bank 0 (NAND-FLASH) initialization                            */
 311 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 312 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 313 #endif
 314
 315 /* Memory Bank 2 (CPLD) initialization                                  */
 316 #define CONFIG_SYS_EBC_PB2AP            0x24814580
 317 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 318
 319 #define CONFIG_SYS_BCSR5_PCI66EN        0x80
 320
 321 /*
 322  * NAND FLASH
 323  */
 324 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 325 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 326 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 327
 328 /*
 329  * PPC440 GPIO Configuration
 330  */
 331 /* test-only: take GPIO init from pcs440ep ???? in config file */
 332 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 333 {                                                                                       \
 334 /* GPIO Core 0 */                                                                       \
 335 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 336 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 337 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 338 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 339 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 340 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 341 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 342 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 343 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 344 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 345 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 346 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 347 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 348 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 349 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 350 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 351 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 352 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 353 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 354 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 355 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 356 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 357 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 358 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 359 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 360 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 361 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 362 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 363 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 364 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 365 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 366 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 367 },                                                                                      \
 368 {                                                                                       \
 369 /* GPIO Core 1 */                                                                       \
 370 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 371 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 372 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 373 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 374 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 375 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 376 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 377 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 378 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 379 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 380 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 381 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 382 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 383 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 384 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 385 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 386 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 387 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 388 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 389 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 390 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 391 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 392 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 393 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 394 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 395 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 396 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 397 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 398 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 399 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 400 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 401 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 402 }                                                                                       \
 403 }
 404
 405 #ifdef CONFIG_VIDEO
 406 #define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 407 #define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 408 #define VIDEO_IO_OFFSET                 0xe8000000
 409 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 410 #define CONFIG_VIDEO_LOGO
 411 #define CONFIG_SPLASH_SCREEN
 412 #define CONFIG_CMD_BMP
 413 #endif
 414
 415 #endif /* __CONFIG_H */