include/configs/sh7763rdp.h

   1 /*
   2  * Configuation settings for the Renesas SH7763RDP board
   3  *
   4  * Copyright (C) 2008 Renesas Solutions Corp.
   5  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __SH7763RDP_H
  11 #define __SH7763RDP_H
  12
  13 #define CONFIG_CPU_SH7763       1
  14 #define CONFIG_SH7763RDP        1
  15 #define __LITTLE_ENDIAN         1
  16
  17 /*
  18  * Command line configuration.
  19  */
  20 #define CONFIG_CMD_SDRAM
  21 #define CONFIG_CMD_JFFS2
  22
  23 #define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
  24 #define CONFIG_ENV_OVERWRITE    1
  25
  26 #undef  CONFIG_SHOW_BOOT_PROGRESS
  27
  28 /* SCIF */
  29 #define CONFIG_SCIF_CONSOLE        1
  30 #define CONFIG_BAUDRATE         115200
  31 #define CONFIG_CONS_SCIF2               1
  32
  33 #define CONFIG_SYS_TEXT_BASE    0x8FFC0000
  34 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  35 #define CONFIG_SYS_CBSIZE               256     /* Buffer size for input from the Console */
  36 #define CONFIG_SYS_PBSIZE               256     /* Buffer size for Console output */
  37 #define CONFIG_SYS_MAXARGS              16      /* max args accepted for monitor commands */
  38 #define CONFIG_SYS_BARGSIZE     512     /* Buffer size for Boot Arguments
  39                                                                 passed to kernel */
  40 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }      /* List of legal baudrate
  41                                                                                                 settings for this board */
  42
  43 /* SDRAM */
  44 #define CONFIG_SYS_SDRAM_BASE           (0x8C000000)
  45 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
  46 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE)
  47 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  48
  49 /* Flash(NOR) */
  50 #define CONFIG_SYS_FLASH_BASE           (0xA0000000)
  51 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
  52 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
  53 #define CONFIG_SYS_MAX_FLASH_SECT  (520)
  54
  55 /* U-Boot setting */
  56 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
  57 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
  58 #define CONFIG_SYS_MONITOR_LEN          (128 * 1024)
  59 /* Size of DRAM reserved for malloc() use */
  60 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
  61 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  62
  63 #define CONFIG_SYS_FLASH_CFI
  64 #define CONFIG_FLASH_CFI_DRIVER
  65 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  66 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
  67 /* Timeout for Flash erase operations (in ms) */
  68 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
  69 /* Timeout for Flash write operations (in ms) */
  70 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
  71 /* Timeout for Flash set sector lock bit operations (in ms) */
  72 #define CONFIG_SYS_FLASH_LOCK_TOUT              (3 * 1000)
  73 /* Timeout for Flash clear lock bit operations (in ms) */
  74 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
  75 /* Use hardware flash sectors protection instead of U-Boot software protection */
  76 #undef  CONFIG_SYS_FLASH_PROTECTION
  77 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
  78 #define CONFIG_ENV_IS_IN_FLASH
  79 #define CONFIG_ENV_SECT_SIZE    (128 * 1024)
  80 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
  81 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
  82 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
  83 #define CONFIG_ENV_OFFSET               (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
  85 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
  86
  87 /* Clock */
  88 #define CONFIG_SYS_CLK_FREQ     66666666
  89 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  90 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  91 #define CONFIG_SYS_TMU_CLK_DIV          (4)     /* 4 (default), 16, 64, 256 or 1024 */
  92
  93 /* Ether */
  94 #define CONFIG_SH_ETHER 1
  95 #define CONFIG_SH_ETHER_USE_PORT (1)
  96 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
  97 #define CONFIG_PHYLIB
  98 #define CONFIG_BITBANGMII
  99 #define CONFIG_BITBANGMII_MULTI
 100 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 101
 102 #endif /* __SH7763RDP_H */