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1 /*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * Copyright (C) 2009 TechNexion Ltd.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12
13 /*
14 * High Level Configuration Options
15 */
16 #define CONFIG_OMAP /* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23
24 #define CONFIG_SYS_TEXT_BASE 0x80008000
25
26 #define CONFIG_SYS_CACHELINE_SIZE 64
27
28 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
29
30 #include <asm/arch/cpu.h> /* get chip and board defs */
31 #include <asm/arch/omap.h>
32
33 /*
34 * Display CPU and Board information
35 */
36 #define CONFIG_DISPLAY_CPUINFO
37 #define CONFIG_DISPLAY_BOARDINFO
38
39 /* Clock Defines */
40 #define V_OSCK 26000000 /* Clock output from T2 */
41 #define V_SCLK (V_OSCK >> 1)
42
43 #define CONFIG_MISC_INIT_R
44
45 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS
47 #define CONFIG_INITRD_TAG
48 #define CONFIG_REVISION_TAG
49
50 /*
51 * Size of malloc() pool
52 */
53 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
55 2 * 1024 * 1024)
56 /*
57 * DDR related
58 */
59 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
60 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
61
62 /*
63 * Hardware drivers
64 */
65
66 /*
67 * NS16550 Configuration
68 */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
71 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
72
73 /*
74 * select serial console configuration
75 */
76 #define CONFIG_CONS_INDEX 1
77 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
78 #define CONFIG_SERIAL1 /* UART1 */
79
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
84 115200}
85 #define CONFIG_MMC
86 #define CONFIG_OMAP_HSMMC
87 #define CONFIG_GENERIC_MMC
88 #define CONFIG_DOS_PARTITION
89
90 /* EHCI */
91 #define CONFIG_OMAP3_GPIO_5
92 #define CONFIG_USB_EHCI
93 #define CONFIG_USB_EHCI_OMAP
94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96 #define CONFIG_USB_STORAGE
97
98 /* commands to include */
99 #define CONFIG_CMD_CACHE
100 #define CONFIG_CMD_DHCP
101 #define CONFIG_CMD_EXT2 /* EXT2 Support */
102 #define CONFIG_CMD_FAT /* FAT support */
103 #define CONFIG_CMD_I2C /* I2C serial bus support */
104 #define CONFIG_CMD_MII
105 #define CONFIG_CMD_MMC /* MMC support */
106 #define CONFIG_CMD_NAND /* NAND support */
107 #define CONFIG_CMD_PING
108 #define CONFIG_CMD_USB
109 #define CONFIG_CMD_EEPROM
110
111 #define CONFIG_SYS_NO_FLASH
112 #define CONFIG_SYS_I2C
113 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000
114 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
115 #define CONFIG_SYS_I2C_OMAP34XX
116 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
118 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
119
120 /*
121 * Board NAND Info.
122 */
123 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
124 /* to access */
125 /* nand at CS0 */
126
127 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
128 /* NAND devices */
129
130 #define CONFIG_AUTO_COMPLETE
131
132 /*
133 * Miscellaneous configurable options
134 */
135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
136 #define CONFIG_CMDLINE_EDITING
137 #define CONFIG_AUTO_COMPLETE
138 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
139
140 /* Print Buffer Size */
141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
142 sizeof(CONFIG_SYS_PROMPT) + 16)
143 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
144 /* args */
145 /* Boot Argument Buffer Size */
146 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
147 /* memtest works on */
148 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
149 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
150 0x01F00000) /* 31MB */
151
152 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
153 /* address */
154
155 /*
156 * AM3517 has 12 GP timers, they can be driven by the system clock
157 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
158 * This rate is divided by a local divisor.
159 */
160 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
161 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
162
163 /*
164 * Physical Memory Map
165 */
166 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
167 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
168 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
169
170 /*
171 * FLASH and environment organization
172 */
173
174 /* **** PISMO SUPPORT *** */
175 #define CONFIG_NAND
176 #define CONFIG_NAND_OMAP_GPMC
177 #define CONFIG_ENV_IS_IN_NAND
178 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
179
180 /* Redundant Environment */
181 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
182 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
183 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
184 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
185 2 * CONFIG_SYS_ENV_SECT_SIZE)
186 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
187
188 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
189 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
190 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
191 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
192 CONFIG_SYS_INIT_RAM_SIZE - \
193 GENERATED_GBL_DATA_SIZE)
194
195 /*
196 * ethernet support, EMAC
197 *
198 */
199 #define CONFIG_DRIVER_TI_EMAC
200 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
201 #define CONFIG_MII
202 #define CONFIG_EMAC_MDIO_PHY_NUM 0
203 #define CONFIG_BOOTP_DNS
204 #define CONFIG_BOOTP_DNS2
205 #define CONFIG_BOOTP_SEND_HOSTNAME
206 #define CONFIG_NET_RETRY_COUNT 10
207
208 /* Defines for SPL */
209 #define CONFIG_SPL_FRAMEWORK
210 #define CONFIG_SPL_BOARD_INIT
211 #define CONFIG_SPL_CONSOLE
212 #define CONFIG_SPL_NAND_SIMPLE
213 #define CONFIG_SPL_NAND_SOFTECC
214 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
215
216 #define CONFIG_SPL_LIBCOMMON_SUPPORT
217 #define CONFIG_SPL_LIBDISK_SUPPORT
218 #define CONFIG_SPL_I2C_SUPPORT
219 #define CONFIG_SPL_LIBGENERIC_SUPPORT
220 #define CONFIG_SPL_SERIAL_SUPPORT
221 #define CONFIG_SPL_GPIO_SUPPORT
222 #define CONFIG_SPL_POWER_SUPPORT
223 #define CONFIG_SPL_NAND_SUPPORT
224 #define CONFIG_SPL_NAND_BASE
225 #define CONFIG_SPL_NAND_DRIVERS
226 #define CONFIG_SPL_NAND_ECC
227 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
228
229 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
230 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
231
232 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
233 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
234 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
235 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
236
237 /* NAND boot config */
238 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
239 #define CONFIG_SYS_NAND_PAGE_COUNT 64
240 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
241 #define CONFIG_SYS_NAND_OOBSIZE 64
242 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
243 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
244 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
245 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
246 48, 49, 50, 51, 52, 53, 54, 55,\
247 56, 57, 58, 59, 60, 61, 62, 63}
248 #define CONFIG_SYS_NAND_ECCSIZE 256
249 #define CONFIG_SYS_NAND_ECCBYTES 3
250 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
251 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
252
253 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
254
255 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
256 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
257
258 #define CONFIG_CMD_UBI
259 #define CONFIG_CMD_UBIFS
260 #define CONFIG_RBTREE
261 #define CONFIG_LZO
262 #define CONFIG_MTD_PARTITIONS
263 #define CONFIG_MTD_DEVICE
264 #define CONFIG_CMD_MTDPARTS
265
266 /* Setup MTD for NAND on the SOM */
267 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
268 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
269 "1m(u-boot),256k(env1)," \
270 "256k(env2),6m(kernel),-(rootfs)"
271
272 #define CONFIG_TAM3517_SETTINGS \
273 "netdev=eth0\0" \
274 "nandargs=setenv bootargs root=${nandroot} " \
275 "rootfstype=${nandrootfstype}\0" \
276 "nfsargs=setenv bootargs root=/dev/nfs rw " \
277 "nfsroot=${serverip}:${rootpath}\0" \
278 "ramargs=setenv bootargs root=/dev/ram rw\0" \
279 "addip_sta=setenv bootargs ${bootargs} " \
280 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
281 ":${hostname}:${netdev}:off panic=1\0" \
282 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
283 "addip=if test -n ${ipdyn};then run addip_dyn;" \
284 "else run addip_sta;fi\0" \
285 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
286 "addtty=setenv bootargs ${bootargs}" \
287 " console=ttyO0,${baudrate}\0" \
288 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
289 "loadaddr=82000000\0" \
290 "kernel_addr_r=82000000\0" \
291 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
292 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
293 "flash_self=run ramargs addip addtty addmtd addmisc;" \
294 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
295 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
296 "bootm ${kernel_addr}\0" \
297 "nandboot=run nandargs addip addtty addmtd addmisc;" \
298 "nand read ${kernel_addr_r} kernel\0" \
299 "bootm ${kernel_addr_r}\0" \
300 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
301 "run nfsargs addip addtty addmtd addmisc;" \
302 "bootm ${kernel_addr_r}\0" \
303 "net_self=if run net_self_load;then " \
304 "run ramargs addip addtty addmtd addmisc;" \
305 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
306 "else echo Images not loades;fi\0" \
307 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
308 "load=tftp ${loadaddr} ${u-boot}\0" \
309 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
310 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
311 "uboot_addr=0x80000\0" \
312 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
313 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
314 "updatemlo=nandecc hw;nand erase 0 20000;" \
315 "nand write ${loadaddr} 0 20000\0" \
316 "upd=if run load;then echo Updating u-boot;if run update;" \
317 "then echo U-Boot updated;" \
318 "else echo Error updating u-boot !;" \
319 "echo Board without bootloader !!;" \
320 "fi;" \
321 "else echo U-Boot not downloaded..exiting;fi\0" \
322
323
324 /*
325 * this is common code for all TAM3517 boards.
326 * MAC address is stored from manufacturer in
327 * I2C EEPROM
328 */
329 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
330 /*
331 * The I2C EEPROM on the TAM3517 contains
332 * mac address and production data
333 */
334 struct tam3517_module_info {
335 char customer[48];
336 char product[48];
337
338 /*
339 * bit 0~47 : sequence number
340 * bit 48~55 : week of year, from 0.
341 * bit 56~63 : year
342 */
343 unsigned long long sequence_number;
344
345 /*
346 * bit 0~7 : revision fixed
347 * bit 8~15 : revision major
348 * bit 16~31 : TNxxx
349 */
350 unsigned int revision;
351 unsigned char eth_addr[4][8];
352 unsigned char _rev[100];
353 };
354
355 #define TAM3517_READ_EEPROM(info, ret) \
356 do { \
357 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
358 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
359 (void *)info, sizeof(*info))) \
360 ret = 1; \
361 else \
362 ret = 0; \
363 } while (0)
364
365 #define TAM3517_READ_MAC_FROM_EEPROM(info) \
366 do { \
367 char buf[80], ethname[20]; \
368 int i; \
369 memset(buf, 0, sizeof(buf)); \
370 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
371 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
372 (info)->eth_addr[i][5], \
373 (info)->eth_addr[i][4], \
374 (info)->eth_addr[i][3], \
375 (info)->eth_addr[i][2], \
376 (info)->eth_addr[i][1], \
377 (info)->eth_addr[i][0]); \
378 \
379 if (i) \
380 sprintf(ethname, "eth%daddr", i); \
381 else \
382 strcpy(ethname, "ethaddr"); \
383 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
384 setenv(ethname, buf); \
385 } \
386 } while (0)
387
388 /* The following macros are taken from Technexion's documentation */
389 #define TAM3517_sequence_number(info) \
390 ((info)->sequence_number % 0x1000000000000LL)
391 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
392 #define TAM3517_year(info) ((info)->sequence_number >> 56)
393 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
394 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
395 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
396
397 #define TAM3517_PRINT_SOM_INFO(info) \
398 do { \
399 printf("Vendor:%s\n", (info)->customer); \
400 printf("SOM: %s\n", (info)->product); \
401 printf("SeqNr: %02llu%02llu%012llu\n", \
402 TAM3517_year(info), \
403 TAM3517_week_of_year(info), \
404 TAM3517_sequence_number(info)); \
405 printf("Rev: TN%u %u.%u\n", \
406 TAM3517_revision_tn(info), \
407 TAM3517_revision_major(info), \
408 TAM3517_revision_fixed(info)); \
409 } while (0)
410
411 #endif
412
413 #endif /* __TAM3517_H */