include/configs/wb50n.h

   1 /*
   2  * Configuation settings for the WB50N CPU Module.
   3  *
   4  * SPDX-License-Identifier: GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <asm/hardware.h>
  11
  12 /* ARM asynchronous clock */
  13 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  14 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000        /* from 12 MHz crystal */
  15
  16 #define CONFIG_ARCH_CPU_INIT
  17
  18 #define CONFIG_CMDLINE_TAG      /* enable passing of ATAGs */
  19 #define CONFIG_SETUP_MEMORY_TAGS
  20 #define CONFIG_INITRD_TAG
  21
  22 #ifndef CONFIG_SPL_BUILD
  23 #define CONFIG_SKIP_LOWLEVEL_INIT
  24 #endif
  25
  26 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  27 #define CONFIG_IMAGE_FORMAT_LEGACY
  28
  29 /* general purpose I/O */
  30 #define CONFIG_AT91_GPIO
  31
  32 /* serial console */
  33 #define CONFIG_ATMEL_USART
  34 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
  35 #define CONFIG_USART_ID         ATMEL_ID_DBGU
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41
  42 /* SDRAM */
  43 #define CONFIG_NR_DRAM_BANKS        1
  44 #define CONFIG_SYS_SDRAM_BASE       ATMEL_BASE_DDRCS
  45 #define CONFIG_SYS_SDRAM_SIZE       0x04000000
  46
  47 #ifdef CONFIG_SPL_BUILD
  48 #define CONFIG_SYS_INIT_SP_ADDR     0x310000
  49 #else
  50 #define CONFIG_SYS_INIT_SP_ADDR \
  51     (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
  52 #endif
  53
  54 #define CONFIG_SYS_MEMTEST_START    0x21000000
  55 #define CONFIG_SYS_MEMTEST_END      0x22000000
  56 #define CONFIG_SYS_ALT_MEMTEST
  57
  58 /* NAND flash */
  59 #define CONFIG_NAND_ATMEL
  60 #define CONFIG_SYS_MAX_NAND_DEVICE  1
  61 #define CONFIG_SYS_NAND_BASE        ATMEL_BASE_CS3
  62 /* our ALE is AD21 */
  63 #define CONFIG_SYS_NAND_MASK_ALE    (1 << 21)
  64 /* our CLE is AD22 */
  65 #define CONFIG_SYS_NAND_MASK_CLE    (1 << 22)
  66 #define CONFIG_SYS_NAND_ONFI_DETECTION
  67 /* PMECC & PMERRLOC */
  68 #define CONFIG_ATMEL_NAND_HWECC
  69 #define CONFIG_ATMEL_NAND_HW_PMECC
  70 #define CONFIG_PMECC_CAP            8
  71 #define CONFIG_PMECC_SECTOR_SIZE    512
  72
  73 /* Ethernet Hardware */
  74 #define CONFIG_MACB
  75 #define CONFIG_RMII
  76 #define CONFIG_NET_RETRY_COUNT      20
  77 #define CONFIG_MACB_SEARCH_PHY
  78 #define CONFIG_RGMII
  79 #define CONFIG_ETHADDR              C0:EE:40:00:00:00
  80 #define CONFIG_ENV_OVERWRITE        1
  81
  82 #define CONFIG_SYS_LOAD_ADDR        0x22000000  /* load address */
  83
  84 #define CONFIG_EXTRA_ENV_SETTINGS \
  85     "autoload=no\0" \
  86     "autostart=no\0"
  87
  88 /* bootstrap + u-boot + env in nandflash */
  89 #define CONFIG_ENV_OFFSET           0xA0000
  90 #define CONFIG_ENV_OFFSET_REDUND    0xC0000
  91 #define CONFIG_ENV_SIZE             0x20000
  92 #define CONFIG_BOOTCOMMAND \
  93     "nand read 0x22000000 0x000e0000 0x500000; " \
  94     "bootm"
  95
  96 #define CONFIG_BOOTARGS \
  97     "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
  98
  99 #define CONFIG_BAUDRATE             115200
 100
 101 #define CONFIG_SYS_CBSIZE           1024
 102 #define CONFIG_SYS_MAXARGS          16
 103 #define CONFIG_SYS_PBSIZE \
 104     (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 105
 106 /* Size of malloc() pool */
 107 #define CONFIG_SYS_MALLOC_LEN       (2 * 1024 * 1024)
 108
 109 /* SPL */
 110 #define CONFIG_SPL_TEXT_BASE        0x300000
 111 #define CONFIG_SPL_MAX_SIZE         0x10000
 112 #define CONFIG_SPL_BSS_START_ADDR   0x20000000
 113 #define CONFIG_SPL_BSS_MAX_SIZE     0x80000
 114 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
 115 #define CONFIG_SYS_SPL_MALLOC_SIZE  0x80000
 116
 117 #define CONFIG_SYS_MONITOR_LEN      (512 << 10)
 118
 119 #define CONFIG_SPL_NAND_DRIVERS
 120 #define CONFIG_SPL_NAND_BASE
 121 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
 122 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 123 #define CONFIG_SYS_NAND_PAGE_SIZE   0x800
 124 #define CONFIG_SYS_NAND_PAGE_COUNT  64
 125 #define CONFIG_SYS_NAND_OOBSIZE     64
 126 #define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
 127 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
 128 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 129
 130 #endif