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Move CONFIG_OF_LIBFDT to Kconfig
[people/ms/u-boot.git] / include / configs / x600.h
1 /*
2 * (C) Copyright 2009
3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
4 *
5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14 * High Level Configuration Options
15 * (easy to change)
16 */
17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */
18 #define CONFIG_X600 /* on X600 board */
19 #define CONFIG_SYS_THUMB_BUILD
20
21 #include <asm/arch/hardware.h>
22
23 /* Timer, HZ specific defines */
24 #define CONFIG_SYS_HZ_CLOCK 8300000
25
26 #define CONFIG_SYS_TEXT_BASE 0x00800040
27 #define CONFIG_SYS_FLASH_BASE 0xf8000000
28 /* Reserve 8KiB for SPL */
29 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
30 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
31 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
32 CONFIG_SYS_SPL_LEN)
33 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
35 #define CONFIG_SYS_MONITOR_LEN 0x60000
36
37 #define CONFIG_ENV_IS_IN_FLASH
38
39 /* Serial Configuration (PL011) */
40 #define CONFIG_SYS_SERIAL0 0xD0000000
41 #define CONFIG_SYS_SERIAL1 0xD0080000
42 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
43 (void *)CONFIG_SYS_SERIAL1 }
44 #define CONFIG_PL011_SERIAL
45 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
46 #define CONFIG_CONS_INDEX 0
47 #define CONFIG_BAUDRATE 115200
48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
49 57600, 115200 }
50 #define CONFIG_SYS_LOADS_BAUD_CHANGE
51
52 /* NOR FLASH config options */
53 #define CONFIG_ST_SMI
54 #define CONFIG_SYS_MAX_FLASH_BANKS 1
55 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
56 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
57 #define CONFIG_SYS_MAX_FLASH_SECT 128
58 #define CONFIG_SYS_FLASH_EMPTY_INFO
59 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
60 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
61
62 /* NAND FLASH config options */
63 #define CONFIG_NAND_FSMC
64 #define CONFIG_SYS_NAND_SELF_INIT
65 #define CONFIG_SYS_MAX_NAND_DEVICE 1
66 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
67 #define CONFIG_MTD_ECC_SOFT
68 #define CONFIG_SYS_FSMC_NAND_8BIT
69 #define CONFIG_SYS_NAND_ONFI_DETECTION
70 #define CONFIG_NAND_ECC_BCH
71 #define CONFIG_BCH
72
73 /* UBI/UBI config options */
74 #define CONFIG_MTD_DEVICE
75 #define CONFIG_MTD_PARTITIONS
76 #define CONFIG_RBTREE
77
78 /* Ethernet config options */
79 #define CONFIG_MII
80 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
81 #define CONFIG_PHY_ADDR 0 /* PHY address */
82 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
83
84 #define CONFIG_SPEAR_GPIO
85
86 /* I2C config options */
87 #define CONFIG_SYS_I2C
88 #define CONFIG_SYS_I2C_DW
89 #define CONFIG_SYS_I2C_BASE 0xD0200000
90 #define CONFIG_SYS_I2C_SPEED 400000
91 #define CONFIG_SYS_I2C_SLAVE 0x02
92 #define CONFIG_I2C_CHIPADDRESS 0x50
93
94 #define CONFIG_RTC_M41T62 1
95 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
96
97 /* FPGA config options */
98 #define CONFIG_FPGA
99 #define CONFIG_FPGA_XILINX
100 #define CONFIG_FPGA_SPARTAN3
101 #define CONFIG_FPGA_COUNT 1
102
103 /* USB EHCI options */
104 #define CONFIG_USB_EHCI
105 #define CONFIG_USB_EHCI_SPEAR
106 #define CONFIG_USB_STORAGE
107 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
108
109 /*
110 * Command support defines
111 */
112 #define CONFIG_CMD_CACHE
113 #define CONFIG_CMD_DATE
114 #define CONFIG_CMD_DHCP
115 #define CONFIG_CMD_ENV
116 #define CONFIG_CMD_FAT
117 #define CONFIG_CMD_FPGA_LOADMK
118 #define CONFIG_CMD_FS_GENERIC
119 #define CONFIG_CMD_I2C
120 #define CONFIG_CMD_MII
121 #define CONFIG_CMD_MTDPARTS
122 #define CONFIG_CMD_NAND
123 #define CONFIG_CMD_PING
124 #define CONFIG_CMD_SAVES
125 #define CONFIG_CMD_UBI
126 #define CONFIG_CMD_UBIFS
127 #define CONFIG_CMD_USB
128 #define CONFIG_LZO
129
130 /* Filesystem support (for USB key) */
131 #define CONFIG_SUPPORT_VFAT
132 #define CONFIG_DOS_PARTITION
133
134 #define CONFIG_BOOTDELAY 3
135
136 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
137 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138
139 /*
140 * U-Boot Environment placing definitions.
141 */
142 #define CONFIG_ENV_SECT_SIZE 0x00010000
143 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
144 CONFIG_SYS_MONITOR_LEN)
145 #define CONFIG_ENV_SIZE 0x02000
146 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
147 CONFIG_ENV_SECT_SIZE)
148 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149
150 /* Miscellaneous configurable options */
151 #define CONFIG_ARCH_CPU_INIT
152 #define CONFIG_DISPLAY_CPUINFO
153 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
154 #define CONFIG_CMDLINE_TAG
155 #define CONFIG_SETUP_MEMORY_TAGS
156 #define CONFIG_MISC_INIT_R
157 #define CONFIG_BOARD_LATE_INIT
158 #define CONFIG_LOOPW /* enable loopw command */
159 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
160 #define CONFIG_ZERO_BOOTDELAY_CHECK
161
162 #define CONFIG_SYS_MEMTEST_START 0x00800000
163 #define CONFIG_SYS_MEMTEST_END 0x04000000
164 #define CONFIG_SYS_MALLOC_LEN (8 << 20)
165 #define CONFIG_IDENT_STRING "-SPEAr"
166 #define CONFIG_SYS_LONGHELP
167 #define CONFIG_CMDLINE_EDITING
168 #define CONFIG_AUTO_COMPLETE
169 #define CONFIG_SYS_CBSIZE 256
170 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
171 sizeof(CONFIG_SYS_PROMPT) + 16)
172 #define CONFIG_SYS_MAXARGS 16
173 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
174 #define CONFIG_SYS_LOAD_ADDR 0x00800000
175 #define CONFIG_SYS_CONSOLE_INFO_QUIET
176
177 /* Use last 2 lwords in internal SRAM for bootcounter */
178 #define CONFIG_BOOTCOUNT_LIMIT
179 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
180 CONFIG_SRAM_SIZE)
181
182 #define CONFIG_HOSTNAME x600
183 #define CONFIG_UBI_PART ubi0
184 #define CONFIG_UBIFS_VOLUME rootfs
185
186 #define MTDIDS_DEFAULT "nand0=nand"
187 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
188
189 #define CONFIG_EXTRA_ENV_SETTINGS \
190 "u-boot_addr=1000000\0" \
191 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
192 "load=tftp ${u-boot_addr} ${u-boot}\0" \
193 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
194 " +${filesize};" \
195 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
196 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
197 " ${filesize};" \
198 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
199 " +${filesize}\0" \
200 "upd=run load update\0" \
201 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
202 "part=" __stringify(CONFIG_UBI_PART) "\0" \
203 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
204 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
205 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
206 " ${filesize}\0" \
207 "upd_ubifs=run load_ubifs update_ubifs\0" \
208 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
209 "ubi create ${vol} 4000000\0" \
210 "netdev=eth0\0" \
211 "rootpath=/opt/eldk-4.2/arm\0" \
212 "nfsargs=setenv bootargs root=/dev/nfs rw " \
213 "nfsroot=${serverip}:${rootpath}\0" \
214 "ramargs=setenv bootargs root=/dev/ram rw\0" \
215 "boot_part=0\0" \
216 "altbootcmd=if test $boot_part -eq 0;then " \
217 "echo Switching to partition 1!;" \
218 "setenv boot_part 1;" \
219 "else; " \
220 "echo Switching to partition 0!;" \
221 "setenv boot_part 0;" \
222 "fi;" \
223 "saveenv;boot\0" \
224 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
225 "root=ubi0:rootfs rootfstype=ubifs\0" \
226 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
227 "kernel_fs=/boot/uImage \0" \
228 "kernel_addr=1000000\0" \
229 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
230 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
231 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
232 "dtb_addr=1800000\0" \
233 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
234 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
235 "addip=setenv bootargs ${bootargs} " \
236 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
237 ":${hostname}:${netdev}:off panic=1\0" \
238 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
239 "${baudrate}\0" \
240 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
241 "net_nfs=run load_dtb load_kernel; " \
242 "run nfsargs addip addcon addmtd addmisc;" \
243 "bootm ${kernel_addr} - ${dtb_addr}\0" \
244 "mtdids=" MTDIDS_DEFAULT "\0" \
245 "mtdparts=" MTDPARTS_DEFAULT "\0" \
246 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
247 " addcon addmisc addmtd;" \
248 "bootm ${kernel_addr} - ${dtb_addr}\0" \
249 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
250 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
251 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
252 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
253 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
254 "bootcmd=run nand_ubifs\0" \
255 "\0"
256
257 /* Physical Memory Map */
258 #define CONFIG_NR_DRAM_BANKS 1
259 #define PHYS_SDRAM_1 0x00000000
260 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
261
262 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
263 #define CONFIG_SRAM_BASE 0xd2800000
264 /* Preserve the last 2 lwords for the boot-counter */
265 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
266 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
267 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
268
269 #define CONFIG_SYS_INIT_SP_OFFSET \
270 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
271
272 #define CONFIG_SYS_INIT_SP_ADDR \
273 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
274
275 /*
276 * SPL related defines
277 */
278 #define CONFIG_SPL_TEXT_BASE 0xd2800b00
279 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
280 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
281 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
282
283 #define CONFIG_SPL_FRAMEWORK
284 #define CONFIG_SPL_NOR_SUPPORT
285 #define CONFIG_SPL_SERIAL_SUPPORT
286 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
287 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
288
289 /*
290 * Please select/define only one of the following
291 * Each definition corresponds to a supported DDR chip.
292 * DDR configuration is based on the following selection
293 */
294 #define CONFIG_DDR_MT47H64M16 1
295 #define CONFIG_DDR_MT47H32M16 0
296 #define CONFIG_DDR_MT47H128M8 0
297
298 /*
299 * Synchronous/Asynchronous operation of DDR
300 *
301 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
302 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
303 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
304 */
305 #define CONFIG_DDR_2HCLK 1
306 #define CONFIG_DDR_HCLK 0
307 #define CONFIG_DDR_PLL2 0
308
309 /*
310 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
311 * or not. Modify/Add to only these macros to define new boot types
312 */
313 #define USB_BOOT_SUPPORTED 0
314 #define PCIE_BOOT_SUPPORTED 0
315 #define SNOR_BOOT_SUPPORTED 1
316 #define NAND_BOOT_SUPPORTED 1
317 #define PNOR_BOOT_SUPPORTED 0
318 #define TFTP_BOOT_SUPPORTED 0
319 #define UART_BOOT_SUPPORTED 0
320 #define SPI_BOOT_SUPPORTED 0
321 #define I2C_BOOT_SUPPORTED 0
322 #define MMC_BOOT_SUPPORTED 0
323
324 #endif /* __CONFIG_H */