include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 /* XXX U-BOOT XXX */
  22 #if 0
  23 #include <linux/wait.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/mtd/mtd.h>
  26 #endif
  27
  28 #include "config.h"
  29
  30 #include "linux/mtd/compat.h"
  31 #include "linux/mtd/mtd.h"
  32 #include "linux/mtd/bbm.h"
  33
  34
  35 struct mtd_info;
  36 struct nand_flash_dev;
  37 /* Scan and identify a NAND device */
  38 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  39 /* Separate phases of nand_scan(), allowing board driver to intervene
  40  * and override command or ECC setup according to flash type */
  41 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  42                            const struct nand_flash_dev *table);
  43 extern int nand_scan_tail(struct mtd_info *mtd);
  44
  45 /* Free resources held by the NAND device */
  46 extern void nand_release (struct mtd_info *mtd);
  47
  48 /* Internal helper for board drivers which need to override command function */
  49 extern void nand_wait_ready(struct mtd_info *mtd);
  50
  51 /* This constant declares the max. oobsize / page, which
  52  * is supported now. If you add a chip with bigger oobsize/page
  53  * adjust this accordingly.
  54  */
  55 #define NAND_MAX_OOBSIZE        218
  56 #define NAND_MAX_PAGESIZE       4096
  57
  58 /*
  59  * Constants for hardware specific CLE/ALE/NCE function
  60  *
  61  * These are bits which can be or'ed to set/clear multiple
  62  * bits in one go.
  63  */
  64 /* Select the chip by setting nCE to low */
  65 #define NAND_NCE                0x01
  66 /* Select the command latch by setting CLE to high */
  67 #define NAND_CLE                0x02
  68 /* Select the address latch by setting ALE to high */
  69 #define NAND_ALE                0x04
  70
  71 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  72 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  73 #define NAND_CTRL_CHANGE        0x80
  74
  75 /*
  76  * Standard NAND flash commands
  77  */
  78 #define NAND_CMD_READ0          0
  79 #define NAND_CMD_READ1          1
  80 #define NAND_CMD_RNDOUT         5
  81 #define NAND_CMD_PAGEPROG       0x10
  82 #define NAND_CMD_READOOB        0x50
  83 #define NAND_CMD_ERASE1         0x60
  84 #define NAND_CMD_STATUS         0x70
  85 #define NAND_CMD_STATUS_MULTI   0x71
  86 #define NAND_CMD_SEQIN          0x80
  87 #define NAND_CMD_RNDIN          0x85
  88 #define NAND_CMD_READID         0x90
  89 #define NAND_CMD_PARAM          0xec
  90 #define NAND_CMD_ERASE2         0xd0
  91 #define NAND_CMD_RESET          0xff
  92
  93 /* Extended commands for large page devices */
  94 #define NAND_CMD_READSTART      0x30
  95 #define NAND_CMD_RNDOUTSTART    0xE0
  96 #define NAND_CMD_CACHEDPROG     0x15
  97
  98 /* Extended commands for AG-AND device */
  99 /*
 100  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 101  *       there is no way to distinguish that from NAND_CMD_READ0
 102  *       until the remaining sequence of commands has been completed
 103  *       so add a high order bit and mask it off in the command.
 104  */
 105 #define NAND_CMD_DEPLETE1       0x100
 106 #define NAND_CMD_DEPLETE2       0x38
 107 #define NAND_CMD_STATUS_MULTI   0x71
 108 #define NAND_CMD_STATUS_ERROR   0x72
 109 /* multi-bank error status (banks 0-3) */
 110 #define NAND_CMD_STATUS_ERROR0  0x73
 111 #define NAND_CMD_STATUS_ERROR1  0x74
 112 #define NAND_CMD_STATUS_ERROR2  0x75
 113 #define NAND_CMD_STATUS_ERROR3  0x76
 114 #define NAND_CMD_STATUS_RESET   0x7f
 115 #define NAND_CMD_STATUS_CLEAR   0xff
 116
 117 #define NAND_CMD_NONE           -1
 118
 119 /* Status bits */
 120 #define NAND_STATUS_FAIL        0x01
 121 #define NAND_STATUS_FAIL_N1     0x02
 122 #define NAND_STATUS_TRUE_READY  0x20
 123 #define NAND_STATUS_READY       0x40
 124 #define NAND_STATUS_WP          0x80
 125
 126 /*
 127  * Constants for ECC_MODES
 128  */
 129 typedef enum {
 130         NAND_ECC_NONE,
 131         NAND_ECC_SOFT,
 132         NAND_ECC_HW,
 133         NAND_ECC_HW_SYNDROME,
 134         NAND_ECC_HW_OOB_FIRST,
 135 } nand_ecc_modes_t;
 136
 137 /*
 138  * Constants for Hardware ECC
 139  */
 140 /* Reset Hardware ECC for read */
 141 #define NAND_ECC_READ           0
 142 /* Reset Hardware ECC for write */
 143 #define NAND_ECC_WRITE          1
 144 /* Enable Hardware ECC before syndrom is read back from flash */
 145 #define NAND_ECC_READSYN        2
 146
 147 /* Bit mask for flags passed to do_nand_read_ecc */
 148 #define NAND_GET_DEVICE         0x80
 149
 150
 151 /* Option constants for bizarre disfunctionality and real
 152 *  features
 153 */
 154 /* Chip can not auto increment pages */
 155 #define NAND_NO_AUTOINCR        0x00000001
 156 /* Buswitdh is 16 bit */
 157 #define NAND_BUSWIDTH_16        0x00000002
 158 /* Device supports partial programming without padding */
 159 #define NAND_NO_PADDING         0x00000004
 160 /* Chip has cache program function */
 161 #define NAND_CACHEPRG           0x00000008
 162 /* Chip has copy back function */
 163 #define NAND_COPYBACK           0x00000010
 164 /* AND Chip which has 4 banks and a confusing page / block
 165  * assignment. See Renesas datasheet for further information */
 166 #define NAND_IS_AND             0x00000020
 167 /* Chip has a array of 4 pages which can be read without
 168  * additional ready /busy waits */
 169 #define NAND_4PAGE_ARRAY        0x00000040
 170 /* Chip requires that BBT is periodically rewritten to prevent
 171  * bits from adjacent blocks from 'leaking' in altering data.
 172  * This happens with the Renesas AG-AND chips, possibly others.  */
 173 #define BBT_AUTO_REFRESH        0x00000080
 174 /* Chip does not require ready check on read. True
 175  * for all large page devices, as they do not support
 176  * autoincrement.*/
 177 #define NAND_NO_READRDY         0x00000100
 178 /* Chip does not allow subpage writes */
 179 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 180
 181
 182 /* Options valid for Samsung large page devices */
 183 #define NAND_SAMSUNG_LP_OPTIONS \
 184         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 185
 186 /* Macros to identify the above */
 187 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 188 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 189 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 190 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 191 /* Large page NAND with SOFT_ECC should support subpage reads */
 192 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
 193                                         && (chip->page_shift > 9))
 194
 195 /* Mask to zero out the chip options, which come from the id table */
 196 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 197
 198 /* Non chip related options */
 199 /* Use a flash based bad block table. This option is passed to the
 200  * default bad block table function. */
 201 #define NAND_USE_FLASH_BBT      0x00010000
 202 /* This option skips the bbt scan during initialization. */
 203 #define NAND_SKIP_BBTSCAN       0x00020000
 204 /* This option is defined if the board driver allocates its own buffers
 205    (e.g. because it needs them DMA-coherent */
 206 #define NAND_OWN_BUFFERS        0x00040000
 207 /* Options set by nand scan */
 208 /* bbt has already been read */
 209 #define NAND_BBT_SCANNED        0x40000000
 210 /* Nand scan has allocated controller struct */
 211 #define NAND_CONTROLLER_ALLOC   0x80000000
 212
 213 /* Cell info constants */
 214 #define NAND_CI_CHIPNR_MSK      0x03
 215 #define NAND_CI_CELLTYPE_MSK    0x0C
 216
 217 /* Keep gcc happy */
 218 struct nand_chip;
 219
 220 /**
 221  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 222  * @lock:               protection lock
 223  * @active:             the mtd device which holds the controller currently
 224  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 225  *                      used instead of the per chip wait queue when a hw controller is available
 226  */
 227 struct nand_hw_control {
 228 /* XXX U-BOOT XXX */
 229 #if 0
 230         spinlock_t       lock;
 231         wait_queue_head_t wq;
 232 #endif
 233         struct nand_chip *active;
 234 };
 235
 236 /**
 237  * struct nand_ecc_ctrl - Control structure for ecc
 238  * @mode:       ecc mode
 239  * @steps:      number of ecc steps per page
 240  * @size:       data bytes per ecc step
 241  * @bytes:      ecc bytes per step
 242  * @total:      total number of ecc bytes per page
 243  * @prepad:     padding information for syndrome based ecc generators
 244  * @postpad:    padding information for syndrome based ecc generators
 245  * @layout:     ECC layout control struct pointer
 246  * @hwctl:      function to control hardware ecc generator. Must only
 247  *              be provided if an hardware ECC is available
 248  * @calculate:  function for ecc calculation or readback from ecc hardware
 249  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 250  * @read_page_raw:      function to read a raw page without ECC
 251  * @write_page_raw:     function to write a raw page without ECC
 252  * @read_page:  function to read a page according to the ecc generator requirements
 253  * @write_page: function to write a page according to the ecc generator requirements
 254  * @read_oob:   function to read chip OOB data
 255  * @write_oob:  function to write chip OOB data
 256  */
 257 struct nand_ecc_ctrl {
 258         nand_ecc_modes_t        mode;
 259         int                     steps;
 260         int                     size;
 261         int                     bytes;
 262         int                     total;
 263         int                     prepad;
 264         int                     postpad;
 265         struct nand_ecclayout   *layout;
 266         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 267         int                     (*calculate)(struct mtd_info *mtd,
 268                                              const uint8_t *dat,
 269                                              uint8_t *ecc_code);
 270         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 271                                            uint8_t *read_ecc,
 272                                            uint8_t *calc_ecc);
 273         int                     (*read_page_raw)(struct mtd_info *mtd,
 274                                                  struct nand_chip *chip,
 275                                                  uint8_t *buf, int page);
 276         void                    (*write_page_raw)(struct mtd_info *mtd,
 277                                                   struct nand_chip *chip,
 278                                                   const uint8_t *buf);
 279         int                     (*read_page)(struct mtd_info *mtd,
 280                                              struct nand_chip *chip,
 281                                              uint8_t *buf, int page);
 282         int                     (*read_subpage)(struct mtd_info *mtd,
 283                                              struct nand_chip *chip,
 284                                              uint32_t offs, uint32_t len,
 285                                              uint8_t *buf);
 286         void                    (*write_page)(struct mtd_info *mtd,
 287                                               struct nand_chip *chip,
 288                                               const uint8_t *buf);
 289         int                     (*read_oob)(struct mtd_info *mtd,
 290                                             struct nand_chip *chip,
 291                                             int page,
 292                                             int sndcmd);
 293         int                     (*write_oob)(struct mtd_info *mtd,
 294                                              struct nand_chip *chip,
 295                                              int page);
 296 };
 297
 298 /**
 299  * struct nand_buffers - buffer structure for read/write
 300  * @ecccalc:    buffer for calculated ecc
 301  * @ecccode:    buffer for ecc read from flash
 302  * @databuf:    buffer for data - dynamically sized
 303  *
 304  * Do not change the order of buffers. databuf and oobrbuf must be in
 305  * consecutive order.
 306  */
 307 struct nand_buffers {
 308         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 309         uint8_t ecccode[NAND_MAX_OOBSIZE];
 310         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 311 };
 312
 313 /**
 314  * struct nand_chip - NAND Private Flash Chip Data
 315  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 316  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 317  * @read_byte:          [REPLACEABLE] read one byte from the chip
 318  * @read_word:          [REPLACEABLE] read one word from the chip
 319  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 320  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 321  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 322  * @select_chip:        [REPLACEABLE] select chip nr
 323  * @block_bad:          [REPLACEABLE] check, if the block is bad
 324  * @block_markbad:      [REPLACEABLE] mark the block bad
 325  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 326  *                      ALE/CLE/nCE. Also used to write command and address
 327  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 328  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 329  *                      is read from the chip status register
 330  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 331  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 332  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 333  * @buffers:            buffer structure for read/write
 334  * @hwcontrol:          platform-specific hardware control structure
 335  * @ops:                oob operation operands
 336  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 337  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 338  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 339  * @wq:                 [INTERN] wait queue to sleep on if a NAND operation is in progress
 340  * @state:              [INTERN] the current state of the NAND device
 341  * @oob_poi:            poison value buffer
 342  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 343  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 344  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 345  * @chip_shift:         [INTERN] number of address bits in one chip
 346  * @datbuf:             [INTERN] internal buffer for one page + oob
 347  * @oobbuf:             [INTERN] oob buffer for one eraseblock
 348  * @oobdirty:           [INTERN] indicates that oob_buf must be reinitialized
 349  * @data_poi:           [INTERN] pointer to a data buffer
 350  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 351  *                      special functionality. See the defines for further explanation
 352  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 353  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 354  * @numchips:           [INTERN] number of physical chips
 355  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 356  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 357  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 358  * @subpagesize:        [INTERN] holds the subpagesize
 359  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 360  * @bbt:                [INTERN] bad block table pointer
 361  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 362  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 363  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 364  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 365  *                      which is shared among multiple independend devices
 366  * @priv:               [OPTIONAL] pointer to private chip date
 367  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 368  *                      (determine if errors are correctable)
 369  * @write_page:         [REPLACEABLE] High-level page write function
 370  */
 371
 372 struct nand_chip {
 373         void  __iomem   *IO_ADDR_R;
 374         void  __iomem   *IO_ADDR_W;
 375
 376         uint8_t         (*read_byte)(struct mtd_info *mtd);
 377         u16             (*read_word)(struct mtd_info *mtd);
 378         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 379         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 380         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 381         void            (*select_chip)(struct mtd_info *mtd, int chip);
 382         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 383         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 384         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 385                                     unsigned int ctrl);
 386         int             (*dev_ready)(struct mtd_info *mtd);
 387         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 388         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 389         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 390         int             (*scan_bbt)(struct mtd_info *mtd);
 391         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 392         int             (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 393                                       const uint8_t *buf, int page, int cached, int raw);
 394
 395         int             chip_delay;
 396         unsigned int    options;
 397
 398         int             page_shift;
 399         int             phys_erase_shift;
 400         int             bbt_erase_shift;
 401         int             chip_shift;
 402         int             numchips;
 403         uint64_t        chipsize;
 404         int             pagemask;
 405         int             pagebuf;
 406         int             subpagesize;
 407         uint8_t         cellinfo;
 408         int             badblockpos;
 409
 410         int             state;
 411
 412         uint8_t         *oob_poi;
 413         struct nand_hw_control  *controller;
 414         struct nand_ecclayout   *ecclayout;
 415
 416         struct nand_ecc_ctrl ecc;
 417         struct nand_buffers *buffers;
 418
 419         struct nand_hw_control hwcontrol;
 420
 421         struct mtd_oob_ops ops;
 422
 423         uint8_t         *bbt;
 424         struct nand_bbt_descr   *bbt_td;
 425         struct nand_bbt_descr   *bbt_md;
 426
 427         struct nand_bbt_descr   *badblock_pattern;
 428
 429         void            *priv;
 430 };
 431
 432 /*
 433  * NAND Flash Manufacturer ID Codes
 434  */
 435 #define NAND_MFR_TOSHIBA        0x98
 436 #define NAND_MFR_SAMSUNG        0xec
 437 #define NAND_MFR_FUJITSU        0x04
 438 #define NAND_MFR_NATIONAL       0x8f
 439 #define NAND_MFR_RENESAS        0x07
 440 #define NAND_MFR_STMICRO        0x20
 441 #define NAND_MFR_HYNIX          0xad
 442 #define NAND_MFR_MICRON         0x2c
 443 #define NAND_MFR_AMD            0x01
 444
 445 /**
 446  * struct nand_flash_dev - NAND Flash Device ID Structure
 447  * @name:       Identify the device type
 448  * @id:         device ID code
 449  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 450  *              If the pagesize is 0, then the real pagesize
 451  *              and the eraseize are determined from the
 452  *              extended id bytes in the chip
 453  * @erasesize:  Size of an erase block in the flash device.
 454  * @chipsize:   Total chipsize in Mega Bytes
 455  * @options:    Bitfield to store chip relevant options
 456  */
 457 struct nand_flash_dev {
 458         char *name;
 459         int id;
 460         unsigned long pagesize;
 461         unsigned long chipsize;
 462         unsigned long erasesize;
 463         unsigned long options;
 464 };
 465
 466 /**
 467  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 468  * @name:       Manufacturer name
 469  * @id:         manufacturer ID code of device.
 470 */
 471 struct nand_manufacturers {
 472         int id;
 473         char * name;
 474 };
 475
 476 extern const struct nand_flash_dev nand_flash_ids[];
 477 extern const struct nand_manufacturers nand_manuf_ids[];
 478
 479 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 480 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 481 extern int nand_default_bbt(struct mtd_info *mtd);
 482 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 483 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 484                            int allowbbt);
 485 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 486                         size_t * retlen, uint8_t * buf);
 487
 488 /*
 489 * Constants for oob configuration
 490 */
 491 #define NAND_SMALL_BADBLOCK_POS         5
 492 #define NAND_LARGE_BADBLOCK_POS         0
 493
 494 /**
 495  * struct platform_nand_chip - chip level device structure
 496  * @nr_chips:           max. number of chips to scan for
 497  * @chip_offset:        chip number offset
 498  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 499  * @partitions:         mtd partition list
 500  * @chip_delay:         R/B delay value in us
 501  * @options:            Option flags, e.g. 16bit buswidth
 502  * @ecclayout:          ecc layout info structure
 503  * @part_probe_types:   NULL-terminated array of probe types
 504  * @priv:               hardware controller specific settings
 505  */
 506 struct platform_nand_chip {
 507         int                     nr_chips;
 508         int                     chip_offset;
 509         int                     nr_partitions;
 510         struct mtd_partition    *partitions;
 511         struct nand_ecclayout   *ecclayout;
 512         int                     chip_delay;
 513         unsigned int            options;
 514         const char              **part_probe_types;
 515         void                    *priv;
 516 };
 517
 518 /**
 519  * struct platform_nand_ctrl - controller level device structure
 520  * @hwcontrol:          platform specific hardware control structure
 521  * @dev_ready:          platform specific function to read ready/busy pin
 522  * @select_chip:        platform specific chip select function
 523  * @cmd_ctrl:           platform specific function for controlling
 524  *                      ALE/CLE/nCE. Also used to write command and address
 525  * @priv:               private data to transport driver specific settings
 526  *
 527  * All fields are optional and depend on the hardware driver requirements
 528  */
 529 struct platform_nand_ctrl {
 530         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 531         int             (*dev_ready)(struct mtd_info *mtd);
 532         void            (*select_chip)(struct mtd_info *mtd, int chip);
 533         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 534                                     unsigned int ctrl);
 535         void            *priv;
 536 };
 537
 538 /**
 539  * struct platform_nand_data - container structure for platform-specific data
 540  * @chip:               chip level chip structure
 541  * @ctrl:               controller level device structure
 542  */
 543 struct platform_nand_data {
 544         struct platform_nand_chip       chip;
 545         struct platform_nand_ctrl       ctrl;
 546 };
 547
 548 /* Some helpers to access the data structures */
 549 static inline
 550 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 551 {
 552         struct nand_chip *chip = mtd->priv;
 553
 554         return chip->priv;
 555 }
 556
 557 #endif /* __LINUX_MTD_NAND_H */