include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/sizes.h>
  15 #include <linux/compiler.h>
  16 #include <part.h>
  17
  18 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  19 #define MMC_SUPPORTS_TUNING
  20 #endif
  21 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  22 #define MMC_SUPPORTS_TUNING
  23 #endif
  24
  25 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  26 #define SD_VERSION_SD   (1U << 31)
  27 #define MMC_VERSION_MMC (1U << 30)
  28
  29 #define MAKE_SDMMC_VERSION(a, b, c)     \
  30         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  31 #define MAKE_SD_VERSION(a, b, c)        \
  32         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  33 #define MAKE_MMC_VERSION(a, b, c)       \
  34         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  35
  36 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  37         (((u32)(x) >> 16) & 0xff)
  38 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  39         (((u32)(x) >> 8) & 0xff)
  40 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  41         ((u32)(x) & 0xff)
  42
  43 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  44 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  45 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  46 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  47
  48 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  49 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  50 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  51 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  52 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  53 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  54 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  55 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  56 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  57 #define MMC_VERSION_4_4         MAKE_MMC_VERSION(4, 4, 0)
  58 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  59 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  60 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  61 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  62
  63 #define MMC_CAP(mode)           (1 << mode)
  64 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  65 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  66 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  67 #define MMC_MODE_HS200          MMC_CAP(MMC_HS_200)
  68
  69 #define MMC_MODE_8BIT           BIT(30)
  70 #define MMC_MODE_4BIT           BIT(29)
  71 #define MMC_MODE_1BIT           BIT(28)
  72 #define MMC_MODE_SPI            BIT(27)
  73
  74
  75 #define SD_DATA_4BIT    0x00040000
  76
  77 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  78 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  79
  80 #define MMC_DATA_READ           1
  81 #define MMC_DATA_WRITE          2
  82
  83 #define MMC_CMD_GO_IDLE_STATE           0
  84 #define MMC_CMD_SEND_OP_COND            1
  85 #define MMC_CMD_ALL_SEND_CID            2
  86 #define MMC_CMD_SET_RELATIVE_ADDR       3
  87 #define MMC_CMD_SET_DSR                 4
  88 #define MMC_CMD_SWITCH                  6
  89 #define MMC_CMD_SELECT_CARD             7
  90 #define MMC_CMD_SEND_EXT_CSD            8
  91 #define MMC_CMD_SEND_CSD                9
  92 #define MMC_CMD_SEND_CID                10
  93 #define MMC_CMD_STOP_TRANSMISSION       12
  94 #define MMC_CMD_SEND_STATUS             13
  95 #define MMC_CMD_SET_BLOCKLEN            16
  96 #define MMC_CMD_READ_SINGLE_BLOCK       17
  97 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  98 #define MMC_CMD_SEND_TUNING_BLOCK               19
  99 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
 100 #define MMC_CMD_SET_BLOCK_COUNT         23
 101 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
 102 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
 103 #define MMC_CMD_ERASE_GROUP_START       35
 104 #define MMC_CMD_ERASE_GROUP_END         36
 105 #define MMC_CMD_ERASE                   38
 106 #define MMC_CMD_APP_CMD                 55
 107 #define MMC_CMD_SPI_READ_OCR            58
 108 #define MMC_CMD_SPI_CRC_ON_OFF          59
 109 #define MMC_CMD_RES_MAN                 62
 110
 111 #define MMC_CMD62_ARG1                  0xefac62ec
 112 #define MMC_CMD62_ARG2                  0xcbaea7
 113
 114
 115 #define SD_CMD_SEND_RELATIVE_ADDR       3
 116 #define SD_CMD_SWITCH_FUNC              6
 117 #define SD_CMD_SEND_IF_COND             8
 118 #define SD_CMD_SWITCH_UHS18V            11
 119
 120 #define SD_CMD_APP_SET_BUS_WIDTH        6
 121 #define SD_CMD_APP_SD_STATUS            13
 122 #define SD_CMD_ERASE_WR_BLK_START       32
 123 #define SD_CMD_ERASE_WR_BLK_END         33
 124 #define SD_CMD_APP_SEND_OP_COND         41
 125 #define SD_CMD_APP_SEND_SCR             51
 126
 127 static inline bool mmc_is_tuning_cmd(uint cmdidx)
 128 {
 129         if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
 130             (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
 131                 return true;
 132         return false;
 133 }
 134
 135 /* SCR definitions in different words */
 136 #define SD_HIGHSPEED_BUSY       0x00020000
 137 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 138
 139 #define UHS_SDR12_BUS_SPEED     0
 140 #define HIGH_SPEED_BUS_SPEED    1
 141 #define UHS_SDR25_BUS_SPEED     1
 142 #define UHS_SDR50_BUS_SPEED     2
 143 #define UHS_SDR104_BUS_SPEED    3
 144 #define UHS_DDR50_BUS_SPEED     4
 145
 146 #define SD_MODE_UHS_SDR12       BIT(UHS_SDR12_BUS_SPEED)
 147 #define SD_MODE_UHS_SDR25       BIT(UHS_SDR25_BUS_SPEED)
 148 #define SD_MODE_UHS_SDR50       BIT(UHS_SDR50_BUS_SPEED)
 149 #define SD_MODE_UHS_SDR104      BIT(UHS_SDR104_BUS_SPEED)
 150 #define SD_MODE_UHS_DDR50       BIT(UHS_DDR50_BUS_SPEED)
 151
 152 #define OCR_BUSY                0x80000000
 153 #define OCR_HCS                 0x40000000
 154 #define OCR_S18R                0x1000000
 155 #define OCR_VOLTAGE_MASK        0x007FFF80
 156 #define OCR_ACCESS_MODE         0x60000000
 157
 158 #define MMC_ERASE_ARG           0x00000000
 159 #define MMC_SECURE_ERASE_ARG    0x80000000
 160 #define MMC_TRIM_ARG            0x00000001
 161 #define MMC_DISCARD_ARG         0x00000003
 162 #define MMC_SECURE_TRIM1_ARG    0x80000001
 163 #define MMC_SECURE_TRIM2_ARG    0x80008000
 164
 165 #define MMC_STATUS_MASK         (~0x0206BF7F)
 166 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 167 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 168 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 169 #define MMC_STATUS_ERROR        (1 << 19)
 170
 171 #define MMC_STATE_PRG           (7 << 9)
 172
 173 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 174 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 175 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 176 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 177 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 178 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 179 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 180 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 181 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 182 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 183 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 184 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 185 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 186 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 187 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 188 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 189 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 190
 191 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 192 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 193                                                 addressed by index which are
 194                                                 1 in value field */
 195 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 196                                                 addressed by index, which are
 197                                                 1 in value field */
 198 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 199
 200 #define SD_SWITCH_CHECK         0
 201 #define SD_SWITCH_SWITCH        1
 202
 203 /*
 204  * EXT_CSD fields
 205  */
 206 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 207 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 208 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 209 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 210 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 211 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 212 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 213 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 214 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 215 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 216 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 217 #define EXT_CSD_RPMB_MULT               168     /* RO */
 218 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 219 #define EXT_CSD_BOOT_BUS_WIDTH          177
 220 #define EXT_CSD_PART_CONF               179     /* R/W */
 221 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 222 #define EXT_CSD_HS_TIMING               185     /* R/W */
 223 #define EXT_CSD_REV                     192     /* RO */
 224 #define EXT_CSD_CARD_TYPE               196     /* RO */
 225 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 226 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 227 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 228 #define EXT_CSD_BOOT_MULT               226     /* RO */
 229 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 230
 231 /*
 232  * EXT_CSD field definitions
 233  */
 234
 235 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 236 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 237 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 238
 239 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 240 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 241 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 242 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 243 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 244                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 245
 246 #define EXT_CSD_CARD_TYPE_HS200_1_8V    BIT(4)  /* Card can run at 200MHz */
 247                                                 /* SDR mode @1.8V I/O */
 248 #define EXT_CSD_CARD_TYPE_HS200_1_2V    BIT(5)  /* Card can run at 200MHz */
 249                                                 /* SDR mode @1.2V I/O */
 250 #define EXT_CSD_CARD_TYPE_HS200         (EXT_CSD_CARD_TYPE_HS200_1_8V | \
 251                                          EXT_CSD_CARD_TYPE_HS200_1_2V)
 252
 253 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 254 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 255 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 256 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 257 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 258 #define EXT_CSD_DDR_FLAG        BIT(2)  /* Flag for DDR mode */
 259
 260 #define EXT_CSD_TIMING_LEGACY   0       /* no high speed */
 261 #define EXT_CSD_TIMING_HS       1       /* HS */
 262 #define EXT_CSD_TIMING_HS200    2       /* HS200 */
 263
 264 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 265 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 266 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 267 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 268
 269 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 270 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 271 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 272
 273 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 274 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 275 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 276
 277 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 278 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 279 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 280
 281 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 282
 283 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 284 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 285
 286 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 287
 288 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 289 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 290
 291 #define R1_ILLEGAL_COMMAND              (1 << 22)
 292 #define R1_APP_CMD                      (1 << 5)
 293
 294 #define MMC_RSP_PRESENT (1 << 0)
 295 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 296 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 297 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 298 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 299
 300 #define MMC_RSP_NONE    (0)
 301 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 302 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 303                         MMC_RSP_BUSY)
 304 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 305 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 306 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 307 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 308 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 309 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 310
 311 #define MMCPART_NOAVAILABLE     (0xff)
 312 #define PART_ACCESS_MASK        (0x7)
 313 #define PART_SUPPORT            (0x1)
 314 #define ENHNCD_SUPPORT          (0x2)
 315 #define PART_ENH_ATTRIB         (0x1f)
 316
 317 #define MMC_QUIRK_RETRY_SEND_CID        BIT(0)
 318 #define MMC_QUIRK_RETRY_SET_BLOCKLEN    BIT(1)
 319
 320 enum mmc_voltage {
 321         MMC_SIGNAL_VOLTAGE_000 = 0,
 322         MMC_SIGNAL_VOLTAGE_120 = 1,
 323         MMC_SIGNAL_VOLTAGE_180 = 2,
 324         MMC_SIGNAL_VOLTAGE_330 = 4,
 325 };
 326
 327 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
 328                                 MMC_SIGNAL_VOLTAGE_180 |\
 329                                 MMC_SIGNAL_VOLTAGE_330)
 330
 331 /* Maximum block size for MMC */
 332 #define MMC_MAX_BLOCK_LEN       512
 333
 334 /* The number of MMC physical partitions.  These consist of:
 335  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 336  */
 337 #define MMC_NUM_BOOT_PARTITION  2
 338 #define MMC_PART_RPMB           3       /* RPMB partition number */
 339
 340 /* Driver model support */
 341
 342 /**
 343  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 344  */
 345 struct mmc_uclass_priv {
 346         struct mmc *mmc;
 347 };
 348
 349 /**
 350  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 351  *
 352  * Provided that the device is already probed and ready for use, this value
 353  * will be available.
 354  *
 355  * @dev:        Device
 356  * @return associated mmc struct pointer if available, else NULL
 357  */
 358 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
 359
 360 /* End of driver model support */
 361
 362 struct mmc_cid {
 363         unsigned long psn;
 364         unsigned short oid;
 365         unsigned char mid;
 366         unsigned char prv;
 367         unsigned char mdt;
 368         char pnm[7];
 369 };
 370
 371 struct mmc_cmd {
 372         ushort cmdidx;
 373         uint resp_type;
 374         uint cmdarg;
 375         uint response[4];
 376 };
 377
 378 struct mmc_data {
 379         union {
 380                 char *dest;
 381                 const char *src; /* src buffers don't get written to */
 382         };
 383         uint flags;
 384         uint blocks;
 385         uint blocksize;
 386 };
 387
 388 /* forward decl. */
 389 struct mmc;
 390
 391 #if CONFIG_IS_ENABLED(DM_MMC)
 392 struct dm_mmc_ops {
 393         /**
 394          * send_cmd() - Send a command to the MMC device
 395          *
 396          * @dev:        Device to receive the command
 397          * @cmd:        Command to send
 398          * @data:       Additional data to send/receive
 399          * @return 0 if OK, -ve on error
 400          */
 401         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 402                         struct mmc_data *data);
 403
 404         /**
 405          * set_ios() - Set the I/O speed/width for an MMC device
 406          *
 407          * @dev:        Device to update
 408          * @return 0 if OK, -ve on error
 409          */
 410         int (*set_ios)(struct udevice *dev);
 411
 412         /**
 413          * send_init_stream() - send the initialization stream: 74 clock cycles
 414          * This is used after power up before sending the first command
 415          *
 416          * @dev:        Device to update
 417          */
 418         void (*send_init_stream)(struct udevice *dev);
 419
 420         /**
 421          * get_cd() - See whether a card is present
 422          *
 423          * @dev:        Device to check
 424          * @return 0 if not present, 1 if present, -ve on error
 425          */
 426         int (*get_cd)(struct udevice *dev);
 427
 428         /**
 429          * get_wp() - See whether a card has write-protect enabled
 430          *
 431          * @dev:        Device to check
 432          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 433          */
 434         int (*get_wp)(struct udevice *dev);
 435
 436 #ifdef MMC_SUPPORTS_TUNING
 437         /**
 438          * execute_tuning() - Start the tuning process
 439          *
 440          * @dev:        Device to start the tuning
 441          * @opcode:     Command opcode to send
 442          * @return 0 if OK, -ve on error
 443          */
 444         int (*execute_tuning)(struct udevice *dev, uint opcode);
 445 #endif
 446
 447 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 448         /**
 449          * wait_dat0() - wait until dat0 is in the target state
 450          *              (CLK must be running during the wait)
 451          *
 452          * @dev:        Device to check
 453          * @state:      target state
 454          * @timeout:    timeout in us
 455          * @return 0 if dat0 is in the target state, -ve on error
 456          */
 457         int (*wait_dat0)(struct udevice *dev, int state, int timeout);
 458 #endif
 459 };
 460
 461 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 462
 463 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 464                     struct mmc_data *data);
 465 int dm_mmc_set_ios(struct udevice *dev);
 466 void dm_mmc_send_init_stream(struct udevice *dev);
 467 int dm_mmc_get_cd(struct udevice *dev);
 468 int dm_mmc_get_wp(struct udevice *dev);
 469 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
 470 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
 471
 472 /* Transition functions for compatibility */
 473 int mmc_set_ios(struct mmc *mmc);
 474 void mmc_send_init_stream(struct mmc *mmc);
 475 int mmc_getcd(struct mmc *mmc);
 476 int mmc_getwp(struct mmc *mmc);
 477 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
 478 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
 479
 480 #else
 481 struct mmc_ops {
 482         int (*send_cmd)(struct mmc *mmc,
 483                         struct mmc_cmd *cmd, struct mmc_data *data);
 484         int (*set_ios)(struct mmc *mmc);
 485         int (*init)(struct mmc *mmc);
 486         int (*getcd)(struct mmc *mmc);
 487         int (*getwp)(struct mmc *mmc);
 488 };
 489 #endif
 490
 491 struct mmc_config {
 492         const char *name;
 493 #if !CONFIG_IS_ENABLED(DM_MMC)
 494         const struct mmc_ops *ops;
 495 #endif
 496         uint host_caps;
 497         uint voltages;
 498         uint f_min;
 499         uint f_max;
 500         uint b_max;
 501         unsigned char part_type;
 502 };
 503
 504 struct sd_ssr {
 505         unsigned int au;                /* In sectors */
 506         unsigned int erase_timeout;     /* In milliseconds */
 507         unsigned int erase_offset;      /* In milliseconds */
 508 };
 509
 510 enum bus_mode {
 511         MMC_LEGACY,
 512         SD_LEGACY,
 513         MMC_HS,
 514         SD_HS,
 515         MMC_HS_52,
 516         MMC_DDR_52,
 517         UHS_SDR12,
 518         UHS_SDR25,
 519         UHS_SDR50,
 520         UHS_DDR50,
 521         UHS_SDR104,
 522         MMC_HS_200,
 523         MMC_MODES_END
 524 };
 525
 526 const char *mmc_mode_name(enum bus_mode mode);
 527 void mmc_dump_capabilities(const char *text, uint caps);
 528
 529 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
 530 {
 531         if (mode == MMC_DDR_52)
 532                 return true;
 533 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 534         else if (mode == UHS_DDR50)
 535                 return true;
 536 #endif
 537         else
 538                 return false;
 539 }
 540
 541 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
 542                   MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
 543                   MMC_CAP(UHS_DDR50))
 544
 545 static inline bool supports_uhs(uint caps)
 546 {
 547 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 548         return (caps & UHS_CAPS) ? true : false;
 549 #else
 550         return false;
 551 #endif
 552 }
 553
 554 /*
 555  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 556  * with mmc_get_mmc_dev().
 557  *
 558  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 559  */
 560 struct mmc {
 561 #if !CONFIG_IS_ENABLED(BLK)
 562         struct list_head link;
 563 #endif
 564         const struct mmc_config *cfg;   /* provided configuration */
 565         uint version;
 566         void *priv;
 567         uint has_init;
 568         int high_capacity;
 569         bool clk_disable; /* true if the clock can be turned off */
 570         uint bus_width;
 571         uint clock;
 572         enum mmc_voltage signal_voltage;
 573         uint card_caps;
 574         uint host_caps;
 575         uint ocr;
 576         uint dsr;
 577         uint dsr_imp;
 578         uint scr[2];
 579         uint csd[4];
 580         uint cid[4];
 581         ushort rca;
 582         u8 part_support;
 583         u8 part_attr;
 584         u8 wr_rel_set;
 585         u8 part_config;
 586         uint tran_speed;
 587         uint legacy_speed; /* speed for the legacy mode provided by the card */
 588         uint read_bl_len;
 589 #if CONFIG_IS_ENABLED(MMC_WRITE)
 590         uint write_bl_len;
 591         uint erase_grp_size;    /* in 512-byte sectors */
 592 #endif
 593 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 594         uint hc_wp_grp_size;    /* in 512-byte sectors */
 595 #endif
 596 #if CONFIG_IS_ENABLED(MMC_WRITE)
 597         struct sd_ssr   ssr;    /* SD status register */
 598 #endif
 599         u64 capacity;
 600         u64 capacity_user;
 601         u64 capacity_boot;
 602         u64 capacity_rpmb;
 603         u64 capacity_gp[4];
 604 #ifndef CONFIG_SPL_BUILD
 605         u64 enh_user_start;
 606         u64 enh_user_size;
 607 #endif
 608 #if !CONFIG_IS_ENABLED(BLK)
 609         struct blk_desc block_dev;
 610 #endif
 611         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 612         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 613         char preinit;           /* start init as early as possible */
 614         int ddr_mode;
 615 #if CONFIG_IS_ENABLED(DM_MMC)
 616         struct udevice *dev;    /* Device for this MMC controller */
 617 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 618         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 619         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 620 #endif
 621 #endif
 622         u8 *ext_csd;
 623         u32 cardtype;           /* cardtype read from the MMC */
 624         enum mmc_voltage current_voltage;
 625         enum bus_mode selected_mode; /* mode currently used */
 626         enum bus_mode best_mode; /* best mode is the supported mode with the
 627                                   * highest bandwidth. It may not always be the
 628                                   * operating mode due to limitations when
 629                                   * accessing the boot partitions
 630                                   */
 631         u32 quirks;
 632 };
 633
 634 struct mmc_hwpart_conf {
 635         struct {
 636                 uint enh_start; /* in 512-byte sectors */
 637                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 638                 unsigned wr_rel_change : 1;
 639                 unsigned wr_rel_set : 1;
 640         } user;
 641         struct {
 642                 uint size;      /* in 512-byte sectors */
 643                 unsigned enhanced : 1;
 644                 unsigned wr_rel_change : 1;
 645                 unsigned wr_rel_set : 1;
 646         } gp_part[4];
 647 };
 648
 649 enum mmc_hwpart_conf_mode {
 650         MMC_HWPART_CONF_CHECK,
 651         MMC_HWPART_CONF_SET,
 652         MMC_HWPART_CONF_COMPLETE,
 653 };
 654
 655 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 656
 657 /**
 658  * mmc_bind() - Set up a new MMC device ready for probing
 659  *
 660  * A child block device is bound with the IF_TYPE_MMC interface type. This
 661  * allows the device to be used with CONFIG_BLK
 662  *
 663  * @dev:        MMC device to set up
 664  * @mmc:        MMC struct
 665  * @cfg:        MMC configuration
 666  * @return 0 if OK, -ve on error
 667  */
 668 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 669              const struct mmc_config *cfg);
 670 void mmc_destroy(struct mmc *mmc);
 671
 672 /**
 673  * mmc_unbind() - Unbind a MMC device's child block device
 674  *
 675  * @dev:        MMC device
 676  * @return 0 if OK, -ve on error
 677  */
 678 int mmc_unbind(struct udevice *dev);
 679 int mmc_initialize(bd_t *bis);
 680 int mmc_init(struct mmc *mmc);
 681 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
 682
 683 /**
 684  * mmc_of_parse() - Parse the device tree to get the capabilities of the host
 685  *
 686  * @dev:        MMC device
 687  * @cfg:        MMC configuration
 688  * @return 0 if OK, -ve on error
 689  */
 690 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
 691
 692 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 693
 694 /**
 695  * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
 696  *
 697  * @voltage:    The mmc_voltage to convert
 698  * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
 699  */
 700 int mmc_voltage_to_mv(enum mmc_voltage voltage);
 701
 702 /**
 703  * mmc_set_clock() - change the bus clock
 704  * @mmc:        MMC struct
 705  * @clock:      bus frequency in Hz
 706  * @disable:    flag indicating if the clock must on or off
 707  * @return 0 if OK, -ve on error
 708  */
 709 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
 710
 711 struct mmc *find_mmc_device(int dev_num);
 712 int mmc_set_dev(int dev_num);
 713 void print_mmc_devices(char separator);
 714
 715 /**
 716  * get_mmc_num() - get the total MMC device number
 717  *
 718  * @return 0 if there is no MMC device, else the number of devices
 719  */
 720 int get_mmc_num(void);
 721 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 722 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 723                       enum mmc_hwpart_conf_mode mode);
 724
 725 #if !CONFIG_IS_ENABLED(DM_MMC)
 726 int mmc_getcd(struct mmc *mmc);
 727 int board_mmc_getcd(struct mmc *mmc);
 728 int mmc_getwp(struct mmc *mmc);
 729 int board_mmc_getwp(struct mmc *mmc);
 730 #endif
 731
 732 int mmc_set_dsr(struct mmc *mmc, u16 val);
 733 /* Function to change the size of boot partition and rpmb partitions */
 734 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 735                                         unsigned long rpmbsize);
 736 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 737 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 738 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 739 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 740 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 741 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 742 /* Functions to read / write the RPMB partition */
 743 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 744 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 745 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 746                   unsigned short cnt, unsigned char *key);
 747 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 748                    unsigned short cnt, unsigned char *key);
 749 #ifdef CONFIG_CMD_BKOPS_ENABLE
 750 int mmc_set_bkops_enable(struct mmc *mmc);
 751 #endif
 752
 753 /**
 754  * Start device initialization and return immediately; it does not block on
 755  * polling OCR (operation condition register) status.  Then you should call
 756  * mmc_init, which would block on polling OCR status and complete the device
 757  * initializatin.
 758  *
 759  * @param mmc   Pointer to a MMC device struct
 760  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 761  */
 762 int mmc_start_init(struct mmc *mmc);
 763
 764 /**
 765  * Set preinit flag of mmc device.
 766  *
 767  * This will cause the device to be pre-inited during mmc_initialize(),
 768  * which may save boot time if the device is not accessed until later.
 769  * Some eMMC devices take 200-300ms to init, but unfortunately they
 770  * must be sent a series of commands to even get them to start preparing
 771  * for operation.
 772  *
 773  * @param mmc           Pointer to a MMC device struct
 774  * @param preinit       preinit flag value
 775  */
 776 void mmc_set_preinit(struct mmc *mmc, int preinit);
 777
 778 #ifdef CONFIG_MMC_SPI
 779 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 780 #else
 781 #define mmc_host_is_spi(mmc)    0
 782 #endif
 783 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 784
 785 void board_mmc_power_init(void);
 786 int board_mmc_init(bd_t *bis);
 787 int cpu_mmc_init(bd_t *bis);
 788 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 789 int mmc_get_env_dev(void);
 790
 791 /* Set block count limit because of 16 bit register limit on some hardware*/
 792 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 793 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 794 #endif
 795
 796 /**
 797  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 798  *
 799  * @mmc:        MMC device
 800  * @return block device if found, else NULL
 801  */
 802 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 803
 804 #endif /* _MMC_H_ */