NAND: add support for reading ONFI page table

[people/ms/u-boot.git] / README

diff --git a/README b/README
index a507a1f434b5e9e54f445fa05cdeeeb64098c8aa..21cd71b297854b36c8777d644b8790aa14a9be4b 100644 (file)
--- a/README
+++ b/README
@@ -319,6 +319,11 @@ The following options need to be configured:
                        CONFIG_SYS_PQ2FADS      - PQ2FADS-ZU or PQ2FADS-VR
                        CONFIG_SYS_8272ADS      - MPC8272ADS
 
+- Marvell Family Member
+               CONFIG_SYS_MVFS         - define it if you want to enable
+                                         multiple fs option at one time
+                                         for marvell soc family
+
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
                Define exactly one of
                CONFIG_MPC8240, CONFIG_MPC8245
@@ -675,7 +680,7 @@ The following options need to be configured:
                                          (requires CONFIG_CMD_I2C)
                CONFIG_CMD_SETGETDCR      Support for DCR Register access
                                          (4xx only)
-               CONFIG_CMD_SHA1           print sha1 memory digest
+               CONFIG_CMD_SHA1SUM        print sha1 memory digest
                                          (requires CONFIG_CMD_MEMORY)
                CONFIG_CMD_SOURCE         "source" command Support
                CONFIG_CMD_SPI          * SPI serial bus support
@@ -746,6 +751,10 @@ The following options need to be configured:
                CONFIG_PCA953X          - use NXP's PCA953X series I2C GPIO
                CONFIG_PCA953X_INFO     - enable pca953x info command
 
+               The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+               chip-ngpio pairs that tell the PCA953X driver the number of
+               pins supported by a particular chip.
+
                Note that if the GPIO device uses I2C, then the I2C interface
                must also be configured. See I2C Support, below.
 
@@ -861,6 +870,18 @@ The following options need to be configured:
                        Define this to use i/o functions instead of macros
                        (some hardware wont work with macros)
 
+               CONFIG_FTGMAC100
+               Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
+
+                       CONFIG_FTGMAC100_EGIGA
+                       Define this to use GE link update with gigabit PHY.
+                       Define this if FTGMAC100 is connected to gigabit PHY.
+                       If your system has 10/100 PHY only, it might not occur
+                       wrong behavior. Because PHY usually return timeout or
+                       useless data when polling gigabit status and gigabit
+                       control registers. This behavior won't affect the
+                       correctnessof 10/100 link speed update.
+
                CONFIG_SMC911X
                Support for SMSC's LAN911x and LAN921x chips
 
@@ -876,6 +897,18 @@ The following options need to be configured:
                        automatically converts one 32 bit word to two 16 bit
                        words you may also try CONFIG_SMC911X_32_BIT.
 
+               CONFIG_SH_ETHER
+               Support for Renesas on-chip Ethernet controller
+
+                       CONFIG_SH_ETHER_USE_PORT
+                       Define the number of ports to be used
+
+                       CONFIG_SH_ETHER_PHY_ADDR
+                       Define the ETH PHY's address
+
+                       CONFIG_SH_ETHER_CACHE_WRITEBACK
+                       If this option is set, the driver enables cache flush.
+
 - USB Support:
                At the moment only the UHCI host controller is
                supported (PIP405, MIP405, MPC5200); define
@@ -1632,6 +1665,11 @@ The following options need to be configured:
                SPI EEPROM, also an instance works with Crystal A/D and
                D/As on the SACSng board)
 
+               CONFIG_SH_SPI
+
+               Enables the driver for SPI controller on SuperH. Currently
+               only SH7757 is supported.
+
                CONFIG_SPI_X
 
                Enables extended (16-bit) SPI EEPROM addressing.
@@ -2364,11 +2402,11 @@ Configuration Settings:
 
 - CONFIG_ENV_MAX_ENTRIES
 
-        Maximum number of entries in the hash table that is used
-        internally to store the environment settings. The default
-        setting is supposed to be generous and should work in most
-        cases. This setting can be used to tune behaviour; see
-        lib/hashtable.c for details.
+       Maximum number of entries in the hash table that is used
+       internally to store the environment settings. The default
+       setting is supposed to be generous and should work in most
+       cases. This setting can be used to tune behaviour; see
+       lib/hashtable.c for details.
 
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
@@ -2686,7 +2724,7 @@ Low Level (hardware related) configuration options:
                area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
                CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
                data is located at the end of the available space
-               (sometimes written as (CONFIG_SYS_INIT_RAM_END -
+               (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
                CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
                below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
                CONFIG_SYS_GBL_DATA_OFFSET) downward.
@@ -2771,6 +2809,24 @@ Low Level (hardware related) configuration options:
                Disable PCI-Express on systems where it is supported but not
                required.
 
+- CONFIG_SYS_SRIO:
+               Chip has SRIO or not
+
+- CONFIG_SRIO1:
+               Board has SRIO 1 port available
+
+- CONFIG_SRIO2:
+               Board has SRIO 2 port available
+
+- CONFIG_SYS_SRIOn_MEM_VIRT:
+               Virtual Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_PHYS:
+               Physical Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_SIZE:
+               Size of SRIO port 'n' memory region
+
 - CONFIG_SPD_EEPROM
                Get DDR timing information from an I2C EEPROM. Common
                with pluggable memory modules such as SODIMMs
@@ -2836,19 +2892,17 @@ Low Level (hardware related) configuration options:
                globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-- CONFIG_SKIP_RELOCATE_UBOOT
+               [ARM only] If this variable is defined, then certain
+               low level initializations (like setting up the memory
+               controller) are omitted and/or U-Boot does not
+               relocate itself into RAM.
 
-               [ARM only] If these variables are defined, then
-               certain low level initializations (like setting up
-               the memory controller) are omitted and/or U-Boot does
-               not relocate itself into RAM.
-               Normally these variables MUST NOT be defined. The
-               only exception is when U-Boot is loaded (to RAM) by
-               some other boot loader or by a debugger which
-               performs these initializations itself.
+               Normally this variable MUST NOT be defined. The only
+               exception is when U-Boot is loaded (to RAM) by some
+               other boot loader or by a debugger which performs
+               these initializations itself.
 
 - CONFIG_PRELOADER
-
                Modifies the behaviour of start.S when compiling a loader
                that is executed before the actual U-Boot. E.g. when
                compiling a NAND SPL.