arcv2: Set IOC aperture so it covers available DDR

[people/ms/u-boot.git] / README

diff --git a/README b/README
index 4819696deb64d0b34b1b3fac1337b456662733f7..2abba91b6475d0781e1791336f6e5a37d3966cbc 100644 (file)
--- a/README
+++ b/README
@@ -608,10 +608,6 @@ The following options need to be configured:
                 * Adds the "fdt" command
                 * The bootm command automatically updates the fdt
 
                 * Adds the "fdt" command
                 * The bootm command automatically updates the fdt
 

-               OF_CPU - The proper name of the cpus node (only required for
-                       MPC512X and MPC5xxx based boards).
-               OF_SOC - The proper name of the soc node (only required for
-                       MPC512X and MPC5xxx based boards).

                OF_TBCLK - The timebase frequency.
                OF_STDOUT_PATH - The path to the console device
 
                OF_TBCLK - The timebase frequency.
                OF_STDOUT_PATH - The path to the console device
 


@@ -700,14 +696,6 @@ The following options need to be configured:
                Select one of the baudrates listed in
                CONFIG_SYS_BAUDRATE_TABLE, see below.
 
                Select one of the baudrates listed in
                CONFIG_SYS_BAUDRATE_TABLE, see below.
 

-- Console Rx buffer length
-               With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
-               the maximum receive buffer length for the SMC.
-               This option is actual only for 82xx possible.
-               If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
-               must be defined, to setup the maximum idle timeout for
-               the SMC.
-

 - Autoboot Command:
                CONFIG_BOOTCOMMAND
                Only needed when CONFIG_BOOTDELAY is enabled;
 - Autoboot Command:
                CONFIG_BOOTCOMMAND
                Only needed when CONFIG_BOOTDELAY is enabled;


@@ -937,11 +925,9 @@ The following options need to be configured:
                CONFIG_WATCHDOG
                If this variable is defined, it enables watchdog
                support for the SoC. There must be support in the SoC
                CONFIG_WATCHDOG
                If this variable is defined, it enables watchdog
                support for the SoC. There must be support in the SoC

-               specific code for a watchdog. For the 8260
-               CPUs, the SIU Watchdog feature is enabled in the SYPCR
-               register.  When supported for a specific SoC is
-               available, then no further board specific code should
-               be needed to use it.
+               specific code for a watchdog. When supported for a
+               specific SoC is available, then no further board specific
+               code should be needed to use it.

 
                CONFIG_HW_WATCHDOG
                When using a watchdog circuitry external to the used
 
                CONFIG_HW_WATCHDOG
                When using a watchdog circuitry external to the used


@@ -1242,7 +1228,7 @@ The following options need to be configured:
 
 - USB Support:
                At the moment only the UHCI host controller is
 
 - USB Support:
                At the moment only the UHCI host controller is

-               supported (PIP405, MIP405, MPC5200); define
+               supported (PIP405, MIP405); define

                CONFIG_USB_UHCI to enable it.
                define CONFIG_USB_KEYBOARD to enable the USB Keyboard
                and define CONFIG_USB_STORAGE to enable the USB
                CONFIG_USB_UHCI to enable it.
                define CONFIG_USB_KEYBOARD to enable the USB Keyboard
                and define CONFIG_USB_STORAGE to enable the USB


@@ -1250,19 +1236,6 @@ The following options need to be configured:
                Note:
                Supported are USB Keyboards and USB Floppy drives
                (TEAC FD-05PUB).
                Note:
                Supported are USB Keyboards and USB Floppy drives
                (TEAC FD-05PUB).

-               MPC5200 USB requires additional defines:
-                       CONFIG_USB_CLOCK
-                               for 528 MHz Clock: 0x0001bbbb
-                       CONFIG_PSC3_USB
-                               for USB on PSC3
-                       CONFIG_USB_CONFIG
-                               for differential drivers: 0x00001000
-                               for single ended drivers: 0x00005000
-                               for differential drivers on PSC3: 0x00000100
-                               for single ended drivers on PSC3: 0x00004100
-                       CONFIG_SYS_USB_EVENT_POLL
-                               May be defined to allow interrupt polling
-                               instead of using asynchronous interrupts

 
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.
 
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.


@@ -1904,12 +1877,6 @@ The following options need to be configured:
                In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
                with a list of GPIO LEDs that have inverted polarity.
 
                In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
                with a list of GPIO LEDs that have inverted polarity.
 

-- CAN Support: CONFIG_CAN_DRIVER
-
-               Defining CONFIG_CAN_DRIVER enables CAN driver support
-               on those systems that support this (optional)
-               feature.
-

 - I2C Support: CONFIG_SYS_I2C
 
                This enable the NEW i2c subsystem, and will allow you to use
 - I2C Support: CONFIG_SYS_I2C
 
                This enable the NEW i2c subsystem, and will allow you to use


@@ -2108,12 +2075,6 @@ The following options need to be configured:
 
                eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
 
 
                eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
 

-               I2C_PORT
-
-               (Only for MPC8260 CPU). The I/O port to use (the code
-               assumes both bits are on the same port). Valid values
-               are 0..3 for ports A..D.
-

                I2C_ACTIVE
 
                The code necessary to make the I2C data line active
                I2C_ACTIVE
 
                The code necessary to make the I2C data line active


@@ -2402,7 +2363,7 @@ The following options need to be configured:
 
                        IVMS8, IVML24, SPD8xx,
                        HERMES, IP860, RPXlite, LWMON,
 
                        IVMS8, IVML24, SPD8xx,
                        HERMES, IP860, RPXlite, LWMON,

-                       FLAGADM, TQM8260
+                       FLAGADM

 
 - Access to physical memory region (> 4GB)
                Some basic support is provided for operations on memory not
 
 - Access to physical memory region (> 4GB)
                Some basic support is provided for operations on memory not


@@ -2573,12 +2534,6 @@ The following options need to be configured:
                Define this option to include a destructive SPI flash
                test ('sf test').
 
                Define this option to include a destructive SPI flash
                test ('sf test').
 

-               CONFIG_SF_DUAL_FLASH            Dual flash memories
-
-               Define this option to use dual flash support where two flash
-               memories can be connected with a given cs line.
-               Currently Xilinx Zynq qspi supports these type of connections.
-

 - SystemACE Support:
                CONFIG_SYSTEMACE
 
 - SystemACE Support:
                CONFIG_SYSTEMACE
 


@@ -3860,16 +3815,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
          set. If this value is set, it must be set to the same value as
          CONFIG_ENV_SIZE.
 
          set. If this value is set, it must be set to the same value as
          CONFIG_ENV_SIZE.
 

-- CONFIG_SYS_SPI_INIT_OFFSET
-
-       Defines offset to the initial SPI buffer area in DPRAM. The
-       area is used at an early stage (ROM part) if the environment
-       is configured to reside in the SPI EEPROM: We need a 520 byte
-       scratch DPRAM area. It is used between the two initialization
-       calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
-       to be a good choice since it makes it far enough from the
-       start of the data area as well as from the stack pointer.
-

 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_f()
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_f()


@@ -3923,13 +3868,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_CACHELINE_SIZE:
                Cache Line Size of the CPU.
 
 - CONFIG_SYS_CACHELINE_SIZE:
                Cache Line Size of the CPU.
 

-- CONFIG_SYS_DEFAULT_IMMR:
-               Default address of the IMMR after system reset.
-
-               Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
-               and RPXsuper) to be able to adjust the position of
-               the IMMR register after a reset.
-

 - CONFIG_SYS_CCSRBAR_DEFAULT:
                Default (power-on reset) physical address of CCSR on Freescale
                PowerPC SOCs.
 - CONFIG_SYS_CCSRBAR_DEFAULT:
                Default (power-on reset) physical address of CCSR on Freescale
                PowerPC SOCs.


@@ -3938,9 +3876,6 @@ Low Level (hardware related) configuration options:
                Virtual address of CCSR.  On a 32-bit build, this is typically
                the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 
                Virtual address of CCSR.  On a 32-bit build, this is typically
                the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 

-               CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
-               for cross-platform code that uses that macro instead.
-

 - CONFIG_SYS_CCSRBAR_PHYS:
                Physical address of CCSR.  CCSR can be relocated to a new
                physical address, if desired.  In this case, this macro should
 - CONFIG_SYS_CCSRBAR_PHYS:
                Physical address of CCSR.  CCSR can be relocated to a new
                physical address, if desired.  In this case, this macro should


@@ -4016,8 +3951,6 @@ Low Level (hardware related) configuration options:
                sequences.
 
                U-Boot uses the following memory types:
                sequences.
 
                U-Boot uses the following memory types:

-               - MPC8260: IMMR (internal memory of the CPU)
-               - MPC824X: data cache

                - PPC4xx:  data cache
 
 - CONFIG_SYS_GBL_DATA_OFFSET:
                - PPC4xx:  data cache
 
 - CONFIG_SYS_GBL_DATA_OFFSET:


@@ -4038,16 +3971,6 @@ Low Level (hardware related) configuration options:
                point to an otherwise UNUSED address space between
                the top of RAM and the start of the PCI space.
 
                point to an otherwise UNUSED address space between
                the top of RAM and the start of the PCI space.
 

-- CONFIG_SYS_SIUMCR:   SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR:    System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR:    Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR:    Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR:   PLL, Low-Power, and Reset Control Register (15-30)
-

 - CONFIG_SYS_SCCR:     System Clock and reset Control Register (15-27)
 
 - CONFIG_SYS_OR_TIMING_SDRAM:
 - CONFIG_SYS_SCCR:     System Clock and reset Control Register (15-27)
 
 - CONFIG_SYS_OR_TIMING_SDRAM:


@@ -4056,8 +3979,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_MAMR_PTA:
                periodic timer for refresh
 
 - CONFIG_SYS_MAMR_PTA:
                periodic timer for refresh
 

-- CONFIG_SYS_DER:      Debug Event Register (37-47)
-

 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,


@@ -4069,27 +3990,6 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
                Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
                Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 

-- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
-  CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
-               Machine Mode Register and Memory Periodic Timer
-               Prescaler definitions (SDRAM timing)
-
-- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8260 only)
-               Offset of the bootmode word in DPRAM used by post
-               (Power On Self Tests). This definition overrides
-               #define'd default value in commproc.h resp.
-               cpm_8260.h.
-
-- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
-  CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
-  CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
-  CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
-  CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
-  CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
-  CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
-  CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
-               Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
-

 - CONFIG_PCI_DISABLE_PCIE:
                Disable PCI-Express on systems where it is supported but not
                required.
 - CONFIG_PCI_DISABLE_PCIE:
                Disable PCI-Express on systems where it is supported but not
                required.


@@ -5710,9 +5610,9 @@ configuration for CS0# this is a mirror of the on board Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs

-which provide such a feature like MPC8xx or MPC8260), or in a locked
-part of the data cache. After that, U-Boot initializes the CPU core,
-the caches and the SIU.
+which provide such a feature like), or in a locked part of the data
+cache. After that, U-Boot initializes the CPU core, the caches and
+the SIU.

 
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries
 
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries