rockchip: firefly-rk3399: dts: enable sdmmc device

[people/ms/u-boot.git] / README

diff --git a/README b/README
index da9d4726c88ee8e1439b4e15ebeb29181131abd7..ee35dec5b5c912ce34e7855f24a7f76680aa507e 100644 (file)
--- a/README
+++ b/README
@@ -324,9 +324,6 @@ The following options need to be configured:
                                          multiple fs option at one time
                                          for marvell soc family
 
-- 8xx CPU Options: (if using an MPC8xx CPU)
-               CONFIG_8xx_GCLK_FREQ    - CPU clock
-
 - 85xx CPU Options:
                CONFIG_SYS_PPC64
 
@@ -690,29 +687,10 @@ The following options need to be configured:
                Define this variable to enable hw flow control in serial driver.
                Current user of this option is drivers/serial/nsl16550.c driver
 
-- Console Interface:
-               Depending on board, define exactly one serial port
-               (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2),
-               or switch off the serial console by defining
-               CONFIG_8xx_CONS_NONE
-
-               Note: if CONFIG_8xx_CONS_NONE is defined, the serial
-               port routines must be defined elsewhere
-               (i.e. serial_init(), serial_getc(), ...)
-
 - Console Baudrate:
                CONFIG_BAUDRATE - in bps
                Select one of the baudrates listed in
                CONFIG_SYS_BAUDRATE_TABLE, see below.
-               CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
-
-- Console Rx buffer length
-               With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
-               the maximum receive buffer length for the SMC.
-               This option is actual only for 8xx possible.
-               If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
-               must be defined, to setup the maximum idle timeout for
-               the SMC.
 
 - Autoboot Command:
                CONFIG_BOOTCOMMAND
@@ -3989,16 +3967,6 @@ Low Level (hardware related) configuration options:
                point to an otherwise UNUSED address space between
                the top of RAM and the start of the PCI space.
 
-- CONFIG_SYS_SIUMCR:   SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR:    System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR:    Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR:    Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR:   PLL, Low-Power, and Reset Control Register (15-30)
-
 - CONFIG_SYS_SCCR:     System Clock and reset Control Register (15-27)
 
 - CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4007,8 +3975,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_MAMR_PTA:
                periodic timer for refresh
 
-- CONFIG_SYS_DER:      Debug Event Register (37-47)
-
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
@@ -4094,21 +4060,6 @@ Low Level (hardware related) configuration options:
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.
 
-- CONFIG_ETHER_ON_FEC[12]
-               Define to enable FEC[12] on a 8xx series processor.
-
-- CONFIG_FEC[12]_PHY
-               Define to the hardcoded PHY address which corresponds
-               to the given FEC; i. e.
-                       #define CONFIG_FEC1_PHY 4
-               means that the PHY with address 4 is connected to FEC1
-
-               When set to -1, means to probe for first available.
-
-- CONFIG_FEC[12]_PHY_NORXERR
-               The PHY does not have a RXERR line (RMII only).
-               (so program the FEC to ignore it).
-
 - CONFIG_RMII
                Enable RMII mode for all FECs.
                Note that this is a global option, we can't