arm: mxs: Add debug outputs and comments to mxs SPL source files

[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / spl_mem_init.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 97ef67d8c5843b06fcd6c7d903cd3d4cb21d976b..a744e5d4990a9c4776080293781393257df4bac5 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -92,6 +92,7 @@ static uint32_t dram_vals[] = {
 
 __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
+       debug("SPL: Using default SDRAM parameters\n");
 }
 
 #ifdef CONFIG_MX28
@@ -99,8 +100,10 @@ static void initialize_dram_values(void)
 {
        int i;
 
+       debug("SPL: Setting mx28 board specific SDRAM parameters\n");
        mxs_adjust_memory_params(dram_vals);
 
+       debug("SPL: Applying SDRAM parameters\n");
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
                writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
@@ -109,6 +112,7 @@ static void initialize_dram_values(void)
 {
        int i;
 
+       debug("SPL: Setting mx23 board specific SDRAM parameters\n");
        mxs_adjust_memory_params(dram_vals);
 
        /*
@@ -120,6 +124,7 @@ static void initialize_dram_values(void)
         * HW_DRAM_CTL8 is setup as the last element.
         * So skip the initialization of these HW_DRAM_CTL registers.
         */
+       debug("SPL: Applying SDRAM parameters\n");
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
                if (i == 8 || i == 27 || i == 28 || i == 35)
                        continue;
@@ -146,6 +151,8 @@ static void mxs_mem_init_clock(void)
        const unsigned char divider = 21;
 #endif
 
+       debug("SPL: Initialising FRAC0\n");
+
        /* Gate EMI clock */
        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
@@ -170,6 +177,7 @@ static void mxs_mem_init_clock(void)
                &clkctrl_regs->hw_clkctrl_clkseq_clr);
 
        early_delay(10000);
+       debug("SPL: FRAC0 Initialised\n");
 }
 
 static void mxs_mem_setup_cpu_and_hbus(void)
@@ -177,6 +185,8 @@ static void mxs_mem_setup_cpu_and_hbus(void)
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
+       debug("SPL: Setting CPU and HBUS clock frequencies\n");
+
        /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
         * and ungate CPU clock */
        writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
@@ -209,6 +219,8 @@ static void mxs_mem_setup_vdda(void)
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
 
+       debug("SPL: Configuring VDDA\n");
+
        writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
                (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
                POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
@@ -240,6 +252,8 @@ static void mx23_mem_setup_vddmem(void)
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
 
+       debug("SPL: Setting mx23 VDDMEM\n");
+
        /* We must wait before and after disabling the current limiter! */
        early_delay(10000);
 
@@ -252,6 +266,8 @@ static void mx23_mem_setup_vddmem(void)
 
 static void mx23_mem_init(void)
 {
+       debug("SPL: Initialising mx23 SDRAM Controller\n");
+
        /*
         * Reset/ungate the EMI block. This is essential, otherwise the system
         * suffers from memory instability. This thing is mx23 specific and is
@@ -297,6 +313,8 @@ static void mx28_mem_init(void)
        struct mxs_pinctrl_regs *pinctrl_regs =
                (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
+       debug("SPL: Initialising mx28 SDRAM Controller\n");
+
        /* Set DDR2 mode */
        writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
                &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);