arm: ls102x: add get_svr and IS_SVR_REV helper

[people/ms/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / cpu.c

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index e2eb5f383a4a34b6de8bc665f98f676a107ca0da..2f0df65582893356117c13841f593ccdefc8021d 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -218,6 +218,14 @@ void enable_caches(void)
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
+
+uint get_svr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       return in_be32(&gur->svr);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -301,6 +309,7 @@ int arch_cpu_init(void)
        void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
        void *rcpm2_base =
                (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+       struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
        u32 state;
 
        /*
@@ -328,6 +337,8 @@ int arch_cpu_init(void)
         */
        fsl_epu_clean(epu_base);
 
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
        return 0;
 }
 
@@ -369,3 +380,13 @@ void reset_cpu(ulong addr)
                 */
        }
 }
+
+void arch_preboot_os(void)
+{
+       unsigned long ctrl;
+
+       /* Disable PL1 Physical Timer */
+       asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+       ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+       asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}